Introduce bindings for RPMh regulator devices found on some
Qualcomm Technlogies, Inc. SoCs.  These devices allow a given
processor within the SoC to make PMIC regulator requests which
are aggregated within the RPMh hardware block along with requests
from other processors in the SoC to determine the final PMIC
regulator hardware state.
Signed-off-by: NDavid Collins <collinsd@codeaurora.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

Y Soft is headquartered in the Czech Republic and it is a worldwide
provider of enterprise office solutions for print management.
Signed-off-by: NMichal Vokáč <michal.vokac@ysoft.com>
Signed-off-by: NRob Herring <robh@kernel.org>

Add DT bindings for SPI controller implemented in UniPhier SoCs.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NKeiji Hayashibara <hayashibara.keiji@socionext.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

Commit 59b356ff ("mtd: m25p80: restore the status of SPI flash when
exiting") is the latest from a long history of attempts to add reboot
handling to handle stateful addressing modes on SPI flash. Some prior
mostly-related discussions:

http://lists.infradead.org/pipermail/linux-mtd/2013-March/046343.html
[PATCH 1/3] mtd: m25p80: utilize dedicated 4-byte addressing commands

http://lists.infradead.org/pipermail/barebox/2014-September/020682.html
[RFC] MTD m25p80 3-byte addressing and boot problem

http://lists.infradead.org/pipermail/linux-mtd/2015-February/057683.html
[PATCH 2/2] m25p80: if supported put chip to deep power down if not used

Previously, attempts to add reboot-time software reset handling were
rejected, but the latest attempt was not.

Quick summary of the problem:
Some systems (e.g., boot ROM or bootloader) assume that they can read
initial boot code from their SPI flash using 3-byte addressing. If the
flash is left in 4-byte mode after reset, these systems won't boot. The
above patch provided a shutdown/remove hook to attempt to reset the
addressing mode before we reboot. Notably, this patch misses out on
huge classes of unexpected reboots (e.g., crashes, watchdog resets).

Unfortunately, it is essentially impossible to solve this problem 100%:
if your system doesn't know how to reset the SPI flash to power-on
defaults at initialization time, no amount of software can really rescue
you -- there will always be a chance of some unexpected reset that
leaves your flash in an addressing mode that your boot sequence didn't
expect.

While it is not directly harmful to perform hacks like the
aforementioned commit on all 4-byte addressing flash, a
properly-designed system should not need the hack -- and in fact,
providing this hack may mask the fact that a given system is indeed
broken. So this patch attempts to apply this unsound hack more narrowly,
providing a strong suggestion to developers and system designers that
this is truly a hack. With luck, system designers can catch their errors
early on in their development cycle, rather than applying this hack long
term. But apparently enough systems are out in the wild that we still
have to provide this hack.

Document a new device tree property to denote systems that do not have a
proper hardware (or software) reset mechanism, and apply the hack (with
a loud warning) only in this case.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NBoris Brezillon <boris.brezillon@bootlin.com>

The integration of the Designware SPI controller on Microsemi SoCs requires
an extra register set to be able to give the IP control of the SPI
interface.

Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

This patch adds mask parameter to define IRQ mux field.
This field could vary depend of IRQ mux selection register.
This parameter is needed if the mask is different of 0xf.
Signed-off-by: NLudovic Barre <ludovic.barre@st.com>
Acked-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

In case the exti line is not in line with the bank number (that is the case
when there is an hole between two banks, for example GPIOK and then GPIOZ),
use "st,bank-ioport" DT property to get the right exti line.
Signed-off-by: NAmelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The binding for the USB PHY went thru before the driver. However the
new version of the driver now use the PHY core support for reset, and
this expect the reset to be named "phy". So remove the "usb-" prefix
from the the reset names.
Signed-off-by: NAlban Bedel <albeu@free.fr>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NPaul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/15282/
Cc: linux-kernel@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Antony Pavlov <antonynpavlov@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org

This patch adds bindings of new "System Timer" on Mediatek SoCs.

Remove RTC clock in the same time because it is not used by
both "General Purpose Timer" and "System Timer" now.
Signed-off-by: NStanley Chu <stanley.chu@mediatek.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

'interrupt-parent' is often documented as part of define bindings, but
it is really outside the scope of a device binding. It's never required
in a given node as it is often inherited from a parent node. Or it can
be implicit if a parent node is an 'interrupt-controller' node. So
remove it from all the binding files.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: NRob Herring <robh@kernel.org>

This fixes a spelling mistake.
Signed-off-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NRob Herring <robh@kernel.org>

Documentation was already saying that fixed and dynamic partitioning can
be mixed but was missing a clear description and examples. This commit
adds a proper documentation of how descriptions can be nested and how
layouts can be mixed.

This addition is important for partitions that contain subpartitions.
In such cases partitions have to be properly described in order to let
system handle them correctly.

Depending on situation, nesting descriptions may provide more accurate
logic/structure and/or allow mixing partitioning types (various
"compatible" values).
Signed-off-by: NRafał Miłecki <rafal@milecki.pl>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NBoris Brezillon <boris.brezillon@bootlin.com>

The S5Pv210 external wakeup interrupts differ from Exynos therefore
separate compatible is needed.  Duplicate existing flavor specific data
from exynos4210_wkup_irq_chip and add new compatible for S5Pv210.
At this point this new compatible does not bring anything new and works
exactly as existing "samsung,exynos4210-wakeup-eint".
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <snawrocki@kernel.org>
Acked-by: NTomasz Figa <tomasz.figa@gmail.com>
Tested-by: NMarek Szyprowski <m.szyprowski@samsung.com>

ARMv7 hardware (S5Pv210 and Exynos SoCs) provides only 32 external
interrupts which can wakeup device from deep sleep modes.  On S5Pv210
these are gph0-gph3.  On all ARMv7 Exynos designs these are gpx0-gpx3.
There is only one 32-bit register for controlling the external wakeup
interrupt mask (masking and unmasking waking capability of these
interrupts).

This lead to implementation in pinctrl driver and machine code which was
using static memory for storing the mask value and not caring about
multiple devices of pin controller... because only one pin controller
device will be handling this.

Since each pin controller node in Device Tree maps onto one device, this
corresponds to hidden assumption in parsing the Device Tree: external
wakeup interrupts can be defined only once.  Make this assumption an
explicit requirement.

ARMv8 Exynos5433 and Exynos7 bring additional 32 external wakeup
interrupts (up to 64 total, banks gpa0-gpa3 and gpf1-gpf5) and another
32-bit wide register for controlling them.  Existing code does not
support it but anyway these additional interrupts will be belonging to
the same pin controller device/node.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <snawrocki@kernel.org>
Acked-by: NTomasz Figa <tomasz.figa@gmail.com>
Tested-by: NMarek Szyprowski <m.szyprowski@samsung.com>

Added support for the CPCAP power management regulator functions on
Tegra based Motorola Xoom devices.
Added sw2_sw4 value tables, which provide power to the Tegra core and
aux devices.
Added the Xoom init tables and device tree compatibility match.
Signed-off-by: NPeter Geis <pgwipeout@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

This binding is used to keep the backward compatibility with the current
dtb's [1]. The binding informs the driver that the unused switch regulators
can be disabled.
If it is not specified, the driver doesn't disable the switch regulators.

[1] https://patchwork.kernel.org/patch/10490381/Signed-off-by: NMarco Felsch <m.felsch@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

Add device binding documentation for Qualcomm Technology Inc's RPMH RSC
driver. The driver is used for communicating resource state requests for
shared resources.

Cc: devicetree@vger.kernel.org
Signed-off-by: NLina Iyer <ilina@codeaurora.org>
Reviewed-by: NRob Herring <robh@kernel.org>
[rplsssn@codeaurora.org: minor order correction for TCS type]
Signed-off-by: NRaju P.L.S.S.S.N <rplsssn@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Documentation for last level cache controller device tree bindings,
client bindings usage examples.
Signed-off-by: NChannagoud Kadabi <ckadabi@codeaurora.org>
Signed-off-by: NRishabh Bhatnagar <rishabhb@codeaurora.org>
Reviewed-by: NEvan Green <evgreen@chromium.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Commit 34962fb8 ("docs: Fix more broken references") replaced the
broken reference to rockchip,dwc3-usb-phy.txt binding for the Qualcomm
DWC3 binding (qcom-dwc3-usb-phy.txt). That's wrong, so replace that
reference for the correct ones.

Fixes: 34962fb8 ("docs: Fix more broken references")
Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NRob Herring <robh@kernel.org>

Document R-Car V3H (AKA R8A77980) SoC bindings.
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Renesas RZ/G SoC have the R-Car gen2 compatible IRQC interrupt
controllers. Document RZ/G1C (also known as R8A77470) SoC bindings.
Reviewed-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

The interrupt controller of the JZ4725B works the same way as the other
JZ SoCs from Ingenic; so we just add a new compatible string.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Commit 30f9f2fb ("mtd: denali: add a DT driver") supported the
clock enablement, but did not document it in the DT binding.

In addition to the existing clock, this commit adds more clocks based
on the IP specification.

According to the Denali User's Guide, this IP needs three clocks:

 - clk: controller core clock

 - clk_x: bus interface clock

 - ecc_clk: clock at which ECC circuitry is run

The driver should accept the current single clock for the backward
compatibility, but the DT binding should represent the real hardware,
and future platforms must follow this.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NBoris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Add bindings for SPI NAND chips.
Signed-off-by: NBoris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

1. If nand-ecc-strength specified in DT, then controller will use
   this ECC strength otherwise ECC strength will be calculated
   according to chip requirement and available OOB size.

2. QCOM NAND controller supports only one step size (512 bytes) but
   nand-ecc-step-size is required property in DT. This DT property
   can be removed and ecc step size can be assigned in driver with
   512 bytes value.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Add "rockchip,px30-spi", "rockchip,rk3066-spi" for spi on px30 platform.
Signed-off-by: NLiang Chen <cl@rock-chips.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Commit 34962fb8 ("docs: Fix more broken references") replaced the
broken reference to rockchip,dwc3-usb-phy.txt binding for the Qualcomm
DWC3 binding (qcom-dwc3-usb-phy.txt). That's wrong, so replace that
reference for the correct ones.

Fixes: 34962fb8 ("docs: Fix more broken references")
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

Add the wlf,csnaddr-pd property to allow the CS/Addr pull-down to be
controlled from the device tree.
Signed-off-by: NAnthony Brandon <anthony@amarulasolutions.com>
Acked-by: NCharles Keepax <ckeepax@opensource.cirrus.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NRob Herring <robh@kernel.org>

Add the wlf,spkmode-pu property to control the Speaker Mode pull-up from
the device tree.
Signed-off-by: NAnthony Brandon <anthony@amarulasolutions.com>
Acked-by: NCharles Keepax <ckeepax@opensource.cirrus.com>
Acked-by: NCharles Keepax <ckeepax@opensource.cirrus.com>
Acked-by: NCharles Keepax <ckeepax@opensource.cirrus.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NRob Herring <robh@kernel.org>

Add as370 to existing berlin pinctrl device tree binding.
Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This adds the binding for the i.MX8MQ pin controller, in the same
fashion as earlier i.MX SoCs.
Signed-off-by: NAbel Vesa <abel.vesa@nxp.com>
Acked-by: NDong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add support for the drive strength configuration. Usually, this value is
expressed in mA. Since the numeric value depends on VDDIOP voltage, a
value we can't retrieve at runtime, the controller uses low, medium and
high to define the drive strength.

The PIO controller accepts two values for the low drive configuration: 0
and 1. Most of the time, we don't care about the drive strength. So we
keep the default value which is 0. The drive strength is advertised
through the sysfs only when it has been explicitly set in the device
tree i.e. if its value is different from 0.
Signed-off-by: NLudovic Desroches <ludovic.desroches@microchip.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add DT bindings for regulators implemented in UniPhier SoCs.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Some SoCs (like i.MX53) need to specify the SRAM clock in the
device tree via the clocks property.

Add an entry to the optional property section.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NRob Herring <robh@kernel.org>

"AsusTek Computer Inc. is a Taiwanese multinational computer
and phone hardware and electronics company headquartered
in Beitou District, Taipei, Taiwan." - Wikipedia.org

Website: https://www.asus.com

The prefix is already in use by at least 5 ARM boards
Signed-off-by: NLuis Araneda <luaraneda@gmail.com>
Signed-off-by: NRob Herring <robh@kernel.org>

Add the device-tree binding definition for the AST2400
and AST2500 coprocessor interrupt controller
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NRob Herring <robh@kernel.org>

The device can optionally supply an interrupt, hence document that.

Add required GPIO properties to the example (extracted from a patch by
Wolfram Sang).
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NRob Herring <robh@kernel.org>

Bitmain (https://www.bitmain.com) is a vendor of cryptocurrency
hardware.
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Signed-off-by: NRob Herring <robh@kernel.org>

Trivial fix to spelling mistake in tilcdc.txt devicetree documentation.
Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: NRob Herring <robh@kernel.org>

Added device tree binding documentation for Nuvoton BMC
NPCM7xx Pulse Width Modulation (PWM)  and Fan tach controller.
The Nuvoton BMC NPCM7XX supports 8 PWM controller outputs
and 16 Fan tachometer controller inputs.
Signed-off-by: NTomer Maimon <tmaimon77@gmail.com>
Reviewed-by: NRob Herring <robh@kernel.org>
[groeck: Fixed whitespace errors noticed by git]
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>