The SPICC controller has dedicated SPI pins, this patchs add the pins
definition in the GXL pinctrl driver.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

We use well known standard names for functions that have name, such as
I2C, SPI, SPDIF, etc..

Fix the function name of SPDIF, which was named OWA (One Wire Audio)
based on Allwinner datasheets.

Fixes: 4730f33f ("pinctrl: sunxi: add allwinner A83T PIO controller
		      support")
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

There was no entry for the mvebu pinctrl drivers. As they are tightly
linked to the SoCs and there is a lot of common code to support the
various pinctrl of each SoCs, then add a new entry for the mvebu
maintainers.
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Each text file under Documentation follows a different
format. Some doesn't even have titles!

Change its representation to follow the adopted standard,
using ReST markups for it to be parseable by Sphinx.

This document is almost following the standard stile.

There are only two things to adjust on it:

- promote the level of the document title;
- mark literal blocks as such.
Signed-off-by: NMauro Carvalho Chehab <mchehab@s-opensource.com>
[Fix some indentations]
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The comment does not match the driver, which actually supports
automatic assignment. Fix this by updating the comment.
Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The driver supports using mcp23xxx as interrupt controller, so
let's drop all comments stating otherwise.
Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This moves irq property handling from spi/i2c specific code into
the generic mcp23s08_probe_one. This is possible because the
device properties are named equally.

As a side-effect this drops support for setting the properties via
pdata, which has no mainline users. If boardcode wants to enable
the chip as interrupt controller it can attach the device properties
instead.
Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Simplify spi pdata handling, so that it uses pdata when available
and falls back to reading device properties otherwise.
Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Simplify i2c pdata handling, so that it uses pdata when available
and falls back to reading device properties otherwise.
Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Switching to devm_gpiochip_add_data simplifies the driver's
cleanup routine and safes a few loc.
Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Let's remove a few lines of code by using managed memory for mcp
variable.
Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

i2c-core and spi-core already assign the irq, so we
can drop the additional call from the mcp driver.
Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The driver compiles & works perfectly fine without OF_GPIO on x86,
so lets drop the dependency.
Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Instead of using custom caching, this switches to regmap based
caching. Before the conversion the debugfs file used uncached
values, so that it was easily possible to see power-loss related
problems. The new code will check and recover at this place.

The patch will also ensure, that irqs are not cleared by checking
register status in debugfs.
Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

mcp23s08 support configuration of the pullups using the
pinconf framework. This removes the custom pullup configuration
from platform data, which has no upstream users.
Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

mcp23xxx device have configurable 100k pullup resistors. This adds
support for enabling them using pinctrl's pinconf interface.
Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk>
Tested-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This moves the mcp23s08 driver from gpio to pinctrl. Actual
pinctrl support for configuration of the pull-up resistors
follows in its own patch.
Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: NSylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

All the drivers for the various hardware elements of the jz4740 SoC have
been modified to use the pinctrl framework for their pin configuration
needs.
As such, this platform code is now unused and can be deleted.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

We set the pin configuration for the jz4780-nand and jz4780-uart
drivers.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

We set the pin configuration for the jz4740-nand, jz4740-mmc,
jz4740-fb, jz4740-pwm and jz4740-uart drivers.

This will permit those drivers to be cleaned out of the custom GPIO code
that they currently use.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

For a description of the devicetree node, please read
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt

For a description of the gpio devicetree nodes, please read
Documentation/devicetree/bindings/gpio/ingenic,gpio.txt
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

For a description of the pinctrl devicetree node, please read
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt

For a description of the gpio devicetree nodes, please read
Documentation/devicetree/bindings/gpio/ingenic,gpio.txt
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

There is a pinctrl driver for each of the Ingenic SoCs supported by the
upstream Linux kernel. In order to switch away from the old GPIO
platform code, we now enable the pinctrl drivers by default for the
Ingenic SoCs.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Before, this NAND driver would set itself the configuration of the
chip-select pins for the various NAND banks.

Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Acked-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.

One inherent problem of this new approach is that the pinctrl framework
does not allow us to configure each pin on demand, when the various PWM
channels are requested or released. For instance, the PWM channels can
be configured from sysfs, which would require all PWM pins to be configured
properly beforehand for the PWM function, eventually causing conflicts
with other platform or board drivers.

The proper solution here would be to modify the pwm-jz4740 driver to
handle only one PWM channel, and create an instance of this driver
for each one of the 8 PWM channels. Then, it could use the pinctrl
framework to dynamically configure the PWM pin it controls.

Until this can be done, the only jz4740 board supported upstream
(Qi lb60) can configure all of its connected PWM pins in PWM function
mode, since those are not used by other drivers nor by GPIOs on the
board.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Acked-by: NThierry Reding <thierry.reding@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Acked-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This driver handles the GPIOs of all the Ingenic JZ47xx SoCs
currently supported by the upsteam Linux kernel.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This driver handles pin configuration and pin muxing for the
JZ4740 and JZ4780 SoCs from Ingenic.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This commit adds documentation for the devicetree bindings of the
gpio-ingenic driver, which handles GPIOs of the Ingenic SoCs
currently supported by the Linux kernel.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This commit adds documentation for the devicetree bindings of the
pinctrl-ingenic driver, which handles pin configuration and pin
muxing of the Ingenic SoCs currently supported by the Linux kernel.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

When pinctrl device registers, it automatically claims hogs, that is,
maps that pinctrl device serves for itself.

It is possible that in addition to SoC's pinctrl device, other pinctrl
devices get registered. E.g. some gpio expander devies are registered
as pinctrl devices. For such devices, pinctrl maps could be defined
that set up SoC's pins (e.g. interrupt pin for gpio expander). Such
a map will have target device set to gpio expander.

Here is device tree snippet that causes this scenario:

&i2c0 {
	sx1503@20 {
		compatible = "semtech,sx1503q";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_sx1503_20>;
		...
	};
};
...
&iomuxc {
	pinctrl_sx1503_20: pinctrl-sx1503-20 {
		fsl,pins = <
			VF610_PAD_PTB1__GPIO_23         0x219d
		>;
	};
};

Such a map will have target device set to gpio expander. However is not
a hog, it is a regular map that is claimed by core before gpio expander
device is probed.

Thus when looking for hogs, it is not enough to check that map's target
device is set to pinctrl device being registered. Need also check that
map's control device is also set to the same.
Signed-off-by: NNikita Yushchenko <nikita.yoush@cogentembedded.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

MX7ULP MUX mode mask and shift bit is different from VF610.
Let's make it a platform specific property for the later easy of
adding MX7ULP support.

One trick in exist code that Vybrid hardcoded the config part
as 0xffff because its mux_config register BIT[15-0] are all configs
part. But it's not true in ULP, so use mux_mask instead to address
the difference.

Cc: Stefan Agner <stefan@agner.ch>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: NFugang Duan <fugang.duan@nxp.com>
Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The design is based on the exist architecture that the core will
provide a uniformed way to decode the generic pin config into platform
config register raw data according to the imx_cfg_params_decode maps
registered by platform.

Two useful macros, IMX_CFG_PARAMS_DECODE and IMX_CFG_PARAMS_DECODE_INVERT,
are created for platform to register decode map conveniently.

In order to cope with some special case, a platform specific fixup()
function is also available to use.

Note that rather than fully utilizing the generic pinconf support
provided by pinctrl core, IMX only adopts the device tree bindings
of generic pinconf. The config used in .pin_config_get[set] are raw
register data instead of generic one which makes us align the exist
using. And that's also why we cannot set pinconf_ops.is_generic.

Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The original implemented debug message does not work for
SHARE_MUX_CONF_REG case. This patch fixes it.

Fixes: bf5a5309 ("pinctrl: imx: add VF610 support to imx pinctrl framework")
Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

If 'devm_kzalloc' fails, a NULL pointer will be dereferenced.
Return -ENOMEM instead, as done for the other memory allocation just a
few lines below.
BTW, change the 'devm_kzalloc' into a 'devm_kcalloc'.
Signed-off-by: NChristophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

mt7623 pinctrl hardware can be compatible with mt2701 driver,
so the patch lets the pinctrl on mt7623 SoC reuse the driver
and deletes those redundant ones.
Signed-off-by: NSean Wang <sean.wang@mediatek.com>
Acked-by: NJohn Crispin <john@phrozen.org>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>