1. 10 3月, 2015 1 次提交
  2. 26 1月, 2015 1 次提交
  3. 12 1月, 2015 1 次提交
    • S
      pinctrl: Add driver for Zynq · add958ce
      Soren Brinkmann 提交于
      This adds a pin-control driver for Zynq.
      
      Changes since v2:
      - driver-specific DT properties are passed to the core in two arrays,
        one for the actual DT parsing one for the debugfs representation.
        Issue a compiler warning when the number of entries is not the same
        for both arrays.
      
      Changes since v1:
       - fix EMIO_SD1_CD pin name
       - add USB to pinmux options
      
      changes since RFCv2:
       - let Zynq select PINCTRL_ZYNQ. Boot hangs when pinctrl information is
         present in DT but no driver available.
       - add #defines to get rid of magical constants
       - add commas at end of initializers
       - separate changes in mach-zynq in separate patch
       - add driver specific io-standard DT property
       - refactored pinconf set function to not require arguments for
         argument-less properties
       - squash other patches in
         - support for IO-standard property
         - support for low-power mode property
         - migration to pinconf_generic_dt_node_to_map_all()
       - use newly created infrastructure to add pass driver-specific DT
         params to pinconf-generic
      
      changes since RFC:
       - use syscon/regmap to access registers in SLCR space
       - rebase to 3.18: rename enable -> set_mux
       - add kernel-doc
       - support pinconf
         - supported attributes
           - pin-bias: pull up, tristate, disable
           - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
             argument
      Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
      Tested-by: NAndreas Färber <afaerber@suse.de>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      add958ce
  4. 11 1月, 2015 1 次提交
  5. 29 10月, 2014 1 次提交
  6. 04 9月, 2014 1 次提交
  7. 02 9月, 2014 1 次提交
  8. 29 8月, 2014 1 次提交
  9. 28 8月, 2014 1 次提交
  10. 11 7月, 2014 6 次提交
  11. 27 5月, 2014 1 次提交
  12. 23 5月, 2014 1 次提交
    • A
      pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs · 3de68d33
      Antoine Tenart 提交于
      The Marvell Berlin boards have a group based pinmuxing mechanism. This
      adds the core driver support. We actually do not need any information
      about the pins here and only have the definition of the groups.
      
      Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and
      BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set
      to mode 0:
      
      Group	Modes	Offset Base	Offset	LSB	Bit Width
      GSM12	3	sm_base		0x40	0x10	0x2
      
      Ball	Group	Mode 0		Mode 1		Mode 2
      BK4	GSM12	UART0_RX	IrDA0_RX	GPIO9
      BH6	GSM12	UART0_TX	IrDA0_TX	GPIO10
      
      So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need
      to set (sm_base + 0x40 + 0x10) &= ff3fffff.
      
      As pin control registers are part of either chip control or system
      control registers, that deal with a bunch of other functions we rely
      on a regmap instead of exclusively remapping any resources.
      Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
      Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      3de68d33
  13. 04 5月, 2014 1 次提交
  14. 23 4月, 2014 1 次提交
  15. 22 4月, 2014 1 次提交
  16. 14 4月, 2014 1 次提交
  17. 16 1月, 2014 1 次提交
  18. 13 12月, 2013 1 次提交
  19. 06 12月, 2013 2 次提交
  20. 25 11月, 2013 1 次提交
    • D
      pinctrl: pinctrl-imx: add imx25 pinctrl driver · b4a87c9b
      Denis Carikli 提交于
      This is mostly cut and paste from the imx35 pinctrl driver.
      The data was generated using sed and awk on
        arch/arm/plat-mxc/include/mach/iomux-mx25.h.
      
      Cc: Rob Herring <rob.herring@calxeda.com>
      Cc: Pawel Moll <pawel.moll@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
      Cc: devicetree@vger.kernel.org
      Cc: Shawn Guo <shawn.guo@linaro.org>
      Cc: Sascha Hauer <kernel@pengutronix.de>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: Eric Bénard <eric@eukrea.com>
      Signed-off-by: NDenis Carikli <denis@eukrea.com>
      Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      b4a87c9b
  21. 06 11月, 2013 1 次提交
  22. 29 10月, 2013 2 次提交
  23. 16 10月, 2013 1 次提交
  24. 10 10月, 2013 1 次提交
  25. 19 9月, 2013 1 次提交
    • S
      pinctrl: ADI PIN control driver for the GPIO controller on bf54x and bf60x. · e9a03add
      Sonic Zhang 提交于
      The new ADI GPIO2 controller was introduced since the BF548 and BF60x
      processors. It differs a lot from the old one on BF5xx processors. So,
      create a pinctrl driver under the pinctrl framework.
      
      - Define gpio ports and pin interrupt controllers as individual platform
        devices.
      - Register a pinctrl driver for the whole GPIO ports and pin interrupt
        devices.
      - Probe pint devices before port devices. Put device instances into
        the global gpio and pint lists.
      - Define peripheral, irq and gpio reservation bit masks for each gpio
        port as runtime resources.
      - Save and restore gpio port and pint status MMRs in syscore PM functions.
      - Create the plug-in subdrivers to hold the pinctrl soc data for bf54x
        and bf60x. Add soc data into struct adi_pinctrl. Initialize the soc data
        in pin controller probe function. Get the pin groups and functions via
        the soc data reference.
      - Call gpiochip_add_pin_range() in gpio device probe function to register
        range cross reference between gpio device and pin control device.
      - Get range by pinctrl_find_gpio_range_from_pin(), find gpio_port object
        by container_of() and find adi_pinctrl by pin control device name.
      - Handle peripheral and gpio requests in pinctrl operation functions.
      - Demux gpio IRQs via the irq_domain created by each GPIO port.
      
      v2-changes:
      - Remove unlinke() directive.
      
      v3-changes:
      - Rename struct adi_pmx to adi_pinctrl.
      - Fix the comments of struct gpio_pint.
      - Remove unused pin_base in struct gpio_port.
      - Change pint_assign into bool type.
      - Add comments about the relationship between pint device and port device
      to the driver header.
      - Use BIT macro to shift bit.
      - Remove all bitmap reservation help functions. Inline reservation functions
      into the actual code.
      - Remove gpio and offset mutual reference help functions.
      - Remove all help functions to find gpio_port and adi_pinctrl structs. Get
      range by pinctrl_find_gpio_range_from_pin(), find gpio_port object by
      container_of() and find adi_pinctrl by pin control device name.
      - Pass bool type usage variable to port_setup help function.
      - Separate long bit operations into several lines and add comments.
      - Use debugfs to output all GPIO request information.
      - Avoid to set drvdata to NULL
      - Add explanation to function adi_gpio_init_int()
      - Call gpiochip_add_pin_range() in gpio device probe function to register
      range cross reference between gpio device and pin control device.
      - Remove the reference to pin control device from the gpio_port struct.
      Remove the reference list to gpio device from the adi_pinctrl struct.
      Replace the global adi_pinctrl list with adi_gpio_port_list. Walk through
      the gpio list to do power suspend and resume operations.
      - Remove the global GPIO base from struct adi_pinctrl, define pin base in
      the platform data for each GPIO port device.
      - Initialize adi_pinctrl_setup in arch_initcall().
      - print the status of triggers, whether it is in GPIO mode, if it is
      flagged to be used as IRQ, etc in adi_pin_dbg_show().
      - Create the plug-in subdrivers to hold the pinctrl soc data for bf54x
      and bf60x. Add soc data into struct adi_pinctrl. Initialize the soc data
      in pin controller probe function. Get the pin groups and functions via
      the soc data reference.
      
      v4-changes:
      - remove useless system_state checking.
      - replace dev_err with dev_warn in both irq and gpio pin cases.
      - comment on relationship between irq type and invert operation.
      - It is not necessary to check the reservation mode of the requested
      pin in IRQ chip operation. Remove the reservation map.
      - Use existing gpio/pinctrl subsystem debugfs files. Remove pinctrl-adi2
      driver specific debugfs output.
      - Add linkport group and function information for bf60x.
      - Separate uart and ctsrts pins into 2 groups.
      - Separate APAPI and alternative ATAPI pins into 2 groups.
      Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      e9a03add
  26. 15 8月, 2013 2 次提交
  27. 25 6月, 2013 1 次提交
    • S
      pinctrl: st: Add pinctrl and pinconf support. · 701016c0
      Srinivas KANDAGATLA 提交于
      This patch add pinctrl support to ST SoCs.
      
      About hardware:
      ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
      pin configurations.
      
      Each multi-function pin is controlled, driven and routed through the PIO
      multiplexing block. Each pin supports GPIO functionality (ALT0) and
      multiple alternate functions(ALT1 - ALTx) that directly connect the pin
      to different hardware blocks. When a pin is in GPIO mode, Output Enable
      (OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO
      block. Otherwise the PIO multiplexing block configures these parameters
      and retiming the signal.
      
      About driver:
      This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
      pinconf, pinmux, gpio subsystems. All the pinctrl related config
      information can only come from device trees.
      Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com>
      Acked-by: NLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      701016c0
  28. 24 6月, 2013 2 次提交
    • J
      pinctrl-tz1090-pdc: add TZ1090 PDC pinctrl driver · b58f0273
      James Hogan 提交于
      Add a pin control driver for the TZ1090's low power pins via the
      powerdown controller SOC_GPIO_CONTROL registers.
      
      These pins have individually controlled pull-up, and group controlled
      schmitt, slew-rate, drive-strength, and power-on-start (pos).
      
      The pdc_gpio0 and pdc_gpio1 pins can also be muxed onto the
      ir_mod_stable_out and ir_mod_power_out functions respectively. If no
      function is set they remain in GPIO mode. These muxes can be overridden
      by requesting them as GPIOs.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Rob Herring <rob.herring@calxeda.com>
      Cc: Rob Landley <rob@landley.net>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: linux-doc@vger.kernel.org
      Cc: devicetree-discuss@lists.ozlabs.org
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      b58f0273
    • J
      pinctrl-tz1090: add TZ1090 pinctrl driver · d5025f9f
      James Hogan 提交于
      Add a pin control driver for the main pins on the TZ1090 SoC. This
      doesn't include the low-power pins as they're controlled separately via
      the Powerdown Controller (PDC) registers.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Rob Herring <rob.herring@calxeda.com>
      Cc: Rob Landley <rob@landley.net>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: linux-doc@vger.kernel.org
      Cc: devicetree-discuss@lists.ozlabs.org
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      d5025f9f
  29. 18 6月, 2013 1 次提交
  30. 16 6月, 2013 2 次提交