1. 06 7月, 2018 1 次提交
  2. 12 6月, 2018 1 次提交
    • L
      Revert "iommu/amd_iommu: Use CONFIG_DMA_DIRECT_OPS=y and dma_direct_{alloc,free}()" · e16c4790
      Linus Torvalds 提交于
      This reverts commit b468620f.
      
      It turns out that this broke drm on AMD platforms. Quoting Gabriel C:
       "I can confirm reverting b468620f fixes
        that issue for me.
      
        The GPU is working fine with SME enabled.
      
        Now with working GPU :) I can also confirm performance is back to
        normal without doing any other workarounds"
      
      Christan König analyzed it partially:
       "As far as I analyzed it we now get an -ENOMEM from dma_alloc_attrs()
        in drivers/gpu/drm/ttm/ttm_page_alloc_dma.c when IOMMU is enabled"
      
      and Christoph Hellwig responded:
       "I think the prime issue is that dma_direct_alloc respects the dma
        mask. Which we don't need if actually using the iommu. This would be
        mostly harmless exept for the the SEV bit high in the address that
        makes the checks fail.
      
        For now I'd say revert this commit for 4.17/4.18-rc and I'll look into
        addressing these issues properly"
      Reported-and-bisected-by: NGabriel C <nix.or.die@gmail.com>
      Acked-by: NChristoph Hellwig <hch@lst.de>
      Cc: Christian König <christian.koenig@amd.com>
      Cc: Michel Dänzer <michel.daenzer@amd.com>
      Cc: Joerg Roedel <jroedel@suse.de>
      Cc: Tom Lendacky <thomas.lendacky@amd.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: stable@kernel.org		# v4.17
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      e16c4790
  3. 06 6月, 2018 1 次提交
    • T
      irq_remapping: Use apic_ack_irq() · 8a2b7d14
      Thomas Gleixner 提交于
      To address the EBUSY fail of interrupt affinity settings in case that the
      previous setting has not been cleaned up yet, use the new apic_ack_irq()
      function instead of the special ir_ack_apic_edge() implementation which is
      merily a wrapper around ack_APIC_irq().
      
      Preparatory change for the real fix
      
      Fixes: dccfe314 ("x86/vector: Simplify vector move cleanup")
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Tested-by: NSong Liu <songliubraving@fb.com>
      Cc: Joerg Roedel <jroedel@suse.de>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Song Liu <liu.song.a23@gmail.com>
      Cc: Dmitry Safonov <0x7f454c46@gmail.com>
      Cc: stable@vger.kernel.org
      Cc: Mike Travis <mike.travis@hpe.com>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Tariq Toukan <tariqt@mellanox.com>
      Link: https://lkml.kernel.org/r/20180604162224.555716895@linutronix.de
      8a2b7d14
  4. 15 5月, 2018 2 次提交
  5. 11 5月, 2018 1 次提交
    • G
      PCI: Add "pci=noats" boot parameter · cef74409
      Gil Kupfer 提交于
      Adds a "pci=noats" boot parameter.  When supplied, all ATS related
      functions fail immediately and the IOMMU is configured to not use
      device-IOTLB.
      
      Any function that checks for ATS capabilities directly against the devices
      should also check this flag.  Currently, such functions exist only in IOMMU
      drivers, and they are covered by this patch.
      
      The motivation behind this patch is the existence of malicious devices.
      Lots of research has been done about how to use the IOMMU as protection
      from such devices.  When ATS is supported, any I/O device can access any
      physical address by faking device-IOTLB entries.  Adding the ability to
      ignore these entries lets sysadmins enhance system security.
      Signed-off-by: NGil Kupfer <gilkup@cs.technion.ac.il>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Acked-by: NJoerg Roedel <jroedel@suse.de>
      cef74409
  6. 03 5月, 2018 3 次提交
  7. 29 3月, 2018 10 次提交
  8. 20 3月, 2018 2 次提交
  9. 15 3月, 2018 2 次提交
  10. 15 2月, 2018 1 次提交
    • S
      iommu/amd: Avoid locking get_irq_table() from atomic context · df42a04b
      Scott Wood 提交于
      get_irq_table() previously acquired amd_iommu_devtable_lock which is not
      a raw lock, and thus cannot be acquired from atomic context on
      PREEMPT_RT.  Many calls to modify_irte*() come from atomic context due to
      the IRQ desc->lock, as does amd_iommu_update_ga() due to the preemption
      disabling in vcpu_load/put().
      
      The only difference between calling get_irq_table() and reading from
      irq_lookup_table[] directly, other than the lock acquisition and
      amd_iommu_rlookup_table[] check, is if the table entry is unpopulated,
      which should never happen when looking up a devid that came from an
      irq_2_irte struct, as get_irq_table() would have already been called on
      that devid during irq_remapping_alloc().
      
      The lock acquisition is not needed in these cases because entries in
      irq_lookup_table[] never change once non-NULL -- nor would the
      amd_iommu_devtable_lock usage in get_irq_table() provide meaningful
      protection if they did, since it's released before using the looked up
      table in the get_irq_table() caller.
      
      Rename the old get_irq_table() to alloc_irq_table(), and create a new
      lockless get_irq_table() to be used in non-allocating contexts that WARNs
      if it doesn't find what it's looking for.
      Signed-off-by: NScott Wood <swood@redhat.com>
      Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      df42a04b
  11. 14 2月, 2018 1 次提交
  12. 13 2月, 2018 2 次提交
  13. 12 1月, 2018 1 次提交
  14. 30 12月, 2017 1 次提交
    • T
      genirq/irqdomain: Rename early argument of irq_domain_activate_irq() · 702cb0a0
      Thomas Gleixner 提交于
      The 'early' argument of irq_domain_activate_irq() is actually used to
      denote reservation mode. To avoid confusion, rename it before abuse
      happens.
      
      No functional change.
      
      Fixes: 72491643 ("genirq/irqdomain: Update irq_domain_ops.activate() signature")
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Alexandru Chirvasitu <achirvasub@gmail.com>
      Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
      Cc: Dou Liyang <douly.fnst@cn.fujitsu.com>
      Cc: Pavel Machek <pavel@ucw.cz>
      Cc: Maciej W. Rozycki <macro@linux-mips.org>
      Cc: Mikael Pettersson <mikpelinux@gmail.com>
      Cc: Josh Poulson <jopoulso@microsoft.com>
      Cc: Mihai Costache <v-micos@microsoft.com>
      Cc: Stephen Hemminger <sthemmin@microsoft.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: linux-pci@vger.kernel.org
      Cc: Haiyang Zhang <haiyangz@microsoft.com>
      Cc: Dexuan Cui <decui@microsoft.com>
      Cc: Simon Xiao <sixiao@microsoft.com>
      Cc: Saeed Mahameed <saeedm@mellanox.com>
      Cc: Jork Loeser <Jork.Loeser@microsoft.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: devel@linuxdriverproject.org
      Cc: KY Srinivasan <kys@microsoft.com>
      Cc: Alan Cox <alan@linux.intel.com>
      Cc: Sakari Ailus <sakari.ailus@intel.com>,
      Cc: linux-media@vger.kernel.org
      702cb0a0
  15. 21 12月, 2017 2 次提交
  16. 04 11月, 2017 3 次提交
  17. 13 10月, 2017 1 次提交
  18. 12 10月, 2017 1 次提交
    • T
      iommu/iova: Make rcache flush optional on IOVA allocation failure · 538d5b33
      Tomasz Nowicki 提交于
      Since IOVA allocation failure is not unusual case we need to flush
      CPUs' rcache in hope we will succeed in next round.
      
      However, it is useful to decide whether we need rcache flush step because
      of two reasons:
      - Not scalability. On large system with ~100 CPUs iterating and flushing
        rcache for each CPU becomes serious bottleneck so we may want to defer it.
      - free_cpu_cached_iovas() does not care about max PFN we are interested in.
        Thus we may flush our rcaches and still get no new IOVA like in the
        commonly used scenario:
      
          if (dma_limit > DMA_BIT_MASK(32) && dev_is_pci(dev))
              iova = alloc_iova_fast(iovad, iova_len, DMA_BIT_MASK(32) >> shift);
      
          if (!iova)
              iova = alloc_iova_fast(iovad, iova_len, dma_limit >> shift);
      
         1. First alloc_iova_fast() call is limited to DMA_BIT_MASK(32) to get
            PCI devices a SAC address
         2. alloc_iova() fails due to full 32-bit space
         3. rcaches contain PFNs out of 32-bit space so free_cpu_cached_iovas()
            throws entries away for nothing and alloc_iova() fails again
         4. Next alloc_iova_fast() call cannot take advantage of rcache since we
            have just defeated caches. In this case we pick the slowest option
            to proceed.
      
      This patch reworks flushed_rcache local flag to be additional function
      argument instead and control rcache flush step. Also, it updates all users
      to do the flush as the last chance.
      Signed-off-by: NTomasz Nowicki <Tomasz.Nowicki@caviumnetworks.com>
      Reviewed-by: NRobin Murphy <robin.murphy@arm.com>
      Tested-by: NNate Watterson <nwatters@codeaurora.org>
      Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      538d5b33
  19. 11 10月, 2017 1 次提交
    • T
      iommu/amd: Do not disable SWIOTLB if SME is active · aba2d9a6
      Tom Lendacky 提交于
      When SME memory encryption is active it will rely on SWIOTLB to handle
      DMA for devices that cannot support the addressing requirements of
      having the encryption mask set in the physical address.  The IOMMU
      currently disables SWIOTLB if it is not running in passthrough mode.
      This is not desired as non-PCI devices attempting DMA may fail. Update
      the code to check if SME is active and not disable SWIOTLB.
      
      Fixes: 2543a786 ("iommu/amd: Allow the AMD IOMMU to work with memory encryption")
      Signed-off-by: NTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      aba2d9a6
  20. 10 10月, 2017 2 次提交
  21. 27 9月, 2017 1 次提交