- 05 5月, 2015 1 次提交
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由 Suman Anna 提交于
The L3 Error handling on OMAP5 for the most part is very similar to that of OMAP4, and had leveraged common data structures and register layout definitions so far. Upon closer inspection, there are a few minor differences causing an incorrect decoding and reporting of the master NIU upon an error: 1. The L3_TARG_STDERRLOG_MSTADDR.STDERRLOG_MSTADDR occupies 11 bits on OMAP5 as against 8 bits on OMAP4, with the master NIU connID encoded in the 6 MSBs of the STDERRLOG_MSTADDR field. 2. The CLK3 FlagMux component has 1 input source on OMAP4 and 3 input sources on OMAP5. The common DEBUGSS source is at a different input on each SoC. Fix the above issues by using a OMAP5-specific compatible property and using SoC-specific data where there are differences. Signed-off-by: NSuman Anna <s-anna@ti.com> Acked-by: NNishanth Menon <nm@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 01 4月, 2015 1 次提交
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由 Tero Kristo 提交于
This patch creates the l4_cfg and l4_wkup interconnects for OMAP5, and moves some of the generic peripherals under it. System control module support is added to the device tree also, and the existing SCM related functionality is moved under it. Signed-off-by: NTero Kristo <t-kristo@ti.com>
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- 15 3月, 2015 1 次提交
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由 Marc Zyngier 提交于
OMAP4/5 has been (ab)using the gic_arch_extn to provide wakeup from suspend, and it makes a lot of sense to convert this code to use stacked domains instead. This patch does just this, updating the DT files to actually reflect what the HW provides. BIG FAT WARNING: because the DTs were so far lying by not exposing the WUGEN HW block, kernels with this patch applied won't have any suspend-resume facility when booted with old DTs, and old kernels with updated DTs won't even boot. On a platform with this patch applied, the system looks like this: root@bacon-fat:~# cat /proc/interrupts CPU0 CPU1 16: 0 0 WUGEN 37 gp_timer 19: 233799 155916 GIC 27 arch_timer 23: 0 0 WUGEN 9 l3-dbg-irq 24: 1 0 WUGEN 10 l3-app-irq 27: 282 0 WUGEN 13 omap-dma-engine 44: 0 0 4ae10000.gpio 13 DMA 294: 0 0 WUGEN 20 gpmc 297: 506 0 WUGEN 56 48070000.i2c 298: 0 0 WUGEN 57 48072000.i2c 299: 0 0 WUGEN 61 48060000.i2c 300: 0 0 WUGEN 62 4807a000.i2c 301: 8 0 WUGEN 60 4807c000.i2c 308: 2439 0 WUGEN 74 OMAP UART2 312: 362 0 WUGEN 83 mmc2 313: 502 0 WUGEN 86 mmc0 314: 13 0 WUGEN 94 mmc1 350: 0 0 PRCM pinctrl, pinctrl 406: 35155709 0 GIC 109 ehci_hcd:usb1 407: 0 0 WUGEN 7 palmas 409: 0 0 WUGEN 119 twl6040 410: 0 0 twl6040 5 twl6040_irq_ready 411: 0 0 twl6040 0 twl6040_irq_th IPI0: 0 1 CPU wakeup interrupts IPI1: 0 0 Timer broadcast interrupts IPI2: 95334 902334 Rescheduling interrupts IPI3: 0 0 Function call interrupts IPI4: 479 648 Single function call interrupts IPI5: 0 0 CPU stop interrupts IPI6: 0 0 IRQ work interrupts IPI7: 0 0 completion interrupts Err: 0 Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088629-15377-8-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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- 07 3月, 2015 1 次提交
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由 Tero Kristo 提交于
OMAP4 has a finer counter granularity, which allows for a delay of 1000ms in the thermal zone polling intervals. OMAP5 has a different counter mechanism, which allows at maximum a 500ms timer. Adjust the cpu thermal zone polling interval accordingly. Without this patch, the polling interval information is simply ignored, and the following thermal warnings are printed during boot (assuming thermal is enabled); [ 1.545343] ti-soc-thermal 4a0021e0.bandgap: Delay 1000 ms is not supported [ 1.552691] ti-soc-thermal 4a0021e0.bandgap: Delay 1000 ms is not supported [ 1.560029] ti-soc-thermal 4a0021e0.bandgap: Delay 1000 ms is not supported Signed-off-by: NTero Kristo <t-kristo@ti.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: NEduardo Valentin <edubezval@gmail.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 25 2月, 2015 2 次提交
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由 Peter Ujfalusi 提交于
According to the Documentation/devicetree/bindings/dma/dma.txt the dma-channels and dma-requests property should not have '#'. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Roger Quadros 提交于
The sata_ref_clk is a reference clock to the SATA phy. This fixes SATA malfunction across suspend/resume or when SATA driver is used as a module. Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 11 11月, 2014 1 次提交
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由 Suman Anna 提交于
The '#mbox-cells' property is added to all the OMAP mailbox nodes. This property is mandatory with the new mailbox framework. Cc: "Benoît Cousson" <bcousson@baylibre.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Signed-off-by: NSuman Anna <s-anna@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 19 9月, 2014 2 次提交
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由 Rajendra Nayak 提交于
In order to handle errata I688, a page of sram was reserved by doing a static iotable map. Now that we use gen_pool to manage sram, we can completely remove all of these static mappings and use gen_pool_alloc() to get the one page of sram space needed to implement errata I688. omap_bus_sync will be NOP until SRAM initialization happens. Suggested-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NRajendra Nayak <rnayak@ti.com> Signed-off-by: NDave Gerlach <d-gerlach@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Rajendra Nayak 提交于
Use drivers/misc/sram.c driver to manage SRAM on all DT only OMAP platforms (am33xx, am43xx, omap4 and omap5) instead of the existing private plat-omap/sram.c Address and size related data is removed from mach-omap2/sram.c and now passed to drivers/misc/sram.c from DT. Users can hence use general purpose allocator apis instead of OMAP private ones to manage and use SRAM. Signed-off-by: NRajendra Nayak <rnayak@ti.com> Signed-off-by: NDave Gerlach <d-gerlach@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 12 9月, 2014 1 次提交
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由 Suman Anna 提交于
The sub-mailbox devices are added to the Mailbox DT nodes on OMAP2420, OMAP2430, OMAP3, AM33xx, AM43xx, OMAP4 and OMAP5 family of SoCs. This data represents the same mailboxes that used to be represented in hwmod attribute data previously. The node name is chosen based on the .name field of omap_mbox_dev_info structure used in the hwmod data. Cc: "Benoît Cousson" <bcousson@baylibre.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Signed-off-by: NSuman Anna <s-anna@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 09 9月, 2014 4 次提交
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由 Nishanth Menon 提交于
We've had deeper idle states working on omaps for few years now, but only in the legacy mode. When booted with device tree, the wake-up events did not have a chance to work until commit 3e6cee17 ("pinctrl: single: Add support for wake-up interrupts") that recently got merged. In addition to that we also needed commit 79d97015 ("of/irq: create interrupts-extended property") that's now also merged. Note that there's no longer need to specify the wake-up bit in the pinctrl settings, the request_irq on the wake-up pin takes care of that. Signed-off-by: NNishanth Menon <nm@ti.com>
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由 Nishanth Menon 提交于
Now that ti,omap5-padconf is available, switch over to that compatible property. Retain pinctrl-single for legacy support. While at it, mark pinctrl as interrupt controller so that it can be used with interrupts-extended property for wakeup events. Signed-off-by: NNishanth Menon <nm@ti.com>
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由 Nishanth Menon 提交于
Provide OMAP3, 4 and OMAP5 with interrupt number for PRM And for DRA7, provide crossbar number for prm interrupt. Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tomi Valkeinen 提交于
The RFBI node for OMAP DSS was left out when adding the rest of the DSS nodes, because it was not clear how to set up the clocks for the RFBI. However, it seems that if there is a HWMOD for a device, we also need a DT node for it. Otherwise, at boot, we get: WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2542 _init+0x464/0x4e0() omap_hwmod: dss_rfbi: doesn't have mpu register target base Now that v3.17-rc3 contains a fix 8fd46439 ("ARM: dts: omap54xx-clocks: Fix the l3 and l4 clock rates") for the L3 ICLK required by the RFBI, let's add the RFBI node to get rid of the warning. Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com> [tony@atomide.com: updated description per comments from Nishant] Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 15 7月, 2014 1 次提交
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由 Suman Anna 提交于
The number of mailbox fifos and users (IP interrupts) are added to the Mailbox DT nodes on OMAP2420, OMAP2430, OMAP3, and OMAP5 family of SoCs through the DT properties "ti,mbox-num-fifos" and "ti,mbox-num-users" properties. This data represents the same data that used to be represented in hwmod attribute data through the .num_fifos and .num_users fields previously. Signed-off-by: NSuman Anna <s-anna@ti.com> Acked-by: NPavel Machek <pavel@ucw.cz> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 08 7月, 2014 1 次提交
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由 Andrii.Tseglytskyi 提交于
Add ABB device nodes for OMAP5 family of devices. Data is based on final production OMAP543x Technical Reference Manual revision Z (April 2013). Final production Data Manual for OMAP5432 SWPS050F(APRIL 2014). [nm@ti.com: co-developer and updates to latest documentation] Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NAndrii.Tseglytskyi <andrii.tseglytskyi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 16 6月, 2014 1 次提交
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由 Nishanth Menon 提交于
As per the Final production Data Manual for OMAP5432, SWPS050F(APRIL 2014) There are only two OPPs - 1GHz and 1.5GHz. the older OPP_LOW has been completely descoped. The Nominal voltages are still correct though. However, expectation for final production configuration is operation with Adaptive Body Bias (ABB) and Adaptive Voltage Scaling Class 0 operation. There are no IDcode or version change information encoded to programmatically detect this and software is supposed to NOT use OPP_LOW(500MHz) anymore for all devices (legacy and production samples). Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 03 6月, 2014 2 次提交
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由 Jyri Sarha 提交于
Adds HDMI audio sDMA properties. Signed-off-by: NJyri Sarha <jsarha@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: NTony Lindgren <tony@atomide.com>
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由 Tomi Valkeinen 提交于
Add OMAP5 DSS nodes to omap5.dtsi. Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: NTony Lindgren <tony@atomide.com>
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- 15 5月, 2014 2 次提交
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由 Roger Quadros 提交于
The USB2 PHY driver expects named clocks for wakeup clock and reference clock. Provide this information for USB2 PHY nodes in OMAP4 and OMAP5 SoC DTS. CC: Benoît Cousson <bcousson@baylibre.com> Reviewed-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Balaji T K 提交于
Add support for sata. [Roger Q] Clean up. CC: Benoit Cousson <bcousson@baylibre.com> CC: Tony Lindgren <tony@atomide.com> Signed-off-by: NBalaji T K <balajitk@ti.com> Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 07 5月, 2014 1 次提交
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由 Nathan Lynch 提交于
Expose the PMU on OMAP5. Tested with perf on OMAP5 uEVM. Signed-off-by: NNathan Lynch <nathan_lynch@mentor.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 26 4月, 2014 1 次提交
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由 Suman Anna 提交于
Add the mailbox device DT node for OMAP5 SoC. The OMAP5 mailbox IP is identical to that used in OMAP4. The OMAP5 hwmod data no longer publishes the module address space, so this patch fixes the WARN_ON backtrace associated with the following trace during the kernel boot: "omap_hwmod: mailbox: doesn't have mpu register target base". Otherwise we get a warning like this: WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2538 _init+0x1c0/0x3dc() omap_hwmod: mailbox: doesn't have mpu register target base Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.15.0-rc2-00001-gb5e85a0 #45 [<c0015724>] (unwind_backtrace) from [<c00120f4>] (show_stack+0x10/0x14) [<c00120f4>] (show_stack) from [<c05a1ccc>] (dump_stack+0x78/0x94) [<c05a1ccc>] (dump_stack) from [<c0042a74>] (warn_slowpath_common+0x6c/0x8c) [<c0042a74>] (warn_slowpath_common) from [<c0042b28>] (warn_slowpath_fmt+0x30/0x40) [<c0042b28>] (warn_slowpath_fmt) from [<c0803b40>] (_init+0x1c0/0x3dc) [<c0803b40>] (_init) from [<c0029c8c>] (omap_hwmod_for_each+0x34/0x5c) [<c0029c8c>] (omap_hwmod_for_each) from [<c08042b0>] (__omap_hwmod_setup_all+0x24/0x40) [<c08042b0>] (__omap_hwmod_setup_all) from [<c00088b8>] (do_one_initcall+0x34/0x160) [<c00088b8>] (do_one_initcall) from [<c07f7bf4>] (kernel_init_freeable+0xfc/0x1c8) [<c07f7bf4>] (kernel_init_freeable) from [<c059c4f4>] (kernel_init+0x8/0xe4) [<c059c4f4>] (kernel_init) from [<c000eaa8>] (ret_from_fork+0x14/0x2c) Signed-off-by: NSuman Anna <s-anna@ti.com> [tony@atomide.com: updated description to for the warning] Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 19 4月, 2014 3 次提交
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由 Geert Uytterhoeven 提交于
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Cc: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Geert Uytterhoeven 提交于
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Cc: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Roger Quadros 提交于
The USB3 PHY driver (ti-pipe3) was updated so that the relevant clock phandles are expected in the DT node. Provide the necessary clocks. Reported-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NRoger Quadros <rogerq@ti.com> Acked-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 14 3月, 2014 2 次提交
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由 Roger Quadros 提交于
Use a meaningful name for the reference clocks so that it indicates the function. Update the OMAP4+ USB Host node as well to be in sync with the changes. Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Florian Vaussard 提交于
The GPMC clock is derived from l3_ick. The simplest solution is to reference directly l3_ick to provide the GPMC fck in order to get correct timings. The real management of the clock is left to hwmod. Cc: stable@vger.kernel.org # v3.14+ Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 13 3月, 2014 1 次提交
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由 Suman Anna 提交于
The IOMMU DT nodes have been added for the DSP and IPU subsystems. The MMUs in OMAP5 are identical to those in OMAP4, including the bus error back capability on IPU. Signed-off-by: NSuman Anna <s-anna@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 06 3月, 2014 1 次提交
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由 Kishon Vijay Abraham I 提交于
Added device tree bindings for dwc3, usb2 and usb3 PHYs. The documentation of these can be found at Documentation/devicetree/bindings/phy/phy-bindings.txt and Documentation/devicetree/bindings/phy/ti-phy.txt. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 05 3月, 2014 2 次提交
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由 Roger Quadros 提交于
The OMAP EHCI and OHCI controllers are not compatible with drivers other than "ti,ehci-omap" and "ti,ohci-omap3" respectively, so get rid of the incompatible ids. CC: Alan Stern <stern@rowland.harvard.edu> CC: Nishant Menon <nm@ti.com> CC: Kevin Hilman <khilman@linaro.org> Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Balaji T K 提交于
Add pbias regulator node as a child of system control module - syscon. Signed-off-by: NBalaji T K <balajitk@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Tested-by: NFlorian Vaussard <florian.vaussard@epfl.ch> Tested-by: NStefan Roese <sr@denx.de> Signed-off-by: NChris Ball <chris@printf.net>
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- 03 3月, 2014 1 次提交
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由 Archit Taneja 提交于
Add Dynamic Memory Manager (DMM) bindings for OMAP4 and OMAP5 and DRA7x devices. DMM only requires address and irq information. Add documentation for the DMM bindings. Originally worked on by Andy Gross <andygro@gmail.com> Cc: Andy Gross <andygro@gmail.com> Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>
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- 01 3月, 2014 3 次提交
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由 Nishanth Menon 提交于
OMAP34xx, AM3517 and OMAP36xx platforms use dpll1 clock. OMAP443x, OMAP446x, OMAP447x, OMAP5, DRA7, AM43xx platforms use dpll_mpu clock. Latency used is the generic latency defined in omap-cpufreq driver. Signed-off-by: NNishanth Menon <nm@ti.com> Acked-by: NAcked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Peter Ujfalusi 提交于
Board dts files will need to enable the IP nodes which they are using and does not have to care about the not used ones (to disable them). Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Suman Anna 提交于
Add a new generic property "#hwlock-cells" to the hwspinlock DT nodes on OMAP4, OMAP5 and AM33xx. This common property allows different platform implementations to define the args specifier length. OMAP implementations will always use a value of 1. Signed-off-by: NSuman Anna <s-anna@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 18 1月, 2014 1 次提交
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由 Tero Kristo 提交于
This patch creates a unique node for each clock in the OMAP5 power, reset and clock manager (PRCM). Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 04 12月, 2013 2 次提交
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由 Eduardo Valentin 提交于
OMAP5 devices can reach high temperatures and thus needs to have cpufreq-cooling on systems running on it. This patch adds the required cooling device properties so that cpufreq-cpu0 driver loads the cooling device. Cc: "Benoît Cousson" <bcousson@baylibre.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Ian Campbell <ian.campbell@citrix.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: linux-omap@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: NEduardo Valentin <eduardo.valentin@ti.com>
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由 Eduardo Valentin 提交于
This patch changes the dtsi entry on omap5 to contain the thermal data. This data will enable the passive cooling with CPUfreq cooling device at 100C. The system will do a thermal shutdown at 125C whenever any of its sensors sees this level. Cc: "Benoît Cousson" <bcousson@baylibre.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Ian Campbell <ian.campbell@citrix.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: linux-omap@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: NEduardo Valentin <eduardo.valentin@ti.com>
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- 30 10月, 2013 1 次提交
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由 Suman Anna 提交于
Add the hwspinlock device tree node for OMAP5 SoCs. Signed-off-by: NSuman Anna <s-anna@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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