- 05 5月, 2015 10 次提交
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由 Suman Anna 提交于
The L3 Error handling on OMAP5 for the most part is very similar to that of OMAP4, and had leveraged common data structures and register layout definitions so far. Upon closer inspection, there are a few minor differences causing an incorrect decoding and reporting of the master NIU upon an error: 1. The L3_TARG_STDERRLOG_MSTADDR.STDERRLOG_MSTADDR occupies 11 bits on OMAP5 as against 8 bits on OMAP4, with the master NIU connID encoded in the 6 MSBs of the STDERRLOG_MSTADDR field. 2. The CLK3 FlagMux component has 1 input source on OMAP4 and 3 input sources on OMAP5. The common DEBUGSS source is at a different input on each SoC. Fix the above issues by using a OMAP5-specific compatible property and using SoC-specific data where there are differences. Signed-off-by: NSuman Anna <s-anna@ti.com> Acked-by: NNishanth Menon <nm@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Nishanth Menon 提交于
Fix a typo in DRA7 dtsi where 12 bytes are needed for register description of ABB efuse registers, however only 8 bytes are provided to map. For some weird reason, this does not generate abort at offset 0x8, probably due to default maps already provided in io.c for the bus register ranges. Reported-by: NMatt Gessner <Matt.Gessner@windriver.com> Reported-by: NSuman Anna <s-anna@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Nishanth Menon 提交于
BeagleBoard-X15 pre-production change includes switching the GPIO fan gpio over from 1 to 2 to allow for a potential fix at a later point in time for USB client VBUS detection using PMIC VBUS detect capability. Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Nishanth Menon 提交于
BeagleBoard-X15 pre-production change includes switching over to UART pins that now allow for UART download capability. All original boards should either have been returned for modifications or already modified for the required change and maintaining compatibility for older boards are no longer needed. Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Felipe Balbi 提交于
The new AM437x SK Beta boards have removed the large capacitors on the gpio-matrix column lines which means we can reduce col-scan-delay-us to 5us without loosing functionality. Signed-off-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Felipe Balbi 提交于
AM437x Starter Kit uses a NewHaven Display module with a 4.3" display and EDT FT5306 touchscreen On that module's new revision, NewHave decided to change the pinout on the 6 pin flat-pcb touchscreen connector so that instead of having WAKE pin, we now have RESETn. The new display module is available on AM437x SK Beta and all new revisions while the older revision is only available on AM437x SK Alpha which, unfortunately, can't be supported anymore in mainline without a revert of this patch. Signed-off-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Nishanth Menon 提交于
With commit bc078316 ("ARM: dts: DRA7: Add node for RTC"), we now have AM57xx RTC register itself as alias 0 even before DS1307 or TPS rtc drivers are loaded up. However, since neither TPS, nor AM57xx RTC are capable of being backedup by battery, we would like to maintain the "primary" rtc as mcp79410 rtc device. This also generates the following warnings in the bootlog highlighting the issue: [ 5.895445] rtc-ds1307 2-006f: /aliases ID 0 not available ... [ 6.476285] palmas-rtc 48070000.i2c:tps659038@58:tps659038_rtc: /aliases ID 1 not available So, add proper aliases to ensure that RTC order is always consistent to userspace immaterial of probe order. Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Grygorii Strashko 提交于
The interrupt polarity provided in devicetree is used to configure the interrupt controller(ARM GIC), however, it seems that we have an inverter at the GIC boundary inside AM57xx which inverts the signal input from sys_irq external interrupt source. Further, as per GIC distributor TRM, http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438d/BGBHIACJ.html#BABJFCFB ARM GIC distributor does not support IRQ trigger type IRQ_TYPE_LEVEL_LOW, and only rising or level high signals. However, for some reason, the current configuration(which gets ignored by GIC driver) functions on some platforms, however, on few platforms results in infinite interrupts hogging the system down. Switch over to rising edge for GIC configuration which is also aligned with trigger point from the RTC chip and the internal inversion. Fixes: 5a0f93c6 ("ARM: dts: Add am57xx-beagle-x15") Signed-off-by: NGrygorii Strashko <Grygorii.Strashko@linaro.org> Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Sebastian Reichel 提交于
Add missing #iommu-cells property to the isp and iva iommu nodes. This fixes the binding (property is required according to the generic iommu binding) and removes the following kernel warning triggered once the iommu nodes are referenced: [ 0.647521] /ocp/isp@480bc000: could not get #iommu-cells for /ocp/mmu@480bd400 Signed-off-by: NSebastian Reichel <sre@kernel.org> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: NSakari Ailus <sakari.ailus@iki.fi> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Pavel Machek 提交于
N900 audio recording needs that codec provides bias voltage for integrated digital microphone and headset microphone depending which one is used. Digital microphone uses 2 V bias and it comes from the codec A part. Codec B part drives the headset microphone bias and that is set to 2.5 V. Cc: stable@vger.kernel.org # v3.16+ Signed-off-by: NPavel Machek <pavel@ucw.cz> [Jarkko: Headset mic bias changed to 2 (2.5 V) as it was before commit e2e8bfdf ("ASoC: tlv320aic3x: Convert mic bias to a supply widget")] Signed-off-by: NJarkko Nikula <jarkko.nikula@bitmer.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 28 4月, 2015 1 次提交
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由 Shawn Guo 提交于
The pinctrl-assert-gpios is an invalid pinctrl property. It was probably sneaked from vendor tree. Remove it. Fixes: 4e18a224 ("ARM: imx6qdl-sabreauto.dtsi: add max7310 support") Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 27 4月, 2015 6 次提交
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由 Marek Vasut 提交于
Fix a typo in the TX DMA interrupt name for AUART4. This patch makes AUART4 operational again. Signed-off-by: NMarek Vasut <marex@denx.de> Fixes: f30fb03d ("ARM: dts: add generic DMA device tree binding for mxs-dma") Cc: stable@vger.kernel.org Acked-by: NStefan Wahren <stefan.wahren@i2se.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Markus Pargmann 提交于
The property '#pwm-cells' is currently missing. It is not possible to use pwm4 without this property. Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de> Fixes: 5658a68f ("ARM i.MX25: Add devicetree") Cc: <stable@vger.kernel.org> Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Philipp Zabel 提交于
The fixed-regulator bindings require a separate property enable-active-high, the standard gpio phandle property polarity setting is ignored. Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Fixes: 4fe69a93 ("ARM: dts: Add Phytec pfla02 with i.MX6 DualLite/Solo") Cc: stable@vger.kernel.org Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Stefan Wahren 提交于
The dr_mode of usb0 on imx233-olinuxino is left to default "otg". Since the green LED (GPIO2_1) on imx233-olinuxino is connected to the same pin as USB_OTG_ID it's possible to disable USB host by LED toggling: echo 0 > /sys/class/leds/green/brightness [ 1068.890000] ci_hdrc ci_hdrc.0: remove, state 1 [ 1068.890000] usb usb1: USB disconnect, device number 1 [ 1068.920000] usb 1-1: USB disconnect, device number 2 [ 1068.920000] usb 1-1.1: USB disconnect, device number 3 [ 1069.070000] usb 1-1.2: USB disconnect, device number 4 [ 1069.450000] ci_hdrc ci_hdrc.0: USB bus 1 deregistered [ 1074.460000] ci_hdrc ci_hdrc.0: timeout waiting for 00000800 in 11 This patch fixes the issue by setting dr_mode to "host" in the dts file. Reported-by: NHarald Geyer <harald@ccbib.org> Signed-off-by: NStefan Wahren <stefan.wahren@i2se.com> Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com> Reviewed-by: NMarek Vasut <marex@denx.de> Acked-by: NPeter Chen <peter.chen@freescale.com> Fixes: b4931294 ("ARM: dts: imx23-olinuxino: Add USB host support") Cc: stable@vger.kernel.org Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Fabio Estevam 提交于
On imx23-olinuxino the LED turns on when level logic high is aplied to GPIO2_1. Fix the gpios property accordingly. Fixes: b34aa185 ("ARM: dts: imx23-olinuxino: Remove unneeded "default-on"") Reported-by: NStefan Wahren <stefan.wahren@i2se.com> Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Tested-by: NStefan Wahren <stefan.wahren@i2se.com> Cc: stable@vger.kernel.org Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Gregory CLEMENT 提交于
There is no crystal connected to the internal RTC on the Open Block AX3. So let's disable it in order to prevent the kernel probing the driver uselessly. Eventually this patches removes the following warning message from the boot log: "rtc-mv d0010300.rtc: internal RTC not ticking" Acked-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.8 +
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- 22 4月, 2015 1 次提交
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由 Mathieu Olivari 提交于
Add the watchdog related entries to the Krait Processor Sub-system (KPSS) timer IPQ8064 devicetree section. Also, add a fixed-clock description of SLEEP_CLK, which will do for now. Signed-off-by: NJosh Cartwright <joshc@codeaurora.org> Signed-off-by: NMathieu Olivari <mathieu@codeaurora.org> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Acked-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
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- 14 4月, 2015 2 次提交
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由 Tsahee Zidenberg 提交于
This patch adds device-tree entry for the internal pci bus on Alpine. Alpine's on-chip devices appear as pci devices on this bus. Signed-off-by: NTsahee Zidenberg <tsahee@annapurnalabs.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Arnd Bergmann 提交于
This reverts commit e6f219b8. to fix a build error: arch/arm/boot/dts/mt8135-pinfunc.h:18:40: fatal error: dt-bindings/pinctrl/mt65xx.h: No such file or directory Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 08 4月, 2015 1 次提交
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由 Thomas Petazzoni 提交于
All Marvell EBU SoCs (Kirkwood, Dove, Orion, Armada) have the capability of changing the location of their internal registers (i.e the registers for most hardware blocks inside the SoC). When coming out of reset, the internal registers are mapped at 0xd0000000, but since years and years, the tradition has been to have the internal registers remapped at 0xf1000000 by the bootloader, and Linux has since then assumed that the internal registers for the SoC were located at 0xf1000000 on Kirkwood, Dove, Orion, etc. Linux has never been aware that those registers are remappable (and there is no way to know where they are mapped at runtime, since the register to configure the address of the registers is itself within the internal registers). Then came the Armada 370 and Armada XP, in which some of the very early silicon steppings had an issue, which forced to use 0xd0000000: the SoC was no longer working properly when the internal registers were remapped at 0xf1000000. This issue is only affecting very early silicon steppings and production steppings are not affected: the issue has been fixed in between. Since what we (Free Electrons) used to do the initial submission of the Armada 370 and Armada XP platforms was evaluation boards with those very early steppings, we submitted Device Tree that assumed the internal registers were mapped at 0xd0000000. This is the case for Armada 370 DB, Armada XP DB and Armada XP GP. However, in practice, since Marvell has been shipping the evaluation boards with production steppings of the SoC, they are shipping those boards with bootloaders that remap the registers to 0xf1000000. We have already changed this internal register address to 0xf1000000 for the Armada XP DB in commit 82066bdb and for the Armada XP GP in commit 91ed3220 (both merged in v3.15). We only recently got our hand on an Armada 370 DB with a production stepping of the SoC, which uses a bootloader that remaps internal registers at 0xf1000000. Therefore, this commit aligns the Armada 370 DB to be like the Armada XP DB and Armada XP GP: assume that the internal registers are mapped at 0xf1000000. We would like to stress out the fact that the usage of 0xd0000000 as the internal register base address was a temporary workaround for early steppings deficiencies, and that the real long-term solution is the usage of 0xf1000000. Having 0xd0000000 is an *accident* in the life of the Marvell platform support in the kernel, as is confirmed by the usage of 0xf1000000 in all previous Marvell platforms (Dove, Kirkwood, Orion). There are unfortunately a number of commercial devices that continue to use 0xd0000000 even though they use production steppings of the SoC, simply because the vendors of such devices have never bothered using a more recent bootloader version from Marvell. There is not much we can do about it, and we plan on keeping 0xd0000000 in the Device Tree of such devices. The main reason for remapping the internal registers at 0xf1000000 instead of 0xd0000000 is that it leaves more space in the 0 -> 4 GB part of the physical address space for RAM. With registers at 0xd0000000, all RAM between 0xd0000000 to 0xffffffff is lost because it's covered by the I/O registers. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NAndrew Lunn <andrew@lunn.ch> Acked-by: NJason Cooper <jason@lakedameon.net> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
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- 04 4月, 2015 17 次提交
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由 Nicolas Ferre 提交于
After 57a38eff (net: phy: micrel: disable broadcast for KSZ8081/KSZ8091) the macb1 interface refuses to work properly because it tries to cling to address 0 which isn't able to communicate in broadcast with the mac anymore. The micrel phy on the board is actually configured to show up at address 1. Adding the phy node and its real address fixes the issue. Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Cc: Johan Hovold <johan@kernel.org> Cc: <stable@vger.kernel.org> #3.19 Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Lina Iyer 提交于
Add ARM common idle state device bindings for cpuidle support for APQ 8064. Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu. Signed-off-by: NLina Iyer <lina.iyer@linaro.org> Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Lina Iyer 提交于
Add ARM common idle states device bindings for cpuidle support for APQ 8084. Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu. Signed-off-by: NLina Iyer <lina.iyer@linaro.org> Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Lina Iyer 提交于
Add ARM common idle states device bindings for cpuidle support for APQ 8974/8074. Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu. Signed-off-by: NLina Iyer <lina.iyer@linaro.org> Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Lina Iyer 提交于
Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible binding string to configure SPM registers and allow the SPM to put the core in deeper idle states when the core is idle. Signed-off-by: NLina Iyer <lina.iyer@linaro.org> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Lina Iyer 提交于
Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to regulate the power to the cpu and aide the core in entering idle states. Reference the SAW instance and associate the instance with the CPU core. Signed-off-by: NLina Iyer <lina.iyer@linaro.org> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Lina Iyer 提交于
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to regulate the power to the cpu and aide the core in entering idle states. Reference the SAW instance and associate the instance with the CPU core. Signed-off-by: NLina Iyer <lina.iyer@linaro.org> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Kenneth Westfield 提交于
Model the Qualcomm Technologies LPASS hardware for the ipq806x SOC. Signed-off-by: NKenneth Westfield <kwestfie@codeaurora.org> Acked-by: NBanajit Goswami <bgoswami@codeaurora.org> Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Ivan T. Ivanov 提交于
PMA8084 have 2 SPMI devices per physical package. Add their configuration nodes and include them in boards which are using AQP8084 based chipset. Signed-off-by: NIvan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Ivan T. Ivanov 提交于
PM8841 and PM8941 have 2 SPMI devices per physical package. Add their configuration nodes and include them in boards which are using 8x74 based chipset. Signed-off-by: NIvan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Ivan T. Ivanov 提交于
Add SPMI PMIC Arbiter configuration nodes for APQ8084 and MSM8974. Signed-off-by: NIvan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Kumar Gala 提交于
Add the node for the LPASS clock controller found on a few qcom SoCs so that the clock driver can probe. Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> Signed-off-by: NKumar Gala <galak@codeaurora.org> [sboyd@codeaurora.org: Added apq8064 and msm8960 nodes] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Andy Gross 提交于
This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by: NAndy Gross <agross@codeaurora.org> Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Andy Gross 提交于
This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by: NAndy Gross <agross@codeaurora.org> Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Andy Gross 提交于
This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by: NAndy Gross <agross@codeaurora.org> Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Andy Gross 提交于
This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by: NAndy Gross <agross@codeaurora.org> Signed-off-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Olof Johansson 提交于
Reported-by: NBrian Norris <computersforpeace@gmail.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 03 4月, 2015 2 次提交
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由 Sebastian Reichel 提交于
This adds support for the N900's accelerometer to the Nokia N900 DTS file. Signed-off-by: NSebastian Reichel <sre@kernel.org> Acked-by: NTony Lindgren <tony@atomide.com> Reviewed-by: NÉric Piel <eric.piel@tremplin-utc.net> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Kaixu Xia 提交于
The coresight-default-sink configuration option has been removed from the framework. As such remove it from DT and bindings. Signed-off-by: NKaixu Xia <xiakaixu@huawei.com> Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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