1. 22 8月, 2009 2 次提交
    • L
      x86: don't call '->send_IPI_mask()' with an empty mask · b04e6373
      Linus Torvalds 提交于
      As noted in 83d349f3 ("x86: don't send
      an IPI to the empty set of CPU's"), some APIC's will be very unhappy
      with an empty destination mask.  That commit added a WARN_ON() for that
      case, and avoided the resulting problem, but didn't fix the underlying
      reason for why those empty mask cases happened.
      
      This fixes that, by checking the result of 'cpumask_andnot()' of the
      current CPU actually has any other CPU's left in the set of CPU's to be
      sent a TLB flush, and not calling down to the IPI code if the mask is
      empty.
      
      The reason this started happening at all is that we started passing just
      the CPU mask pointers around in commit 4595f962 ("x86: change
      flush_tlb_others to take a const struct cpumask"), and when we did that,
      the cpumask was no longer thread-local.
      
      Before that commit, flush_tlb_mm() used to create it's own copy of
      'mm->cpu_vm_mask' and pass that copy down to the low-level flush
      routines after having tested that it was not empty.  But after changing
      it to just pass down the CPU mask pointer, the lower level TLB flush
      routines would now get a pointer to that 'mm->cpu_vm_mask', and that
      could still change - and become empty - after the test due to other
      CPU's having flushed their own TLB's.
      
      See
      
      	http://bugzilla.kernel.org/show_bug.cgi?id=13933
      
      for details.
      Tested-by: NThomas Björnell <thomas.bjornell@gmail.com>
      Cc: stable@kernel.org
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      b04e6373
    • L
      x86: don't send an IPI to the empty set of CPU's · 83d349f3
      Linus Torvalds 提交于
      The default_send_IPI_mask_logical() function uses the "flat" APIC mode
      to send an IPI to a set of CPU's at once, but if that set happens to be
      empty, some older local APIC's will apparently be rather unhappy.  So
      just warn if a caller gives us an empty mask, and ignore it.
      
      This fixes a regression in 2.6.30.x, due to commit 4595f962 ("x86:
      change flush_tlb_others to take a const struct cpumask"), documented
      here:
      
      	http://bugzilla.kernel.org/show_bug.cgi?id=13933
      
      which causes a silent lock-up.  It only seems to happen on PPro, P2, P3
      and Athlon XP cores.  Most developers sadly (or not so sadly, if you're
      a developer..) have more modern CPU's.  Also, on x86-64 we don't use the
      flat APIC mode, so it would never trigger there even if the APIC didn't
      like sending an empty IPI mask.
      Reported-by: NPavel Vilim <wylda@volny.cz>
      Reported-and-tested-by: NThomas Björnell <thomas.bjornell@gmail.com>
      Reported-and-tested-by: NMartin Rogge <marogge@onlinehome.de>
      Cc: Mike Travis <travis@sgi.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: stable@kernel.org
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      83d349f3
  2. 18 8月, 2009 6 次提交
  3. 17 8月, 2009 3 次提交
    • I
      x86, mce: Don't initialize MCEs on unknown CPUs · e412cd25
      Ingo Molnar 提交于
      An older test-box started hanging at the following point during
      bootup:
      
       [    0.022996] Mount-cache hash table entries: 512
       [    0.024996] Initializing cgroup subsys debug
       [    0.025996] Initializing cgroup subsys cpuacct
       [    0.026995] Initializing cgroup subsys devices
       [    0.027995] Initializing cgroup subsys freezer
       [    0.028995] mce: CPU supports 5 MCE banks
      
      I've bisected it down to commit 4efc0670 ("x86, mce: use 64bit
      machine check code on 32bit"), which utilizes the MCE code on
      32-bit systems too.
      
      The problem is caused by this detail in my config:
      
        # CONFIG_CPU_SUP_INTEL is not set
      
      This disables the quirks in mce_cpu_quirks() but still enables
      MCE support - which then hangs due to the missing quirk
      workaround needed on this CPU:
      
      	if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
      		mce_banks[0].init = 0;
      
      The safe solution is to not initialize MCEs if we dont know on
      what CPU we are running (or if that CPU's support code got
      disabled in the config).
      
      Also be a bit more defensive on 32-bit systems: dont do a
      boot-time dump of pending MCEs not just on the specific system
      that we found a problem with (Pentium-M), but earlier ones as
      well.
      
      Now this problem is probably not common and disabling CPU
      support is rare - but still being more defensive in something
      we turned on for a wide range of CPUs is prudent.
      
      Cc: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      LKML-Reference: Message-ID: <4A88E3E4.40506@jp.fujitsu.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      e412cd25
    • B
      x86, mce: don't log boot MCEs on Pentium M (model == 13) CPUs · c7f6fa44
      Bartlomiej Zolnierkiewicz 提交于
      On my legacy Pentium M laptop (Acer Extensa 2900) I get bogus MCE on a cold
      boot with CONFIG_X86_NEW_MCE enabled, i.e. (after decoding it with mcelog):
      
      MCE 0
      HARDWARE ERROR. This is *NOT* a software problem!
      Please contact your hardware vendor
      CPU 0 BANK 1 MCG status:
      MCi status:
      Error overflow
      Uncorrected error
      Error enabled
      Processor context corrupt
      MCA: Data CACHE Level-1 UNKNOWN Error
      STATUS f200000000000195 MCGSTATUS 0
      
      [ The other STATUS values observed: f2000000000001b5 (... UNKNOWN error)
        and f200000000000115 (... READ Error).
      
        To verify that this is not a CONFIG_X86_NEW_MCE bug I also modified
        the CONFIG_X86_OLD_MCE code (which doesn't log any MCEs) to dump
        content of STATUS MSR before it is cleared during initialization. ]
      
      Since the bogus MCE results in a kernel taint (which in turn disables
      lockdep support) don't log boot MCEs on Pentium M (model == 13) CPUs
      by default ("mce=bootlog" boot parameter can be be used to get the old
      behavior).
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      Reviewed-by: NAndi Kleen <andi@firstfloor.org>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      c7f6fa44
    • L
      x86: Annotate section mismatch warnings in kernel/apic/x2apic_uv_x.c · 52459ab9
      Leonardo Potenza 提交于
      The function uv_acpi_madt_oem_check() has been marked __init,
      the struct apic_x2apic_uv_x has been marked __refdata.
      
      The aim is to address the following section mismatch messages:
      
      WARNING: arch/x86/kernel/apic/built-in.o(.data+0x1368): Section mismatch in reference from the variable apic_x2apic_uv_x to the function .cpuinit.text:uv_wakeup_secondary()
      The variable apic_x2apic_uv_x references
      the function __cpuinit uv_wakeup_secondary()
      If the reference is valid then annotate the
      variable with __init* or __refdata (see linux/init.h) or name the variable:
      *driver, *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
      
      WARNING: arch/x86/kernel/built-in.o(.data+0x68e8): Section mismatch in reference from the variable apic_x2apic_uv_x to the function .cpuinit.text:uv_wakeup_secondary()
      The variable apic_x2apic_uv_x references
      the function __cpuinit uv_wakeup_secondary()
      If the reference is valid then annotate the
      variable with __init* or __refdata (see linux/init.h) or name the variable:
      *driver, *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
      
      WARNING: arch/x86/built-in.o(.text+0x7b36f): Section mismatch in reference from the function uv_acpi_madt_oem_check() to the function .init.text:early_ioremap()
      The function uv_acpi_madt_oem_check() references
      the function __init early_ioremap().
      This is often because uv_acpi_madt_oem_check lacks a __init
      annotation or the annotation of early_ioremap is wrong.
      
      WARNING: arch/x86/built-in.o(.text+0x7b38d): Section mismatch in reference from the function uv_acpi_madt_oem_check() to the function .init.text:early_iounmap()
      The function uv_acpi_madt_oem_check() references
      the function __init early_iounmap().
      This is often because uv_acpi_madt_oem_check lacks a __init
      annotation or the annotation of early_iounmap is wrong.
      
      WARNING: arch/x86/built-in.o(.data+0x8668): Section mismatch in reference from the variable apic_x2apic_uv_x to the function .cpuinit.text:uv_wakeup_secondary()
      The variable apic_x2apic_uv_x references
      the function __cpuinit uv_wakeup_secondary()
      If the reference is valid then annotate the
      variable with __init* or __refdata (see linux/init.h) or name the variable:
      *driver, *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
      Signed-off-by: NLeonardo Potenza <lpotenza@inwind.it>
      LKML-Reference: <200908161855.48302.lpotenza@inwind.it>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      52459ab9
  4. 16 8月, 2009 1 次提交
  5. 15 8月, 2009 5 次提交
    • L
      ARM: 5673/1: U300 fix initsection compile warning · a2bb9f4d
      Linus Walleij 提交于
      The u300_init_check_chip() function was not properly tagged with
      the __init macro and provided a initsection mismatch on
      compilation.
      Signed-off-by: NLinus Walleij <linus.walleij@stericsson.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      a2bb9f4d
    • R
      ARM: Fix broken highmem support · dde5828f
      Russell King 提交于
      Currently, highmem is selectable, and you can request an increased
      vmalloc area.  However, none of this has any effect on the memory
      layout since a patch in the highmem series was accidentally dropped.
      Moreover, even if you did want highmem, all memory would still be
      registered as lowmem, possibly resulting in overflow of the available
      virtual mapping space.
      
      The highmem boundary is determined by the highest allowed beginning
      of the vmalloc area, which depends on its configurable minimum size
      (see commit 60296c71 for details on
      this).
      
      We should create mappings and initialize bootmem only for low memory,
      while the zone allocator must still be told about highmem.
      
      Currently, memory nodes which are completely located in high memory
      are not supported.  This is not a huge limitation since systems
      relying on highmem support are unlikely to have discontiguous memory
      with large holes.
      
      [ A similar patch was meant to be merged before commit 5f0fbf9e
        and be available  in Linux v2.6.30, however some git rebase screw-up
        of mine dropped the first commit of the series, and that goofage
        escaped testing somehow as well. -- Nico ]
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      Reviewed-by: NNicolas Pitre <nico@marvell.com>
      dde5828f
    • C
      x86: Fix UV BAU destination subnode id · 3ef12c3c
      Cliff Wickman 提交于
      The SGI UV Broadcast Assist Unit is used to send TLB shootdown
      messages to remote nodes of the system.  The header of the
      message must contain the subnode id of the block in the
      receiving hub that handles such messages.  It should always be
      0x10, the id of the "LB" block.
      
      It had previously been documented as a "must be zero" field.
      Signed-off-by: NCliff Wickman <cpw@sgi.com>
      Acked-by: NJack Steiner <steiner@sgi.com>
      LKML-Reference: <E1Mc1x7-0005Ce-6t@eag09.americas.sgi.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      3ef12c3c
    • M
      sh: sh7724 ddr self-refresh changes · 237674e0
      Magnus Damm 提交于
      This patch updates the SuperH Mobile sleep assembly code with
      support for DBSC memory controller found in the sh7724 processor.
      
      Without this fix the memory hooked up to the sh7724 processor
      will never enter self-refresh mode before suspending to ram. The
      effect of this is that the memory contents most likeley will be
      lost upon resume which may or may not be what you want.
      Signed-off-by: NMagnus Damm <damm@igel.co.jp>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      237674e0
    • M
      sh: use in-soc KEYSC on se7724 · 9747e78b
      Magnus Damm 提交于
      This patch updates the Solution Engine 7724 board code to use
      in-SoC KEYSC resources for the keyboard platform device. Using
      the in-SoC key scan controller fixes a crash-during-resume issue.
      
      Without this patch the KEYSC hardware block located in the board
      specific FPGA is used together with an external IRQ which is
      routed through the FPGA and handled by some board specific demux
      code. This board specific FPGA interrupt code does not implement
      desc->set_wake() so the enable_irq_wake() call in the sh_keysc
      driver will fail at suspend-to-ram time and the disable_irq_wake()
      will bomb out when resuming.
      
      Changing the platform data to use the in-SoC KEYSC hardware makes
      the se7724 board support code less special which is a good thing.
      Also, the board specific KEYSC pin setup code selects in-SoC pin
      functions already which makes the current FPGA platform device data
      look like a typo.
      Signed-off-by: NMagnus Damm <damm@igel.co.jp>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      9747e78b
  6. 14 8月, 2009 3 次提交
    • V
      mx31moboard: invert sdhc ro signal sense · 563abb4b
      Valentin Longchamp 提交于
      Small confusion with our hardware engineer, the WP signal (RO) is
      active low on our boards, the signal has to inverted.
      
      This is a pretty straightforward patch, it could even go to -rc,
      but if not, then push it for 2.6.32.
      Signed-off-by: NValentin Longchamp <valentin.longchamp@epfl.ch>
      Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
      563abb4b
    • T
      percpu, sparc64: fix sparse possible cpu map handling · 74d46d6b
      Tejun Heo 提交于
      percpu code has been assuming num_possible_cpus() == nr_cpu_ids which
      is incorrect if cpu_possible_map contains holes.  This causes percpu
      code to access beyond allocated memories and vmalloc areas.  On a
      sparc64 machine with cpus 0 and 2 (u60), this triggers the following
      warning or fails boot.
      
       WARNING: at /devel/tj/os/work/mm/vmalloc.c:106 vmap_page_range_noflush+0x1f0/0x240()
       Modules linked in:
       Call Trace:
        [00000000004b17d0] vmap_page_range_noflush+0x1f0/0x240
        [00000000004b1840] map_vm_area+0x20/0x60
        [00000000004b1950] __vmalloc_area_node+0xd0/0x160
        [0000000000593434] deflate_init+0x14/0xe0
        [0000000000583b94] __crypto_alloc_tfm+0xd4/0x1e0
        [00000000005844f0] crypto_alloc_base+0x50/0xa0
        [000000000058b898] alg_test_comp+0x18/0x80
        [000000000058dad4] alg_test+0x54/0x180
        [000000000058af00] cryptomgr_test+0x40/0x60
        [0000000000473098] kthread+0x58/0x80
        [000000000042b590] kernel_thread+0x30/0x60
        [0000000000472fd0] kthreadd+0xf0/0x160
       ---[ end trace 429b268a213317ba ]---
      
      This patch fixes generic percpu functions and sparc64
      setup_per_cpu_areas() so that they handle sparse cpu_possible_map
      properly.
      
      Please note that on x86, cpu_possible_map() doesn't contain holes and
      thus num_possible_cpus() == nr_cpu_ids and this patch doesn't cause
      any behavior difference.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Acked-by: NDavid S. Miller <davem@davemloft.net>
      Cc: Ingo Molnar <mingo@elte.hu>
      74d46d6b
    • D
      ARM: S3C24XX: Fix clkout mpx error · 48ec45e7
      Davide Rizzo 提交于
      Bug correction: CLK Outputs cannot have XTAL as parent
      Signed-off-by: NDavide Rizzo <elpa.rizzo@gmail.com>
      [ben-linux@fluff.org: updated patch subject]
      Signed-off-by: NBen Dooks <ben-linux@fluff.org>
      48ec45e7
  7. 13 8月, 2009 3 次提交
  8. 12 8月, 2009 10 次提交
    • I
      perf_counter, x86: Fix/improve apic fallback · 04da8a43
      Ingo Molnar 提交于
      Johannes Stezenbach reported that his Pentium-M based
      laptop does not have the local APIC enabled by default,
      and hence perfcounters do not get initialized.
      
      Add a fallback for this case: allow non-sampled counters
      and return with an error on sampled counters. This allows
      'perf stat' to work out of box - and allows 'perf top'
      and 'perf record' to fall back on a hrtimer based sampling
      method.
      
      ( Passing 'lapic' on the boot line will allow hardware
        sampling to occur - but if the APIC is disabled
        permanently by the hardware then this fallback still
        allows more systems to use perfcounters. )
      
      Also decouple perfcounter support from X86_LOCAL_APIC.
      
      -v2: fix typo breaking counters on all other systems ...
      Reported-by: NJohannes Stezenbach <js@sig21.net>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Mike Galbraith <efault@gmx.de>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      04da8a43
    • O
      x86: Fix oops in identify_cpu() on CPUs without CPUID · e8055139
      Ondrej Zary 提交于
      Kernel is broken for x86 CPUs without CPUID since 2.6.28. It
      crashes with NULL pointer dereference in identify_cpu():
      
      766        generic_identify(c);
      767
      768-->     if (this_cpu->c_identify)
      769               this_cpu->c_identify(c);
      
      this_cpu is NULL. This is because it's only initialized in
      get_cpu_vendor() function, which is not called if the CPU has
      no CPUID instruction.
      Signed-off-by: NOndrej Zary <linux@rainbow-software.org>
      LKML-Reference: <200908112000.15993.linux@rainbow-software.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      e8055139
    • R
      arch/ia64/kernel/iosapic: missing test after ioremap() · e7369e01
      Roel Kluin 提交于
      Missing test after ioremap()
      Signed-off-by: NRoel Kluin <roel.kluin@gmail.com>
      Acked-by: NFenghua Yu <fenghua.yu@intel.com>
      e7369e01
    • F
      ia64/topology.c: exit cache_add_dev when kobject_init_and_add fails · 5359dffd
      Fenghua Yu 提交于
      Make cache_add_dev exit sysfs when kobject_init_and_add returns an error.
      Signed-off-by: NXiaotian Feng <dfeng@redhat.com>
      Signed-off-by: NFenghua Yu <fenghua.yu@intel.com>
      5359dffd
    • F
      arch/ia64/Makefile: Remove -mtune=merced in IA64 kernel build · bf2a4c72
      Fenghua Yu 提交于
      Between GCC version 3.4.0 and 4.3.3 (including 3.4.0 and 4.3.3), -mtune=merced
      is implemented in GCC. Starting from 4.4.0, -mtune=merced is deprecated.
      
      Even implemented in versions between 3.4.0 and 4.3.3, the -mtune=merced
      feature has been broken in some of the versions. For example, GCC 4.1.2 reports
      interanl tuning function errors during kernel building with -mtune=merced. Or
      GCC Bugzilla 16130 reports another -mtune=merced issue on GCC 3.4.1.
      
      So I would remove the -mtune=merced from IA64 kernel build. Without this option,
      kernel on Merced will remain the same except losing an unstable and out-of-date
      performance tunning feature.
      
      Since GCC version 3.4.0, -mtune=mckinley has been implemented. The
      -mtune=mckinley option functions the same as mtune=itanium2. And mtune=itanium2
      is the default option. So we don't need to add mtune=mckinley either since its
      been the default option in any GCC version which implements this option.
      Signed-off-by: NFenghua Yu <fenghua.yu@intel.com>
      bf2a4c72
    • J
      IA64: includecheck fix: ia64, pgtable.h · b5a88793
      Jaswinder Singh Rajput 提交于
      fix the following 'make includecheck' warning:
      
        arch/ia64/include/asm/pgtable.h: asm/processor.h is included more than once.
      Signed-off-by: NJaswinder Singh Rajput <jaswinderrajput@gmail.com>
      Acked-by: NFenghua Yu <fenghua.yu@intel.com>
      b5a88793
    • J
      IA64: includecheck fix: ia64, ia64_ksyms.c · cfa5f809
      Jaswinder Singh Rajput 提交于
      fix the following 'make includecheck' warning:
      
        arch/ia64/kernel/ia64_ksyms.c: asm/page.h is included more than once.
      Signed-off-by: NJaswinder Singh Rajput <jaswinderrajput@gmail.com>
      Acked-by: NFenghua Yu <fenghua.yu@intel.com>
      cfa5f809
    • J
      ia64: boolean __test_and_clear_bit · 8d6f9af9
      Johannes Weiner 提交于
      __test_and_clear_bit() returns a bitfield with the tested-for bit set.
      Make it consistent with the other bitops - of ia64 but also every
      other architecture - and return a boolean value.
      Signed-off-by: NJohannes Weiner <hannes@cmpxchg.org>
      Acked-by: NFenghua Yu <fenghua.yu@intel.com>
      8d6f9af9
    • F
      Bug Fix arch/ia64/kernel/pci-dma.c: fix recursive dma_supported() call in iommu_dma_supported() · 51b89f7a
      Fenghua Yu 提交于
      In commit 160c1d8e,
      dma_ops->dma_supported = iommu_dma_supported;
      
      This dma_ops->dma_supported is first called in platform_dma_init() during kernel
      boot. Then dma_ops->dma_supported will be called recursively in
      iommu_dma_supported.
      
      Kernel can not boot because kernel can not get out of iommu_dma_supported until
      it runs out of stack memory.
      Signed-off-by: NFenghua Yu <fenghua.yu@intel.com>
      51b89f7a
    • M
      IXP4xx: Fix IO_SPACE_LIMIT for 2.6.31-rc core PCI changes · dee2b904
      Mikael Pettersson 提交于
      2.6.31-rc kernels don't boot on my ixp4xx box (ds101), because the libata
      driver doesn't find the PCI IDE controller any more. 2.6.30 was fine.
      I traced this to a PCI update (1f82de10)
      in 2.6.30-git19. Diffing the kernel boot logs from 2.6.30-git18 and
      2.6.30-git19 illustrates the breakage:
      
      > --- dmesg-2.6.30-git18	2009-08-04 01:45:22.000000000 +0200
      > +++ dmesg-2.6.30-git19	2009-08-04 01:45:46.000000000 +0200
      > @@ -26,6 +26,13 @@
      >  pci 0000:00:02.2: PME# supported from D0 D1 D2 D3hot
      >  pci 0000:00:02.2: PME# disabled
      >  PCI: bus0: Fast back to back transfers disabled
      > +pci 0000:00:01.0: BAR 0: can't allocate I/O resource [0x10000-0xffff]
      > +pci 0000:00:01.0: BAR 1: can't allocate I/O resource [0x10000-0xffff]
      > +pci 0000:00:01.0: BAR 2: can't allocate I/O resource [0x10000-0xffff]
      > +pci 0000:00:01.0: BAR 3: can't allocate I/O resource [0x10000-0xffff]
      > +pci 0000:00:01.0: BAR 4: can't allocate I/O resource [0x10000-0xffff]
      > +pci 0000:00:02.0: BAR 4: can't allocate I/O resource [0x10000-0xffff]
      > +pci 0000:00:02.1: BAR 4: can't allocate I/O resource [0x10000-0xffff]
      >  bio: create slab <bio-0> at 0
      >  SCSI subsystem initialized
      >  NET: Registered protocol family 2
      > @@ -44,11 +51,7 @@
      >  console [ttyS0] enabled
      >  serial8250.0: ttyS1 at MMIO 0xc8001000 (irq = 13) is a XScale
      >  Driver 'sd' needs updating - please use bus_type methods
      > -PCI: enabling device 0000:00:01.0 (0140 -> 0141)
      > -scsi0 : pata_artop
      > -scsi1 : pata_artop
      > -ata1: PATA max UDMA/100 cmd 0x1050 ctl 0x1060 bmdma 0x1040 irq 28
      > -ata2: PATA max UDMA/100 cmd 0x1058 ctl 0x1064 bmdma 0x1048 irq 28
      > +pata_artop 0000:00:01.0: no available native port
      >  Using configured DiskOnChip probe address 0x50000000
      >  DiskOnChip found at 0x50000000
      >  NAND device: Manufacturer ID: 0x98, Chip ID: 0x73 (Toshiba NAND 16MiB 3,3V 8-bit)
      
      The specific change in 1f82de10 responsible
      for this failure turned out to be the following:
      
      > --- a/drivers/pci/probe.c
      > +++ b/drivers/pci/probe.c
      > @@ -193,7 +193,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
      >  		res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
      >  		if (type == pci_bar_io) {
      >  			l &= PCI_BASE_ADDRESS_IO_MASK;
      > -			mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff;
      > +			mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
      >  		} else {
      >  			l &= PCI_BASE_ADDRESS_MEM_MASK;
      >  			mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
      
      Every arch except arm's ixp4xx defines IO_SPACE_LIMIT as an all-bits-one
      bitmask, typically -1UL but sometimes only a 16-bit 0x0000ffff. But ixp4xx
      defines it as 0xffff0000, which is now causing the PCI failures.
      
      Russell King noted that ixp4xx has 64KB PCI IO space, so IO_SPACE_LIMIT
      should be 0x0000ffff. This patch makes that change, which fixes the PCI
      failures on my ixp4xx box.
      Signed-off-by: NMikael Pettersson <mikpe@it.uu.se>
      Signed-off-by: NKrzysztof Hałasa <khc@pm.waw.pl>
      dee2b904
  9. 11 8月, 2009 6 次提交
    • K
      x86: Clear incorrectly forced X86_FEATURE_LAHF_LM flag · fbd8b181
      Kevin Winchester 提交于
      Due to an erratum with certain AMD Athlon 64 processors, the
      BIOS may need to force enable the LAHF_LM capability.
      Unfortunately, in at least one case, the BIOS does this even
      for processors that do not support the functionality.
      
      Add a specific check that will clear the feature bit for
      processors known not to support the LAHF/SAHF instructions.
      Signed-off-by: NKevin Winchester <kjwinchester@gmail.com>
      Acked-by: NBorislav Petkov <petkovbb@googlemail.com>
      LKML-Reference: <4A80A5AD.2000209@gmail.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      fbd8b181
    • I
      perf_counter, x86: Fix generic cache events on P6-mobile CPUs · f64ccccb
      Ingo Molnar 提交于
      Johannes Stezenbach reported that 'perf stat' does not count
      cache-miss and cache-references events on his Pentium-M based
      laptop.
      
      This is because we left them blank in p6_perfmon_event_map[],
      fill them in.
      Reported-by: NJohannes Stezenbach <js@sig21.net>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Mike Galbraith <efault@gmx.de>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      f64ccccb
    • I
      perf_counter, x86: Fix lapic printk message · 3c581a7f
      Ingo Molnar 提交于
      Instead of this garbled bootup on UP Pentium-M systems:
      
      [    0.015048] Performance Counters:
      [    0.016004] no Local APIC, try rebooting with lapicno PMU driver, software counters only.
      
      Print:
      
      [    0.015050] Performance Counters:
      [    0.016004] no APIC, boot with the "lapic" boot parameter to force-enable it.
      [    0.017003] no PMU driver, software counters only.
      
      Cf: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      3c581a7f
    • D
      x86, mce: therm_throt - change when we print messages · 0d01f314
      Dmitry Torokhov 提交于
      My Latitude d630 seems to be handling thermal events in SMI by
      lowering the max frequency of the CPU till it cools down but
      still leaks the "everything is normal" events.
      
      This spams the console and with high priority printks.
      
      Adjust therm_throt driver to only print messages about the fact
      that temperatire returned back to normal when leaving the
      throttling state.
      
      Also lower the severity of "back to normal" message from
      KERN_CRIT to KERN_INFO.
      Signed-off-by: NDmitry Torokhov <dtor@mail.ru>
      Acked-by: NH. Peter Anvin <hpa@zytor.com>
      LKML-Reference: <20090810051513.0558F526EC9@mailhub.coreip.homeip.net>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      0d01f314
    • S
      x86: Add reboot quirk for every 5 series MacBook/Pro · 3e03bbea
      Shunichi Fuji 提交于
      Reboot does not work on my MacBook Pro 13 inch (MacBookPro5,5)
      too. It seems all unibody MacBook and MacBookPro require
      PCI reboot handling, i guess.
      
      Following model/machine ID list shows unibody MacBook/Pro have
      the 5 series of model number:
      
         http://www.everymac.com/systems/by_capability/macs-by-machine-model-machine-id.htmlSigned-off-by: NShunichi Fuji <palglowr@gmail.com>
      Cc: Ozan Çağlayan <ozan@pardus.org.tr>
      LKML-Reference: <30046e3b0908101134p6487ddbftd8776e4ddef204be@mail.gmail.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      3e03bbea
    • L
      x86: Fix serialization in pit_expect_msb() · b6e61eef
      Linus Torvalds 提交于
      Wei Chong Tan reported a fast-PIT-calibration corner-case:
      
      | pit_expect_msb() is vulnerable to SMI disturbance corner case
      | in some platforms which causes /proc/cpuinfo to show wrong
      | CPU MHz value when quick_pit_calibrate() jumps to success
      | section.
      
      I think that the real issue isn't even an SMI - but the fact
      that in the very last iteration of the loop, there's no
      serializing instruction _after_ the last 'rdtsc'. So even in
      the absense of SMI's, we do have a situation where the cycle
      counter was read without proper serialization.
      
      The last check should be done outside the outer loop, since
      _inside_ the outer loop, we'll be testing that the PIT has
      the right MSB value has the right value in the next iteration.
      
      So only the _last_ iteration is special, because that's the one
      that will not check the PIT MSB value any more, and because the
      final 'get_cycles()' isn't serialized.
      
      In other words:
      
       - I'd like to move the PIT MSB check to after the last
         iteration, rather than in every iteration
      
       - I think we should comment on the fact that it's also a
         serializing instruction and so 'fences in' the TSC read.
      
      Here's a suggested replacement.
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      Reported-by: N"Tan, Wei Chong" <wei.chong.tan@intel.com>
      Tested-by: N"Tan, Wei Chong" <wei.chong.tan@intel.com>
      LKML-Reference: <B28277FD4E0F9247A3D55704C440A140D5D683F3@pgsmsx504.gar.corp.intel.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      b6e61eef
  10. 10 8月, 2009 1 次提交