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  1. 26 12月, 2013 2 次提交
  3. 24 12月, 2013 6 次提交
  5. 19 12月, 2013 2 次提交
  7. 05 11月, 2013 1 次提交
  9. 06 8月, 2013 1 次提交
  11. 15 7月, 2013 1 次提交
    • S
      ARM: imx: fix vf610 enet module clock selection · 4f71612e
      由 Shawn Guo 提交于 
      The fec/enet driver calculates MDC rate with the formula below.

  ref_freq / ((MII_SPEED + 1) x 2)

The ref_freq here is the fec internal module clock, which is missing
from clk-vf610 clock driver right now.  And clk-vf610 driver mistakenly
supplies RMII clock (50 MHz) as the source to fec.  This results in the
situation that fec driver gets ref_freq as 50 MHz, while physically it
runs at 66 MHz (fec module clock physically sources from ipg which runs
at 66 MHz).  That's why software expects MDC runs at 2.5 MHz, while the
measurement tells it runs at 3.3 MHz.  And this causes the PHY KSZ8041
keeps swithing between Full and Half mode as below.

  libphy: 400d0000.etherne:00 - Link is Up - 100/Full
  libphy: 400d0000.etherne:00 - Link is Up - 100/Half
  libphy: 400d0000.etherne:00 - Link is Up - 100/Full
  libphy: 400d0000.etherne:00 - Link is Up - 100/Half
  libphy: 400d0000.etherne:00 - Link is Up - 100/Full
  libphy: 400d0000.etherne:00 - Link is Up - 100/Half

Add the missing module clock for ENET0 and ENET1, and correct the clock
supplying in device tree to fix above issue.

Thanks to Alison Wang <b18965@freescale.com> for debugging the issue.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      4f71612e
  13. 17 6月, 2013 2 次提交
  15. 29 5月, 2013 3 次提交
    • H
      ARM: tegra114: create a DT header defining CLK IDs · 992bb598
      由 Hiroshi Doyu 提交于 
      Create a header file to define the clock IDs used by the Tegra114 clock
binding. Remove the list of definitions from the binding documentation,
and refer the reader to the header file.

This will allow the same header to be used by both device tree files,
and drivers implementing this binding, which guarantees that the two
stay in sync. This also makes device trees more readable by using names
instead of magic numbers.
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
[swarren, add header to clock/ instead of clk/ to match binding location]
Signed-off-by: NStephen Warren <swarren@nvidia.com>
      992bb598
    • H
      ARM: tegra30: create a DT header defining CLK IDs · 9513109d
      由 Hiroshi Doyu 提交于 
      Create a header file to define the clock IDs used by the Tegra30 clock
binding. Remove the list of definitions from the binding documentation,
and refer the reader to the header file.

This will allow the same header to be used by both device tree files,
and drivers implementing this binding, which guarantees that the two
stay in sync. This also makes device trees more readable by using names
instead of magic numbers.
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
[swarren, add header to clock/ instead of clk/ to match binding location]
Signed-off-by: NStephen Warren <swarren@nvidia.com>
      9513109d
    • H
      ARM: tegra20: create a DT header defining CLK IDs · ec23ad67
      由 Hiroshi Doyu 提交于 
      Create a header file to define the clock IDs used by the Tegra20 clock
binding. Remove the list of definitions from the binding documentation,
and refer the reader to the header file.

This will allow the same header to be used by both device tree files,
and drivers implementing this binding, which guarantees that the two
stay in sync. This also makes device trees more readable by using names
instead of magic numbers.
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
[swarren, add header to clock/ instead of clk/ to match binding location]
Signed-off-by: NStephen Warren <swarren@nvidia.com>
      ec23ad67