The CPU_2X clock does not have a classical in-kernel user, but is,
amongst other things, required for OCM and debug access. Make sure this
clock is not mistakenly disabled during boot up by enabling it in the
platform's clock driver.

Cc: stable@vger.kernel.org # 3.11+
Fixes: 0ee52b15 'clk: zynq: Add clock controller driver'
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Merge tag 'sunxi-clocks-for-3.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Allwinner clock changes for 3.20

The set of clock changes for the 3.20 merge window, with mostly:
  - Some PLL fixes for the A80 and A31
  - The MMC custom phase functions are removed, and moved over to the generic
    phase API.
  - Add the A80 MMC clocks

Some DT changes slipped here as well, to preserve bisectability.

Merge tag 'v3.20-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

The two big changes are the additional of the watchdog clock, which
we currently only "fake" as the clock gate control is living in a
very strange place, but the watchdog driver needs to read the clock
rate from it and the setting of rk3288 plls to slow mode upon suspend.

Other than that some more exported clocks and a CLK_SET_RATE_PARENT
flag for the uart clocks.

These modules don't need to include clk-private.h. Replace the
include with clk.h because these modules are clock consumers and
also include clk-provider.h in clk/ti.h because struct
clk_hw_omap has a struct clk_hw embedded in it.

Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

These drivers don't need to include clk-private.h. Remove the
include.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NUlf Hansson <ulf.hansson@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

The phase setter and getter were not exported until now, which was causing
build breakages when callers were compiled as module. Export these two
functions.
Reported-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Document the LPASS (low power audio subsystem) clock controller
found on Qualcomm devices.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Add an LCC driver for MSM8960/APQ8064 that supports the i2s,
slimbus, and pcm clocks.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Tested-by: NKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Add an LCC driver for IPQ806x that supports the i2s, S/PDIF, and
pcm clocks.
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NJosh Cartwright <joshc@codeaurora.org>
[sboyd@codeaurora.org: Reworded commit text, added Kconfig
select, fleshed out Kconfig description a bit more, added pll4
configuration and reworked probe for it, added muxes, split out
dt-binding file]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Tested-by: NKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Add defines to make more human readable numbers for the lpass
clock controller found on IPQ806x SoCs. Also remove the PLL4
define in gcc to avoid #define conflicts because that clock
doesn't exist in gcc, instead it lives in lcc.
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
[sboyd@codeaurora.org: Split off into separate patch]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Tested-by: NKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Add support for muxes that use regmap instead of readl/writel
directly. We don't support as many features as clk-mux.c, but
this is good enough to support getting and setting parents.
Adding a table based lookup can be added in the future if needed.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Tested-by: NKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Add support for dividers that use regmap instead of readl/writel.
Signed-off-by: NJosh Cartwright <joshc@codeaurora.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
[sboyd@codeaurora.org: Switch to using generic divider code, drop
enable/disable, reword commit text]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Tested-by: NKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Some devices don't use mmio to interact with dividers. Split out the
logic from the register read/write parts so that we can reuse the
division logic elsewhere.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Tested-by: NKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Some clock drivers want to find the closest rate on the input of
a mux instead of a rate that's less than or equal to the desired
rate. Add a generic mux function to support this.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Tested-by: NKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Some of the clks can be registered & unregistered before the clk related debugfs
entries are initialized at late_initcall. In the unregister path checking for only
dentry before clk_debug_init() would lead dangling pointers in the debug clk list,
because the list is already populated in register path and the clk pointer freed in
unregister path.
The side effect of not removing it from the list is either a null pointer
dereference or if lucky to boot the system, the number of clk entries in
debugfs disappear.

We could add more checks like if (inited && !clk->dentry) but just removing
the check for dentry made more sense as debugfs_remove_recursive() seems to be
safe with null pointers. This will ensure that the unregistering clk would be
removed from the debug list in all the code paths.

Without this patch kernel would crash with log:
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c0204000
[00000000] *pgd=00000000
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 1 PID: 1 Comm: swapper/0 Tainted: G    B          3.19.0-rc3-00007-g412f9ba-dirty #840
Hardware name: Qualcomm (Flattened Device Tree)
task: ed948000 ti: ed944000 task.ti: ed944000
PC is at strlen+0xc/0x40
LR is at __create_file+0x64/0x1dc
pc : [<c04ee604>]    lr : [<c049f1c4>]    psr: 60000013
sp : ed945e40  ip : ed945e50  fp : ed945e4c
r10: 00000000  r9 : c1006094  r8 : 00000000
r7 : 000041ed  r6 : 00000000  r5 : ed4af998  r4 : c11b5e28
r3 : 00000000  r2 : ed945e38  r1 : a0000013  r0 : 00000000
Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
Control: 10c5787d  Table: 8020406a  DAC: 00000015
Process swapper/0 (pid: 1, stack limit = 0xed944248)
Stack: (0xed945e40 to 0xed946000)
5e40: ed945e7c ed945e50 c049f1c4 c04ee604 c0fc2fa4 00000000 ecb748c0 c11c2b80
5e60: c0beec04 0000011c c0fc2fa4 00000000 ed945e94 ed945e80 c049f3e0 c049f16c
5e80: 00000000 00000000 ed945eac ed945e98 c08cbc50 c049f3c0 ecb748c0 c11c2b80
5ea0: ed945ed4 ed945eb0 c0fc3080 c08cbc30 c0beec04 c107e1d8 ecdf0600 c107e1d8
5ec0: c107e1d8 ecdf0600 ed945f54 ed945ed8 c0208ed4 c0fc2fb0 c026a784 c04ee628
5ee0: ed945f0c ed945ef0 c0f5d600 c04ee604 c0f5d5ec ef7fcc7d c0b40ecc 0000011c
5f00: ed945f54 ed945f10 c026a994 c0f5d5f8 c04ecc00 00000007 ef7fcc95 00000007
5f20: c0e90744 c0dd0884 ed945f54 c106cde0 00000007 c117f8c0 0000011c c0f5d5ec
5f40: c1006094 c100609c ed945f94 ed945f58 c0f5de34 c0208e50 00000007 00000007
5f60: c0f5d5ec be9b5ae0 00000000 c117f8c0 c0af1680 00000000 00000000 00000000
5f80: 00000000 00000000 ed945fac ed945f98 c0af169c c0f5dd2c ed944000 00000000
5fa0: 00000000 ed945fb0 c020f298 c0af168c 00000000 00000000 00000000 00000000
5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
5fe0: 00000000 00000000 00000000 00000000 00000013 00000000 ebcc6d33 bfffca73
[<c04ee604>] (strlen) from [<c049f1c4>] (__create_file+0x64/0x1dc)
[<c049f1c4>] (__create_file) from [<c049f3e0>] (debugfs_create_dir+0x2c/0x34)
[<c049f3e0>] (debugfs_create_dir) from [<c08cbc50>] (clk_debug_create_one+0x2c/0x16c)
[<c08cbc50>] (clk_debug_create_one) from [<c0fc3080>] (clk_debug_init+0xdc/0x144)
[<c0fc3080>] (clk_debug_init) from [<c0208ed4>] (do_one_initcall+0x90/0x1e0)
[<c0208ed4>] (do_one_initcall) from [<c0f5de34>] (kernel_init_freeable+0x114/0x1e0)
[<c0f5de34>] (kernel_init_freeable) from [<c0af169c>] (kernel_init+0x1c/0xfc)
[<c0af169c>] (kernel_init) from [<c020f298>] (ret_from_fork+0x14/0x3c)
Code: c0b40ecc e1a0c00d e92dd800 e24cb004 (e5d02000)
---[ end trace b940e45b5e25c1e7 ]---

Fixes: 6314b679 "clk: Don't hold prepare_lock across debugfs creation"
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Merge branch 'clk-shmobile-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

For all pll-s on sun6i n == 0 means use a multiplier of 1, rather then 0 as
it means on sun4i / sun5i / sun7i. n_start = 1 is already correctly set
for sun6i pll6, but was missing for pll1, this commit fixes this.

Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The old implementation of sun9i_a80_get_pll4_factors() has several issues,
it checks against 256 / 512 in various places where it should use 255 / 511,
it does the wrong thing for low frequencies which are an even multiple of
6 MHz, e.g. if you ask it for 72 MHz it will result in 144 Mhz, and it does
not take into account that n must be at least 12. Moreover it is quite hard
to read / follow it.

This commit rewrites it to be correct in all cases, and makes it much easier
to follow the code / to read.

Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This new function is similar to clk_set_parent(), except that it doesn't
actually change the parent. It merely checks that the given parent clock
can be a parent for the given clock.

A situation where this is useful is to check that a particular setup is
valid before switching to it. One specific use-case for this is atomic
modesetting in the DRM framework where setting a mode is divided into a
check phase where a given configuration is validated before applying
changes to the hardware.

Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

The pclk supplying the watchdog is controlled via the SGRF register area.
Currently we don't have any clock-type handling external clock bits like
this one. Additionally the SGRF isn't even writable in every boot mode.

But still the clock control is available and in the future someone might
want to use it. Therefore define a simple clock for the time being so
that the watchdog driver can read its rate.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Process-Voltage-Temperatiure Monitor block on RK3288 has two clocks:
PVTM_CORE and PVTM_GPU.
Signed-off-by: NHuang Lin <hl@rock-chips.com>
Signed-off-by: NDmitry Torokhov <dtor@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Use the clock ID for usbphy480m_src so that we can find
this clock node in dts.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Adds a new id for the pclk supplying the watchdog on rk3288 socs.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>

Provide CLK support for Alphascale ASM9260 SoC.
Signed-off-by: NOleksij Rempel <linux@rempel-privat.de>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Debugging eMMC on upstream kernels it has been noticed that when the
targetpack configures MMC0 clock to 200Mhz (required to switch to
HS200) then everything works OK. However if the kernel sets the
clock rate using clk_set_rate, then the eMMC card initialisation
fails with timeouts. Lower clock speeds (the default being 50Mhz)
work ok, but they we fail to get good eMMC transfer rates.

Looking through the vendor kernel clock driver reveals Giuseppe
had already fixed this issue, but the patch hasn't made its way
upstream.

The issue is fixed by changing the logic to manage the pdiv and
fdiv divisors used for setting the rate inside the flexgen driver code.

Pdiv is mainly targeted for low freq results, while fdiv should be
used for divs =< 64. The other way can lead to 'duty cycle'
issues.

I have changed the original patch to keep the original behaviour
in cases where the div is >64 which matches the original comment
and patch description more closely. Although no clocks appear to hit
this case currently when booting an upstream kernel.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Freescale introduced new ARM-based socs which using the compatible
clock IP block with PowerPC-based socs'. So this driver can be used
on both platforms.
Updated relevant descriptions and renamed this driver to better
represent its meaning and keep the function of driver untouched.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

redefine variable clocks_per_pll as a struct member

If there are multiple PLL clock nodes, this variable will
get overwritten. Redefining it as a struct member can avoid that.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

- Clock definitions for Exynos7 SoC peripheral devices:
  video scaler, USB, DMA, SPI and the audio subsystem.

The clocks on ti81xx are not compatible with omap3. On dm816x
the clock source is a FAPLL (Flying Adder PLL), and on dm814x
there seems to be an APLL (All Digital PLL).

Let's fix up things for dm816x in preparation for adding the
FAPLL support. As we already have a dummy ti81xx_dt_clk_init()
in place, let's use that for now to avoid adding a dependency
to the omap patches.

Later on if somebody adds dm814x support we can split the
ti81xx_dt_clk_init() clock init function as needed.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

On dm816x the clocks are sourced from a FAPLL (Flying Adder PLL)
that does not seem to be used on the other omap variants.

There are four instances of the FAPLL on dm816x that each have three
to seven child synthesizers.

I've set up the FAPLL as a single fapll.c driver. Later on we could
potentially have the PLL code generic. To do that, we would have to
consider the following:

1. Setting the PLL to bypass mode also sets the child synthesizers
   into bypass mode. As the bypass rate can also be generated by
   the PLL in regular mode, there's no way for the child synthesizers
   to detect the bypass mode based on the parent clock rate.

2. The PLL registers control the power for each of the child
   syntheriser.

Note that the clocks are currently still missing the set_rate
implementation so things are still running based on the bootloader
values. That's OK for now as most of the outputs have dividers and
those can be set using the existing TI component clock code.

I have verified that the extclk rates are correct for a few clocks,
so adding the set_rate support should be fairly trivial later on.

This code is partially based on the TI81XX-LINUX-PSP-04.04.00.02
patches published at:

http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

We don't need to fetch the parent index for clocks if they only
have one parent. Doing this also avoid an unnecessary allocation
for the parent cache.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

In case CLK_GATE_HIWORD_MASK flag is passed to clk_register_gate(), the bit #
should be no higher than 15, however the corresponding check is obviously off-
by-one.

Fixes: 04577994 ("clk: gate: add CLK_GATE_HIWORD_MASK")
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

In order to fix the following section mismatch warning:
  WARNING: drivers/clk/built-in.o(.data+0xe4): Section mismatch in reference from the variable ppc_corenet_clk_driver to the function .init.text:ppc_corenet_clk_probe()
  The variable ppc_corenet_clk_driver references
  the function __init ppc_corenet_clk_probe()
  If the reference is valid then annotate the
  variable with __init* or __refdata (see linux/init.h) or name the variable:
  *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

  WARNING: drivers/clk/built-in.o(.data+0x10c): Section mismatch in reference from the variable ppc_corenet_clk_driver to the variable .init.rodata:ppc_clk_ids
  The variable ppc_corenet_clk_driver references
  the variable __initconst ppc_clk_ids
  If the reference is valid then annotate the
  variable with __init* or __refdata (see linux/init.h) or name the variable:
  *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

We can't just add the __init annotation to ppc_corenet_clk_driver or
remove the __init from ppc_corenet_clk_probe() and ppc_clk_ids.
So choose to use CLK_OF_DECLARE to scan and init the clock devices.
Signed-off-by: NKevin Hao <haokexin@gmail.com>
Acked-by: NScott Wood <scottwood@freescale.com>
Acked-by: NMichael Turquette <mturquette@linaro.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

So the boards which has COMMON_CLK enabled don't have to
invoke this in its board specific file.
Signed-off-by: NKevin Hao <haokexin@gmail.com>
Acked-by: NScott Wood <scottwood@freescale.com>
Acked-by: NMichael Turquette <mturquette@linaro.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

On the A80 SoC, the 4 mmc controllers each have a separate register
controlling their register access clocks and reset controls. These
registers in turn share a ahb clock gate and reset control.

This patch adds a platform device driver for these controls. It
requires both clocks and reset controls to be available, so using
CLK_OF_DECLARE might not be the best way.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The module 0 style clocks, or storage module clocks as named in the
official SDK, are almost the same as the module 0 clocks on earlier
Allwinner SoCs. The only difference is wider mux register bits.

As with earlier Allwinner SoCs, mmc module clocks are a special case
of mod0 clocks, with phase controls for 2 child clocks, output and
sample.

This patch adds support for both.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The memory allocated by basic clock divider/gate/mux (struct clk_gate,
clk_divider and clk_mux) was leaking. During driver unbind or probe
failure the driver only unregistered the clocks.

Use clk_unregister_{gate,divider,mux} to release all resources.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

The common clk_register_{divider,gate,mux} functions allocated memory
for internal data which wasn't freed anywhere. Drivers using these
helpers could only unregister clocks but the memory would still leak.

Add corresponding unregister functions which will release all resources.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>