Correction of the omap_usb3_dpll_params array when the sys_clk_rate is
20MHz.
Signed-off-by: NNikhil Devshatwar <nikhil.nd@ti.com>
Signed-off-by: NRuchika Kharwar <ruchika@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Addition of the M and N recommended values for the USB3 PHY DPLL.
Sysclk for DRA7xx is 20MHz.

This yields:
Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz
Signed-off-by: NRuchika Kharwar <ruchika@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

this will make sure that we have sensible names
for all phy drivers. Current situation was already
quite bad with too generic names being used.
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Use the newly introduced devm_ioremap_resource() instead of
devm_request_and_ioremap() which provides more consistent error handling.

devm_ioremap_resource() provides its own error messages; so all explicit
error messages can be removed from the failure code paths.
Reviewed-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Added a driver for usb3 phy that handles the interaction between usb phy
device and dwc3 controller.

This also includes device tree support for usb3 phy driver and
the documentation with device tree binding information is updated.

Currently writing to control module register is taken care in this
driver which will be removed once the control module driver is in place.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NMoiz Sonasath <m-sonasath@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>