1. 05 5月, 2014 2 次提交
  2. 08 4月, 2014 1 次提交
  3. 20 3月, 2014 1 次提交
    • A
      audit: Add CONFIG_HAVE_ARCH_AUDITSYSCALL · 7a017721
      AKASHI Takahiro 提交于
      Currently AUDITSYSCALL has a long list of architecture depencency:
             depends on AUDIT && (X86 || PARISC || PPC || S390 || IA64 || UML ||
      		SPARC64 || SUPERH || (ARM && AEABI && !OABI_COMPAT) || ALPHA)
      The purpose of this patch is to replace it with HAVE_ARCH_AUDITSYSCALL
      for simplicity.
      Signed-off-by: NAKASHI Takahiro <takahiro.akashi@linaro.org>
      Acked-by: Will Deacon <will.deacon@arm.com> (arm)
      Acked-by: Richard Guy Briggs <rgb@redhat.com> (audit)
      Acked-by: Matt Turner <mattst88@gmail.com> (alpha)
      Acked-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc)
      Signed-off-by: NEric Paris <eparis@redhat.com>
      7a017721
  4. 19 3月, 2014 1 次提交
  5. 14 3月, 2014 1 次提交
  6. 05 3月, 2014 1 次提交
    • M
      x86/efi: Wire up CONFIG_EFI_MIXED · 7d453eee
      Matt Fleming 提交于
      Add the Kconfig option and bump the kernel header version so that boot
      loaders can check whether the handover code is available if they want.
      
      The xloadflags field in the bzImage header is also updated to reflect
      that the kernel supports both entry points by setting both of
      XLF_EFI_HANDOVER_32 and XLF_EFI_HANDOVER_64 when CONFIG_EFI_MIXED=y.
      XLF_CAN_BE_LOADED_ABOVE_4G is disabled so that the kernel text is
      guaranteed to be addressable with 32-bits.
      
      Note that no boot loaders should be using the bits set in xloadflags to
      decide which entry point to jump to. The entire scheme is based on the
      concept that 32-bit bootloaders always jump to ->handover_offset and
      64-bit loaders always jump to ->handover_offset + 512. We set both bits
      merely to inform the boot loader that it's safe to use the native
      handover offset even if the machine type in the PE/COFF header claims
      otherwise.
      Signed-off-by: NMatt Fleming <matt.fleming@intel.com>
      7d453eee
  7. 28 2月, 2014 2 次提交
  8. 19 2月, 2014 1 次提交
  9. 12 2月, 2014 2 次提交
  10. 25 1月, 2014 1 次提交
  11. 24 1月, 2014 2 次提交
  12. 21 1月, 2014 1 次提交
  13. 16 1月, 2014 1 次提交
  14. 15 1月, 2014 1 次提交
  15. 14 1月, 2014 1 次提交
  16. 09 1月, 2014 1 次提交
    • D
      arch: x86: New MailBox support driver for Intel SOC's · 46184415
      David E. Box 提交于
      Current Intel SOC cores use a MailBox Interface (MBI) to provide access to
      configuration registers on devices (called units) connected to the system
      fabric. This is a support driver that implements access to this interface on
      those platforms that can enumerate the device using PCI. Initial support is for
      BayTrail, for which port definitons are provided. This is a requirement for
      implementing platform specific features (e.g. RAPL driver requires this to
      perform platform specific power management using the registers in PUNIT).
      Dependant modules should select IOSF_MBI in their respective Kconfig
      configuraiton. Serialized access is handled by all exported routines with
      spinlocks.
      
      The API includes 3 functions for access to unit registers:
      
      int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
      int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
      int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
      
      port:	indicating the unit being accessed
      opcode:	the read or write port specific opcode
      offset:	the register offset within the port
      mdr:	the register data to be read, written, or modified
      mask:	bit locations in mdr to change
      
      Returns nonzero on error
      
      Note: GPU code handles access to the GFX unit. Therefore access to that unit
      with this driver is disallowed to avoid conflicts.
      Signed-off-by: NDavid E. Box <david.e.box@linux.intel.com>
      Link: http://lkml.kernel.org/r/1389216471-734-1-git-send-email-david.e.box@linux.intel.comSigned-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
      Cc: Matthew Garrett <mjg59@srcf.ucam.org>
      46184415
  17. 03 1月, 2014 1 次提交
  18. 20 12月, 2013 1 次提交
    • K
      stackprotector: Unify the HAVE_CC_STACKPROTECTOR logic between architectures · 19952a92
      Kees Cook 提交于
      Instead of duplicating the CC_STACKPROTECTOR Kconfig and
      Makefile logic in each architecture, switch to using
      HAVE_CC_STACKPROTECTOR and keep everything in one place. This
      retains the x86-specific bug verification scripts.
      Signed-off-by: NKees Cook <keescook@chromium.org>
      Cc: Arjan van de Ven <arjan@linux.intel.com>
      Cc: Michal Marek <mmarek@suse.cz>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      Cc: Shawn Guo <shawn.guo@linaro.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-mips@linux-mips.org
      Cc: linux-arch@vger.kernel.org
      Link: http://lkml.kernel.org/r/1387481759-14535-2-git-send-email-keescook@chromium.orgSigned-off-by: NIngo Molnar <mingo@kernel.org>
      19952a92
  19. 11 12月, 2013 1 次提交
  20. 02 12月, 2013 1 次提交
  21. 15 11月, 2013 2 次提交
  22. 12 11月, 2013 1 次提交
  23. 06 11月, 2013 2 次提交
  24. 26 10月, 2013 1 次提交
  25. 24 10月, 2013 1 次提交
  26. 14 10月, 2013 1 次提交
  27. 13 10月, 2013 2 次提交
  28. 06 10月, 2013 2 次提交
  29. 05 10月, 2013 1 次提交
    • T
      x86, build, pci: Fix PCI_MSI build on !SMP · 0dbc6078
      Thomas Petazzoni 提交于
      Commit ebd97be6 ('PCI: remove ARCH_SUPPORTS_MSI kconfig option')
      removed the ARCH_SUPPORTS_MSI option which architectures could select
      to indicate that they support MSI. Now, all architectures are supposed
      to build fine when MSI support is enabled: instead of having the
      architecture tell *when* MSI support can be used, it's up to the
      architecture code to ensure that MSI support can be enabled.
      
      On x86, commit ebd97be6 removed the following line:
      
        select ARCH_SUPPORTS_MSI if (X86_LOCAL_APIC && X86_IO_APIC)
      
      Which meant that MSI support was only available when the local APIC
      and I/O APIC were enabled. While this is always true on SMP or x86-64,
      it is not necessarily the case on i386 !SMP.
      
      The below patch makes sure that the local APIC and I/O APIC support is
      always enabled when MSI support is enabled. To do so, it:
      
       * Ensures the X86_UP_APIC option is not visible when PCI_MSI is
         enabled. This is the option that allows, on UP machines, to enable
         or not the APIC support. It is already not visible on SMP systems,
         or x86-64 systems, for example. We're simply also making it
         invisible on i386 MSI systems.
      
       * Ensures that the X86_LOCAL_APIC and X86_IO_APIC options are 'y'
         when PCI_MSI is enabled.
      
      Notice that this change requires a change in drivers/iommu/Kconfig to
      avoid a recursive Kconfig dependencey. The AMD_IOMMU option selects
      PCI_MSI, but was depending on X86_IO_APIC. This dependency is no
      longer needed: as soon as PCI_MSI is selected, the presence of
      X86_IO_APIC is guaranteed. Moreover, the AMD_IOMMU already depended on
      X86_64, which already guaranteed that X86_IO_APIC was enabled, so this
      dependency was anyway redundant.
      Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
      Link: http://lkml.kernel.org/r/1380794354-9079-1-git-send-email-thomas.petazzoni@free-electrons.comReported-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      Acked-by: NBjorn Helgaas <bhelgaas@google.com>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      0dbc6078
  30. 01 10月, 2013 1 次提交
    • F
      x86: Tell about irq stack coverage · a2cd11f7
      Frederic Weisbecker 提交于
      x86-64 runs irq_exit() under the irq stack. So it can afford
      to run softirqs in hardirq exit without the need to switch
      the stacks. The hardirq stack is good enough for that.
      
      Now x86-64 runs softirqs in the hardirq stack anyway, so what we
      mostly skip is some needless per cpu refcounting updates there.
      
      x86-32 is not concerned because it only runs the irq handler on
      the irq stack.
      Acked-by: NLinus Torvalds <torvalds@linux-foundation.org>
      Signed-off-by: NFrederic Weisbecker <fweisbec@gmail.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@au1.ibm.com>
      Cc: Ingo Molnar <mingo@kernel.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: H. Peter Anvin <hpa@zytor.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Paul Mackerras <paulus@au1.ibm.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: James E.J. Bottomley <jejb@parisc-linux.org>
      Cc: Helge Deller <deller@gmx.de>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      a2cd11f7
  31. 25 9月, 2013 2 次提交