1. 28 5月, 2014 16 次提交
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      MIPS: pm-cps: add PM state entry code for CPS systems · 3179d37e
      Paul Burton 提交于
      This patch adds code to generate entry & exit code for various low power
      states available on systems based around the MIPS Coherent Processing
      System architecture (ie. those with a Coherence Manager, Global
      Interrupt Controller & for >=CM2 a Cluster Power Controller). States
      supported are:
      
        - Non-coherent wait. This state first leaves the coherent domain and
          then executes a regular MIPS wait instruction. Power savings are
          found from the elimination of coherency interventions between the
          core and any other coherent requestors in the system.
      
        - Clock gated. This state leaves the coherent domain and then gates
          the clock input to the core. This removes all dynamic power from the
          core but leaves the core at the mercy of another to restart its
          clock. Register state is preserved, but the core can not service
          interrupts whilst its clock is gated.
      
        - Power gated. This deepest state removes all power input to the core.
          All register state is lost and the core will restart execution from
          its BEV when another core powers it back up. Because register state
          is lost this state requires cooperation with the CONFIG_MIPS_CPS SMP
          implementation in order for the core to exit the state successfully.
      
      The code will detect which states are available on the current system
      during boot & generate the entry/exit code for those states. This will
      be used by cpuidle & hotplug implementations.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      3179d37e
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      MIPS: smp-cps: use CPC core-other locking · dd9233d0
      Paul Burton 提交于
      The core which the CPC core-other region relates to is based upon the
      core-local core-other addressing register. As its name suggests this
      register is shared between all VPEs within a core, and if there is a
      possibility that multiple VPEs within a core will attempt to access
      another core simultaneously then locking is required. This wasn't
      previously a problem with the only user being cpu0 during boot, but will
      be an issue once hotplug is implemented & may race with other users such
      as cpuidle.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      dd9233d0
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      MIPS: smp-cps: flush cache after patching mips_cps_core_entry · 0f4d3d11
      Paul Burton 提交于
      The start of mips_cps_core_entry is patched in order to provide the code
      with the address of the CM register region at a point where it will be
      running non-coherent with the rest of the system. However the cache
      wasn't being flushed after that patching which could in principle lead
      to secondary cores using an invalid CM base address.
      
      The patching is moved to cps_prepare_cpus since local_flush_icache_range
      has not been initialised at the point cps_smp_setup is called.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      0f4d3d11
    • P
      MIPS: smp-cps: function to determine whether CPS SMP is in use · 68c1232f
      Paul Burton 提交于
      The core power down state for cpuidle will require that the CPS SMP
      implementation is in use. This patch provides a mips_cps_smp_in_use
      function which determines whether or not the CPS SMP implementation is
      currently in use.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      68c1232f
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      MIPS: smp-cps: rework core/VPE initialisation · 245a7868
      Paul Burton 提交于
      When hotplug and/or a powered down idle state are supported cases will
      arise where a non-zero VPE must be brought online without VPE 0, and it
      where multiple VPEs must be onlined simultaneously. This patch prepares
      for that by:
      
        - Splitting struct boot_config into core & VPE boot config structures,
          allocated one per core or VPE respectively. This allows for multiple
          VPEs to be onlined simultaneously without clobbering each others
          configuration.
      
        - Indicating which VPEs should be online within a core at any given
          time using a bitmap. This allows multiple VPEs to be brought online
          simultaneously and also indicates to VPE 0 whether it should halt
          after starting any non-zero VPEs that should be online within the
          core. For example if all VPEs within a core are offlined via hotplug
          and the user onlines the second VPE within that core:
      
            1) The core will be powered up.
      
            2) VPE 0 will run from the BEV (ie. mips_cps_core_entry) to
               initialise the core.
      
            3) VPE 0 will start VPE 1 because its bit is set in the cores
               bitmap.
      
            4) VPE 0 will halt itself because its bit is clear in the cores
               bitmap.
      
        - Moving the core & VPE initialisation to assembly code which does not
          make any use of the stack. This is because if a non-zero VPE is to
          be brought online in a powered down core then when VPE 0 of that
          core runs it may not have a valid stack, and even if it did then
          it's messy to run through parts of generic kernel code on VPE 0
          before starting the correct VPE.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      245a7868
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      MIPS: uasm: add MT ASE yield instruction · d674dd14
      Paul Burton 提交于
      This patch allows use of the MT ASE yield instruction from uasm. It will
      be used by a subsequent patch.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      d674dd14
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      MIPS: uasm: add wait instruction · 53ed1389
      Paul Burton 提交于
      This patch allows use of the wait instruction from uasm. It will be used
      by a subsequent patch.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      53ed1389
    • P
      MIPS: uasm: add sync instruction · 729ff561
      Paul Burton 提交于
      This patch allows use of the sync instruction from uasm. It will be used
      by a subsequent patch.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      729ff561
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      MIPS: uasm: add jalr instruction · 49e9529b
      Paul Burton 提交于
      This patch allows use of the jalr instruction from uasm. It will be used
      by a subsequent patch.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      49e9529b
    • P
      MIPS: uasm: add a label variant of beq · 8dee5901
      Paul Burton 提交于
      This patch allows for use of the beq instruction with labels from uasm,
      much as bne & others already do. It will be used by a subsequent patch.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      8dee5901
    • P
      MIPS: inst.h: define microMIPS wait op · f263839a
      Paul Burton 提交于
      The opcode for the wait instruction within POOL32AXf was missing. This
      patch adds it for use by a subsequent patch.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      f263839a
    • P
      MIPS: inst.h: define microMIPS sync op · 7ed82ad1
      Paul Burton 提交于
      The opcode for the sync instruction within POOL32AXf was missing. This
      patch adds it for use by a subsequent patch.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      7ed82ad1
    • P
      MIPS: inst.h: define MT yield op · 6f5bb424
      Paul Burton 提交于
      The opcode for the MT ASE yield instruction within the spec3 group was
      missing. This patch adds it for use by a subsequent patch.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      6f5bb424
    • P
      MIPS: inst.h: define COP0 wait op · b0a3eae2
      Paul Burton 提交于
      The func field for the wait instruction was missing from inst.h - this
      patch adds it.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      b0a3eae2
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      MIPS: MT: define write_c0_tchalt macro · 27476f3b
      Paul Burton 提交于
      Define a macro to write to the current TCs TCHalt register. This will be
      used by a subsequent patch.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      27476f3b
    • P
      MIPS: add kmap_noncoherent to wire a cached non-coherent TLB entry · e2a9e5ad
      Paul Burton 提交于
      This is identical to kmap_coherent apart from the cache coherency
      attribute used for the TLB entry, so kmap_coherent is abstracted to
      kmap_prot which is then called for both kmap_coherent &
      kmap_noncoherent. This will be used by a subsequent patch.
      Suggested-by: NLeonid Yegoshin <leonid.yegoshin@imgtec.com>
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      e2a9e5ad
  2. 02 5月, 2014 13 次提交
  3. 24 4月, 2014 1 次提交
  4. 21 4月, 2014 4 次提交
  5. 20 4月, 2014 6 次提交