Switched Tegra210 PLLRE registration to common PLL ops instead of special
PLLRE ops used on previous Tegra chips. The latter ops do not follow
chip specific PLL frequency table, and do not apply chip specific rate
calculation method.

Removed unnecessary default rate setting that duplicates h/w reset
state, and is overwritten by clock initialization, anyway.
Signed-off-by: NAlex Frid <afrid@nvidia.com>
Reviewed-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: NJon Mayo <jmayo@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Remove from Tegra210 PLLSS registration code sections that
- attempt to set PLL minimum rate (unnecessary, and dangerous if PLL
  is already enabled on boot)
- apply pre-Tegra210 defaults settings
- check IDDQ setting (duplicated with Tegra210 PLLSS check defaults)

Replaced setting of reference clock with check that default oscillator
selection is not changed, and failed registration otherwise as validation
was only done with the oscillator as the reference clock.

Reordered registration, so that PLL initialization is called after
VCOmin adjustment.
Signed-off-by: NAlex Frid <afrid@nvidia.com>
Reviewed-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Tegra210 PLLX uses the same sequences than then PLLC instances. So there
is no need to have a special registration function and ops struct for it.
Simplify the code by changing all references to the Tegra210 PLLX
registration function to the Tegra210 PLLC registration function and
avoid duplicate functionality.

Based on work by Alex Frid <afrid@nvidia.com>
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

If the PLL is on, only warn if the defaults are not yet set. Otherwise be
silent.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: NTimo Alho <talho@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Increase delay after PLL IDDQ release to 5us per PLL specifications.

based on work by Alex Frid <afrid@nvidia.com>
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

I2C controllers are also on the APB bus and therefor need this flag to handle
resets correctly.
Signed-off-by: NAlex Frid <afrid@nvidia.com>
Reviewed-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Don't take the fractional part into account to calculate the effective
NDIV if fractional ndiv is not enabled.
Signed-off-by: NAlex Frid <afrid@nvidia.com>
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Not all fields are read from the hw depending on the PLL type. Make sure
the other fields are 0 by clearing the structure beforehand to prevent
users such as the rate re-calculation code from using bogus values.

Based on work by  Alex Frid <afrid@nvidia.com>
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

PLLD2 is used for HDMI which does not allow Spread Spectrum clocking.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Make sure the pll_ss ops are compiled even when only building for Tegra210.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: NShreshtha Sahu <ssahu@nvidia.com>
Tested-by: NShreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: NJon Mayo <jmayo@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

PLL SS was only controlled when setting the PLL rate, not when the PLL itself
is enabled or disabled.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: NJon Mayo <jmayo@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The clock bimc_gpu_clk_src is incorrectly set to use the shared rcg2
ops, which are for RCGs with child branches controlled by different
CPUs.

The result of the incorrect ops is that the GPU's PM runtime may leave
this clock set at a very low rate. Fix this issue by using the correct
rcg2 ops.

Fixes: a2e8272f ("clk: qcom: Add MSM8916 gpu clocks")
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Make these const as they are only stored in the const field of a
clk_init_data structure.
Signed-off-by: NBhumika Goyal <bhumirks@gmail.com>
Acked-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Merge tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull Renesas clk driver updates from Geert Uytterhoeven:

  * Add more module clocks for R-Car V2H and M3-W,
  * Add support for the R-Car Gen3 USB 2.0 clock selector PHY,
  * Add support for the new R-Car D3 SoC,
  * Allow compile-testing of all (sub)drivers now all dummy infrastructure
    is available,
  * Small fixes and cleanups.

* tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7796: Add USB3.0 clock
  clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY
  clk: renesas: cpg-mssr: Add R8A77995 support
  clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks
  clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3
  clk: renesas: Add r8a77995 CPG Core Clock Definitions
  clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div table
  clk: renesas: rcar-gen3-cpg: Drop superfluous variable
  clk: renesas: Allow compile-testing of all (sub)drivers
  clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocks
  clk: renesas: div6: Document fields used for parent selection

Silence the sparse warning

clk/rockchip/clk.c:172:6: warning: symbol 'rockchip_fractional_approximation' was not declared. Should it be static?

Cc: Elaine Zhang <zhangqing@rock-chips.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Merge tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull Rockchip clk driver updates from Heiko Stuebner:

The biggest change is fixing the jitter on the fractional clock-type
Rockchip socs experience with the default approximation. For that we
introduce the ability to override it with a clock-specific approximation
and use that to create the needed rate settings as described in the
Rockchip soc manuals (same for all Rockchip socs).

Apart from that we have support for the rk3126 clock controller
which is similar to the rk3128 with some minimal differences
and a lot of improvements and fixes for the rv1108 clock controller
(missing clocks, some clock-ids, naming fixes, register fixes).

* tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: fix the rv1108 clk_mac sel register description
  clk: rockchip: rename rv1108 macphy clock to mac
  clk: rockchip: add rv1108 ACLK_GMAC and PCLK_GMAC clocks
  clk: rockchip: add rk3228 SCLK_SDIO_SRC clk id
  clk: rockchip: add rv1108 ACLK_GAMC and PCLK_GMAC ID
  clk: rockchip: add rk3228 sclk_sdio_src ID
  clk: rockchip: add special approximation to fix up fractional clk's jitter
  clk: fractional-divider: allow overriding of approximation
  clk: rockchip: modify rk3128 clk driver to also support rk3126
  dt-bindings: add documentation for rk3126 clock
  clk: rockchip: add some critical clocks for rv1108 SoC
  clk: rockchip: rename some of clks for rv1108 SoC
  clk: rockchip: fix up some clks describe error for rv1108 SoC
  clk: rockchip: support more clks for rv1108
  clk: rockchip: fix up the pll clks error for rv1108 SoC
  clk: rockchip: support more rates for rv1108 cpuclk
  clk: rockchip: fix up indentation of some RV1108 clock-ids
  clk: rockchip: rename the clk id for HCLK_I2S1_2CH
  clk: rockchip: add more clk ids for rv1108

Merge tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next

Pull Allwinner clock changes from Chen-Yu Tsai:

 * Added support for fixed post-divider on divider and NKM-style clocks
 * Added driver for R40 CCU
 * Fix sunxi-ng/ccu-sunxi-r.h header file guard macro typo
 * Make fractional clock modes really used and correctly configured
 * Make H3 cpu clock rate change correctly to be used with cpufreq

* tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: support R40 SoC
  dt-bindings: add compatible string for Allwinner R40 CCU
  clk: sunxi-ng: nkm: add support for fixed post-divider
  clk: sunxi-ng: div: Add support for fixed post-divider
  dt-bindings: clock: sunxi-ccu: Add compatibles for sun5i CCU driver
  clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
  clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change
  clk: sunxi-ng: Wait for lock when using fractional mode
  clk: sunxi-ng: Make fractional helper less chatty
  clk: sunxi-ng: multiplier: Fix fractional mode
  clk: sunxi-ng: Fix fractional mode for N-M clocks
  clk: sunxi-ng: Fix header guard of ccu-sun8i-r.h

Merge tag 'clk-v4.14-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next

Pull Samsung clk driver updates from Sylwester Nawrocki:

Changes in definitions of audio related clocks for Exynos5420/5422/5800
SoCs: a fix of mau_epll clock definition and changes enabling clock rate
setting propagation on a path from the I2S IP block up the EPLL.

* tag 'clk-v4.14-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: exynos542x: Enable clock rate propagation up to the EPLL
  clk: samsung: Add CLK_SET_RATE_PARENT to some AUDSS CLK CON clocks
  clk: samsung: Fix mau_epll clock definition for exynos5422

Pull Amlogic clock driver updates from Neil Armstrong:

 * meson8b: add the reset controller to the clkc
 * meson: expose all clk ids
 * gxbb-aoclk: Add CEC 32k clock
 * gxbb: add mmc input 0 clocks
 * meson: fix protection against undefined clks
 * gxbb: fix audio divider flags

* tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson:
  clk: meson: gxbb-aoclk: Add CEC 32k clock
  clk: meson: gxbb-aoclk: Switch to regmap for register access
  dt-bindings: clock: amlogic, gxbb-aoclkc: Update bindings
  clk: meson: gxbb: Add sd_emmc clk0 clocks
  clk: meson: gxbb: fix clk_mclk_i958 divider flags
  clk: meson: gxbb: fix meson cts_amclk divider flags
  clk: meson: meson8b: register the built-in reset controller
  dt-bindings: clock: gxbb-aoclk: Add CEC 32k clock
  clk: meson: gxbb: Add sd_emmc clk0 clkids
  clk: meson-gxbb: expose almost every clock in the bindings
  clk: meson8b: expose every clock in the bindings
  clk: meson: gxbb: fix protection against undefined clks
  clk: meson: meson8b: fix protection against undefined clks
  dt-bindings: clock: meson8b: describe the embedded reset controller

The source clock ordering is wrong, as shown in the TRM:
cru_sel24_con[8]
rmii_extclk_sel
clock source select control register
1'b0: from internal PLL
1'b1: from external IO
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: NDavid Wu <david.wu@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This MAC has no internal phy for rv1108 and the whole clock
infrastructure hasn't been used yet, so is safe to fix.
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: NDavid Wu <david.wu@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add gmac aclk and pclk clock gates.
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: NDavid Wu <david.wu@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

In some special circumstances, may be need to reparent clk for sclk_sdio_src.
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch exports gmac aclk and pclk for dts reference.
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: NDavid Wu <david.wu@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch exports sdio src clock for dts reference.
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.

Add support for it.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.io>
Signed-off-by: NChen-Yu Tsai <wens@csie.org>

Allwinner R40 has a clock controlling unit like the ones on other
Allwinner SoCs after sun6i, and can also use a CCU-based driver.

Add a compatible string for it.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.io>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NChen-Yu Tsai <wens@csie.org>

This patch adds USB3.0-IF0 clock for R8A7796 SoC.
Signed-off-by: NHiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

R-Car USB 2.0 controller can change the clock source from an oscillator
to an external clock via a register. So, this patch adds support
the clock source selector as a clock driver.
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add R-Car D3 (R8A77995) Clock Pulse Generator / Module Standby and
Software Reset support, using the CPG/MSSR driver core and the common
R-Car Gen3 CPG code.

Based on the R-Car Series, 3rd Generation Hardware User's Manual, Rev.
0.55, Jun. 30, 2017.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NRob Herring <robh@kernel.org>

On R-Car Gen3 SoCs with a Spread Spectrum Clock Generator (e.g. R-Car
D3), a peripheral clock divider has been added, to select between clean
and spread spectrum parents.

Add a new clock type to the R-Car Gen3 driver core to handle this.
To avoid increasing the size of struct cpg_core_clk, both parents and
dividers are stored in the existing parent resp. div fields.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>

On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider
value different from one.  Extend struct rcar_gen3_cpg_pll_config to handle
this.  As all multipliers and dividers are small, table size increase
can be kept limited by storing them in u8s instead of unsigned ints,
which saves ca. 0.5 KiB for a generic kernel.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>

Add all R-Car D3 Clock Pulse Generator Core Clock Outputs, as listed
in Table 8.2f ("List of Clocks [R-Car D3]") of the R-Car Series, 3rd
Generation Hardware User's Manual (Rev. 0.55, Jun. 30, 2017).

Note that internal CPG clocks (S0, S1, S2, S3, S1C, S3C, SDSRC, and
SSPSRC) are not included, as they are used as internal clock sources
only, and never referenced from DT.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>

SATA PLL on Allwinner R40 is of type (parent) * N * K / M / 6 where 6 is
the fixed post-divider.

Add post-divider support for NKM type clock.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.io>
[wens@csie.org: Fixed application of post-divider in set_rate callback]
Signed-off-by: NChen-Yu Tsai <wens@csie.org>

SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
6 is fixed post-divider.
Signed-off-by: NPriit Laes <plaes@plaes.org>
Signed-off-by: NIcenowy Zheng <icenowy@aosc.io>
Signed-off-by: NChen-Yu Tsai <wens@csie.org>

The bindings were not updated when the sun5i CCU driver was added in
commit 5e737617 ("clk: sunxi-ng: Add sun5i CCU driver").
Signed-off-by: NJonathan Liu <net147@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NChen-Yu Tsai <wens@csie.org>

The CLK_SET_RATE_PARENT flag is added to clocks between the EPLL
and the audio subsystem clock controller so that the EPLL's output
frequency can be set indirectly with clk_set_rate() on a leaf clock.
That should be safe as EPLL is normally only used to generate clock
for the audio subsystem.
With this change we can avoid passing the EPLL clock to the ASoC
machine driver.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This allows clk rate propagation up to the clock tree so EPLL
can be reprogrammed indirectly when setting rate of the Audio
Subsystem clocks.
The advantage is that sound machine driver can operate only
on the leaf clocks rather than explicitly re-configuring
the root clock (EPLL).
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>