The compatible string "simple-bus" is well defined in ePAPR, while
I see no documentation for the "arm,amba-bus" arnywhere in ePAPR or
Documentation/devicetree/.

DT is also used by other projects than Linux kernel.  It is not a
good idea to rely on such an unofficial binding.

This commit
  - replaces "arm,amba-bus" with "simple-bus"
  - drops "arm,amba-bus" where it is used along with "simple-bus"
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

These clocks are fixed rate board sources that should be in DT.
Add them.

Cc: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add a label to the serial nodes that are being used for the
console.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Replace the standalone gpio driver with pinctrl-msm as we now have
msm8660 support there.
Signed-off-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NAndy Gross <agross@codeaurora.org>

Enable perf events on msm8660 devices by adding the pmu node.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>

This patch adds TCSR support for use by the GSBI to automatically
configure ADM CRCI values based on the GSBI port configuration.
Signed-off-by: NAndy Gross <agross@codeaurora.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Add the sdcc nodes to support the SD card controller using pl180
mmci driver. We also add a temporary fixed regulator until the
regulator driver is mainlined.

Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>

Add the PMIC and the sub-devices that are currently supported in
the kernel to the DT.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>

* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8660-surf.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
  should be per cpu, not part of the container
* Add GSBI node and configuration of GSBI controller
Signed-off-by: NKumar Gala <galak@codeaurora.org>

Add the necessary nodes to support SMP on MSM8660, MSM8960, and
MSM8974/APQ8074. While we're here also add in the error
interrupts for the Krait cache error detection.
Signed-off-by: NRohit Vaswani <rvaswani@codeaurora.org>
[sboyd: Split into separate patch, add error interrupts]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>

Pull the SoC device tree bits into their own files so other boards based
on these SoCs can include them and reduce duplication across a number of
boards.
Signed-off-by: NKumar Gala <galak@codeaurora.org>

Add the necessary DT nodes to probe the clock controllers on MSM
devices as well as hook up the uart nodes to the clock
controllers. This should allow us to boot to a serial console on
all DT enabled MSM platforms.

Cc: David Brown <davidb@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The summary interrupt is #16 in the SPI space. Unfortunately,
when this device was translated from board files to DT we forgot
to subtract 16 from the interrupt number to translate it into a
SPI interrupt. Also, the register space is larger than 4k, increase
it appropriately so that the gpio driver doesn't try to access
registers outside of its mapping.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

Use a standard 'qcom' prefix to denotate device trees meant for Qualcomm
based processors.
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Let's follow the ratified DT binding and use uartdm instead of
hsuart. This does break backwards compatibility but this
shouldn't be a problem because the uart driver isn't probing on
these devices without adding clock support (which isn't merged so
far).

Cc: David Brown <davidb@codeaurora.org>
Acked-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

This cleans up the gpio-msm-v2 driver of all the global define usage.
The number of gpios are now defined in the device tree. This enables
adding irqdomain support as well.
Signed-off-by: NRohit Vaswani <rvaswani@codeaurora.org>
Acked-by: NGrant Likely <grant.likely@linaro.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Some bad copy/paste got in as well as too many zeroes. Fix
everything up so that the registers after the @ sign are
consistent with the first reg property.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

The SSBI bus is exclusive to the Qualcomm MSM targets, and all SoCs
using it will be using device tree.  Convert this driver to indentify
with device tree.

This makes the bus probing a good bit simpler, since the attaching of
child nodes can be represented directly in the devicetree, rather than
having to be inferred by name.
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The msm timer binding I wrote is bad. First off, the clock
frequency in the binding for the dgt is wrong. Software divides
down the input rate by 4 to achieve the rate listed in the
binding. We also treat each individual timer as a separate
hardware component, when in reality there is one timer block
(that may be duplicated per cpu) with multiple timers within it.
Depending on the version of the hardware there can be one or two
general purpose timers, status and divider control registers, and
an entirely different register layout.

In the next patch we'll need to know about the different register
layouts so that we can properly check the status register after
clearing the count. The current binding makes this complicated
because the general purpose timer's reg property doesn't indicate
where that status register is, and in fact it is beyond the size
of the reg property.

Clean all this up by just having one node for the timer hardware,
and describe all the interrupts and clock frequencies supported
while having one reg property that covers the entire timer
register region. We'll use the compatible field in the future to
determine different register layouts and if we should read the
status registers, etc.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Add the timer entry and point the machine descriptor to the
device tree based msm timer.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
[davidb@codeaurora.org: Remove leading zeros]
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

As of

    commit 75294957
    Author: Grant Likely <grant.likely@secretlab.ca>
    Date:   Tue Feb 14 14:06:57 2012 -0700

        irq_domain: Remove 'new' irq_domain in favour of the ppc one

the ARM gic controller uses proper irq domains.  Fix the MSM gic
initialization and DT so that it works again.
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>

Adds support for booting via device tree with a simple serial console.

Change-Id: I7f175b8db21928cd13e0fb49f3eed74966a2696f
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>