- 26 2月, 2016 4 次提交
-
-
由 Stephen Boyd 提交于
This config was used for the ARM port so that it could use a machine specific clkdev.h include, but those are all gone now. The MIPS architecture is the last user, and from what I can tell it doesn't actually use it anyway, so let's remove the config all together. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: <linux-mips@linux-mips.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Reviewed-by: NJoshua Henderson <joshua.henderson@microchip.com>
-
由 Stephen Boyd 提交于
* clk-ipq4019: clk: qcom: Add IPQ4019 Global Clock Controller support
-
由 Varadarajan Narayanan 提交于
This patch adds support for the global clock controller found on the IPQ4019 based devices. This includes UART, I2C, SPI etc. Signed-off-by: NPradeep Banavathi <pradeepb@codeaurora.org> Signed-off-by: NSenthilkumar N L <snlakshm@codeaurora.org> Signed-off-by: NVaradarajan Narayanan <varada@codeaurora.org> Signed-off-by: NMatthew McClintock <mmcclint@codeaurora.org> Acked-by: NAndy Gross <andy.gross@linaro.org> [sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Stephen Boyd 提交于
We forgot to free this clock when we return early in this code. Cc: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 25 2月, 2016 1 次提交
-
-
由 Sudip Mukherjee 提交于
We were not checking the return from devm_add_action() which can fail. Start using the helper devm_add_action_or_reset() and return directly as we know that the cleanup has been done by this helper. Signed-off-by: NSudip Mukherjee <sudip.mukherjee@codethink.co.uk> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 23 2月, 2016 9 次提交
-
-
由 Stephen Boyd 提交于
__clk_init() was renamed to __clk_core_init() but these comments weren't updated. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Stephen Boyd 提交于
This reverts commit 858d5881. Joachim reports that this commit breaks lpc18xx boot. This is because the hardware has circular clk topology where PLLs can feed into dividers and the same dividers can feed into the PLLs. The hardware is designed this way so that you can choose to put the divider before the PLL or after the PLL depending on what you configure to be the parent of the divider and what you configure to be the parent of the PLL. So let's drop this patch for now because we have hardware that actually has loops. A future patch could check for circular parents when we change parents and fail the switch, but that's probably best left to some debugging Kconfig option so that we don't suffer the sanity checking cost all the time. Reported-by: NJoachim Eastwood <manabian@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Dinh Nguyen 提交于
There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can have multiple parents. Fix up the __socfpga_periph_init() to call of_clk_parent_fill() that will return the appropriate number of parents. Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper function. Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Tero Kristo 提交于
Convert DPLL support code to use clk_hw pointers for reference and bypass clocks. This allows us to use clk_hw_* APIs for accessing any required parameters for these clocks, avoiding some locking problems at least with DPLL enable code; this used clk_get_rate which uses mutex but isn't good under clk_enable / clk_disable. Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Stephen Boyd 提交于
* clk-fixes: clk: ti: omap3+: dpll: use non-locking version of clk_get_rate
-
由 Srinivas Kandagatla 提交于
This patch corrects the enable register offset which is actually 0x36cc instead of 0x36c4 Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: 5f775498 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Tero Kristo 提交于
As the code in this file is being executed within irq context in some cases, we must avoid the clk_get_rate which uses mutex internally. Switch the code to use clk_hw_get_rate instead which is non-locking. This fixes an issue where PM runtime will hang the system if enabled with a serial console before a suspend-resume cycle. Signed-off-by: NTero Kristo <t-kristo@ti.com> Tested-by: NTony Lindgren <tony@atomide.com> Fixes: a53ad8ef ("clk: ti: Convert to clk_hw based provider APIs") Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Michael Turquette 提交于
-
由 Krzysztof Kozlowski 提交于
Currently the Exynos5433 (ARMv8 SoC) clock driver depends on ARCH_EXYNOS so it is built also on ARMv7. This does not bring any kind of benefit. There won't be a single kernel image for ARMv7 and ARMv8 SoCs (like multi_v7 for ARMv7). Instead build clock drivers only for respective SoC's architecture. Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
- 20 2月, 2016 1 次提交
-
-
由 Michael Turquette 提交于
Merge branch 'clk-shmobile-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
-
- 19 2月, 2016 2 次提交
-
-
由 Stephen Boyd 提交于
* clk-fixes: clk: gpio: Really allow an optional clock= DT property Revert "clk: qcom: Specify LE device endianness"
-
由 Stephen Boyd 提交于
We mis-merged the original patch from Russell here and so the patch went almost all the way, except that we still failed to probe when there wasn't a clocks property in the DT node. Allow that case by making a negative value from of_clk_get_parent_count() into "no parents", like the original patch did. Fixes: 7ed88aa2 ("clk: fix clk-gpio.c with optional clock= DT property") Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 18 2月, 2016 2 次提交
-
-
由 Magnus Damm 提交于
Add the "intc-ex" clock to the r8a7795 CPG MSSR driver. According to information from the hardware team the INTC-EX parent clock is CP. The next data sheet version will include this information. Signed-off-by: NMagnus Damm <damm+renesas@opensource.se> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Andrew F. Davis 提交于
Export symbol of_clk_get_from_provider so it can be used in loadable kernel modules Signed-off-by: NAndrew F. Davis <afd@ti.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
- 17 2月, 2016 4 次提交
-
-
由 Krzysztof Kozlowski 提交于
Enable the COMPILE_TEST to get build coverage of some of Samsung clock controller drivers. Still some of them will be built only if appropriate SoC is chosen (like SOC_EXYNOS4415 or ARCH_S3C64XX). Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com> Tested-by: NJavier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: NAndi Shyti <andi.shyti@samsung.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
由 Michael Turquette 提交于
-
由 Eric Anholt 提交于
We were rolling this ourselves, but clk-divider can do it now. Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
由 Eric Anholt 提交于
Our dividers weren't being set successfully because CM_PASSWORD wasn't included in the register write. It looks easier to just compute the divider to write ourselves than to update clk-divider for the ability to OR in some arbitrary bits on write. Fixes about half of the video modes on my HDMI monitor (everything except 720x400). Cc: stable@vger.kernel.org Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
- 16 2月, 2016 2 次提交
-
-
由 Geert Uytterhoeven 提交于
Cfr. commit a9ec81f4 ("serial: sh-sci: Drop the interface clock"). Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NMichael Turquette <mturquette@baylibre.com>
-
由 Michael Turquette 提交于
Merge tag 'v4.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Introduction of a factor type and a variant containing a gate to be able to also declare factor clocks in their correct place in the clock tree instead of having to register factor clocks in the init callback separately. And as always some more clock-ids and non-regression fixes for mistakes introduced in past kernel releases.
-
- 13 2月, 2016 1 次提交
-
-
由 Stephen Boyd 提交于
This reverts commit 329cabce. The commit that caused us to specify LE device endianness here, 29bb45f2 (regmap-mmio: Use native endianness for read/write, 2015-10-29), has been reverted in mainline so now when we specify LE it actively breaks big endian kernels because the byte swapping in regmap-mmio is incorrect. Let's revert this change because it will 1) fix the big endian kernels and 2) be redundant to specify LE because that will become the default soon. Cc: Kevin Hilman <khilman@linaro.org> Tested-by: NKevin Hilman <khilman@baylibre.com> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 12 2月, 2016 6 次提交
-
-
由 Rajendra Nayak 提交于
With gdsc driver capable of handling hierarchical power domains, specify oxili_gdsc as parent of oxilicx_gdsc. Remove all direct calls to genpd from the mmcc clock driver. The adding and removing of subdomains is now handled from within the gdsc driver. Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Rajendra Nayak 提交于
Add all gdsc data which are part of mmcc on msm8996 family Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Rajendra Nayak 提交于
Add all data for the GDSCs which are part of msm8996 GCC block Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Rajendra Nayak 提交于
Some gdscs might be controlled via voting registers and might not really disable when the kernel intends to disable them (due to other votes keeping them enabled) Mark these gdscs with a flag for we do not check/wait on a disable status for these gdscs within the kernel disable callback. Also at boot, if these GDSCs are found to be ON, we make sure we vote for them before we inform the genpd framework about their status. If genpd gets no users, it then disables (removes the vote) them as part of genpd_poweroff_unused() Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Rajendra Nayak 提交于
Some gdsc power domains can have a gds_hw_controller block inside to help ensure all slave devices within the power domain are idle before the gdsc is actually switched off. This is mainly useful in power domains which host a MMU, in which case its necessary to make sure there are no outstanding MMU operations or pending bus transactions before the power domain is turned off. In gdscs with gds_hw_controller block, its necessary to check the gds_hw_ctrl status bits instead of the ones in gdscr, to determine the state of the powerdomain. While at it, also move away from using jiffies and use ktime APIs instead for busy looping on status bits. Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Rajendra Nayak 提交于
Some qcom SoCs' can have hierarchical power domains. Let the gdsc structs specify the parents (if any) and the driver add genpd subdomains for them. Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 11 2月, 2016 3 次提交
-
-
由 Sylvain Lemieux 提交于
This patch add the support to setup the HCLK PLL output using the "assigned-clock-rates" parameter in the device tree. If the option is not use, the clock setup by the kickstart and/or bootloader remain unchanged. The previous kernel version did not change the clock frequency output setup by the kickstart and/or bootloader; this version always setup the clock frequency output to 208MHz. Signed-off-by: NSylvain Lemieux <slemieux@tycoint.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Stephen Boyd 提交于
* clk-fixes: clk: versatile: mask VCO bits before writing
-
由 Linus Walleij 提交于
The Versatile syscon ICST driver OR:s the bits into place but forgets to mask the previous value, making the code only work if the register is zero or giving haphazard results. Mask the 19 bits used by the Versatile syscon interface register. Regression caused and now fixed by yours truly. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Fixes: 179c8fb3 ("clk: versatile-icst: convert to use regmap") Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 10 2月, 2016 2 次提交
-
-
由 Sylvain Lemieux 提交于
The following errors are display in the console during the power-on: [ 0.000000] lpc32xx_usb_clk_init: failed to register (null) clock: -12 [ 0.000000] lpc32xx_clk_init: failed to register (null) clock: -12 There is no need to register clock "0"; the first clock used is 1; Signed-off-by: NSylvain Lemieux <slemieux@tycoint.com> Acked-by: NVladimir Zapolskiy <vz@mleia.com> [sboyd@codeaurora.org: s/prepare/register/] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Masahiro Yamada 提交于
Before commit b3d192d5121f ("clk: simplify __clk_init_parent()"), __clk_init_parent() called .get_parent() only for multi-parent clocks. That commit changed the behavior to call .get_parent() if available even for single-parent clocks and root clocks. It turned out a problem because there are some single-parent clocks that implement .get_parent() callback and return non-zero index. The SOCFPGA clock is the case; the commit broke the SOCFPGA boards. To keep the original behavior, invoke .get_parent() only when num_parents is greater than 1. Fixes: b3d192d5121f ("clk: simplify __clk_init_parent()") Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reported-by: NDinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 09 2月, 2016 3 次提交
-
-
由 Sudip Mukherjee 提交于
We were not checking the return from devm_add_action() which can fail. Start using the helper and devm_add_action_or_reset() and return directly as we know that the cleanup has been done by this helper. Signed-off-by: NSudip Mukherjee <sudip@vectorindia.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Sudip Mukherjee 提交于
Add a helper function devm_add_action_or_reset() which will internally call devm_add_action(). But if devm_add_action() fails then it will execute the action mentioned and return the error code. Signed-off-by: NSudip Mukherjee <sudip@vectorindia.org> Acked-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Andreas Färber 提交于
As preparation for arm64 based mesongxbb, which pulls in this code once enabling ARCH_MESON, fix a size_t vs. unsigned int type mismatch. The loop uses a local unsigned int variable, so adopt that type, matching the header. Fixes: 7a29a869 ("clk: meson: Add support for Meson clock controller") Signed-off-by: NAndreas Färber <afaerber@suse.de> Acked-by: NCarlo Caione <carlo@endlessm.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-