1. 02 9月, 2020 1 次提交
  2. 20 3月, 2018 2 次提交
  3. 27 1月, 2018 1 次提交
  4. 19 1月, 2018 1 次提交
  5. 29 6月, 2017 1 次提交
  6. 27 5月, 2017 1 次提交
  7. 19 4月, 2017 1 次提交
    • B
      PCI: Include PCI-to-PCIe bridges as "Downstream Ports" · 9b70ae49
      Bjorn Helgaas 提交于
      A PCI/PCI-X to PCI Express bridge, sometimes referred to as a "reverse
      bridge", is a bridge with conventional PCI or PCI-X on its primary side and
      a PCI Express Port on its secondary (downstream) side.
      
      That PCIe Port is a Downstream Port and could be connected to a slot, just
      like a Root Port or a Switch Downstream Port.  Make pcie_downstream_port()
      return true for them, so we can access the Slot registers in the PCIe
      capability.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      9b70ae49
  8. 05 4月, 2017 1 次提交
  9. 30 3月, 2017 2 次提交
  10. 02 3月, 2017 1 次提交
  11. 04 2月, 2017 1 次提交
  12. 31 1月, 2017 1 次提交
    • B
      PCI: Avoid possible deadlock on pci_lock and p->pi_lock · cdcb33f9
      Bjorn Helgaas 提交于
      pci_lock is an IRQ-safe spinlock that protects all accesses to PCI
      configuration space (see PCI_OP_READ() and PCI_OP_WRITE() in pci/access.c).
      
      The pci_cfg_access_unlock() path acquires pci_lock, then p->pi_lock (inside
      wake_up_all()).  According to lockdep, there is a possible path involving
      snbep_uncore_pci_read_counter() that could acquire them in the reverse
      order: acquiring p->pi_lock, then pci_lock, which could result in a
      deadlock.  Lockdep details are in the bugzilla below.
      
      Avoid the possible deadlock by dropping pci_lock before waking up any
      config access waiters.
      
      Link: https://bugzilla.kernel.org/show_bug.cgi?id=192901Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      cdcb33f9
  13. 22 11月, 2016 1 次提交
  14. 16 4月, 2016 1 次提交
  15. 11 3月, 2016 1 次提交
    • B
      PCI: Sleep rather than busy-wait for VPD access completion · c521b014
      Bjorn Helgaas 提交于
      Use usleep_range() instead of udelay() while waiting for a VPD access to
      complete.  This is not a performance path, so no need to hog the CPU.
      
      Rationale for usleep_range() parameters:
      
        We clear PCI_VPD_ADDR_F for a read (or set it for a write), then wait for
        the device to change it.  For a device that updates PCI_VPD_ADDR between
        our config write and subsequent config read, we won't sleep at all and
        can get the device's maximum rate.
      
        Sleeping a minimum of 10 usec per 4-byte access limits throughput to
        about 400Kbytes/second.  VPD is small (32K bytes at most), and most
        devices use only a fraction of that.
      
        We back off exponentially up to 1024 usec per iteration.  If we reach
        1024, we've already waited up to 1008 usec (16 + 32 + ... + 512), so if
        we miss an update and wait an extra 1024 usec, we can still get about
        1/2 of the device's maximum rate.
      Tested-by: NShane Seymour <shane.seymour@hpe.com>
      Tested-by: NBabu Moger <babu.moger@oracle.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: NHannes Reinecke <hare@suse.com>
      c521b014
  16. 01 3月, 2016 7 次提交
  17. 09 1月, 2016 1 次提交
  18. 25 9月, 2015 2 次提交
  19. 22 7月, 2015 1 次提交
    • M
      PCI: Add dev_flags bit to access VPD through function 0 · 932c435c
      Mark Rustad 提交于
      Add a dev_flags bit, PCI_DEV_FLAGS_VPD_REF_F0, to access VPD through
      function 0 to provide VPD access on other functions.  This is for hardware
      devices that provide copies of the same VPD capability registers in
      multiple functions.  Because the kernel expects that each function has its
      own registers, both the locking and the state tracking are affected by VPD
      accesses to different functions.
      
      On such devices for example, if a VPD write is performed on function 0,
      *any* later attempt to read VPD from any other function of that device will
      hang.  This has to do with how the kernel tracks the expected value of the
      F bit per function.
      
      Concurrent accesses to different functions of the same device can not only
      hang but also corrupt both read and write VPD data.
      
      When hangs occur, typically the error message:
      
        vpd r/w failed.  This is likely a firmware bug on this device.
      
      will be seen.
      
      Never set this bit on function 0 or there will be an infinite recursion.
      Signed-off-by: NMark Rustad <mark.d.rustad@intel.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Acked-by: NAlexander Duyck <alexander.h.duyck@redhat.com>
      CC: stable@vger.kernel.org
      932c435c
  20. 15 7月, 2015 1 次提交
    • B
      PCI: Add pcie_downstream_port() (true for Root and Switch Downstream Ports) · ffb4d602
      Bjorn Helgaas 提交于
      As used in the PCIe spec, "Downstream Port" includes both Root Ports and
      Switch Downstream Ports.  We sometimes checked for PCI_EXP_TYPE_DOWNSTREAM
      when we should have checked for PCI_EXP_TYPE_ROOT_PORT or
      PCI_EXP_TYPE_DOWNSTREAM.
      
      For a Root Port without a slot, the effect of this was that using
      pcie_capability_read_word() to read PCI_EXP_SLTSTA returned zero instead of
      showing the Presence Detect State bit hardwired to one as the PCIe Spec,
      r3.0, sec 7.8, requires.  (This read is completed in software because
      previous PCIe spec versions didn't require PCI_EXP_SLTSTA to exist at all.)
      
      Nothing in the kernel currently depends on this (pciehp only reads
      PCI_EXP_SLTSTA on ports with slots), so this is a cleanup and not a
      functional change.
      
      Add a pcie_downstream_port() helper function and use it.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Acked-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      ffb4d602
  21. 23 1月, 2015 1 次提交
    • R
      PCI: Add generic config accessors · 1f94a94f
      Rob Herring 提交于
      Many PCI controllers' configuration space accesses are memory-mapped and
      vary only in address calculation and access checks.  There are 2 main
      access methods: a decoded address space such as ECAM or a single address
      and data register similar to x86.  This implementation can support both
      cases as well as be used in cases that need additional pre- or post-access
      handling.
      
      Add a new pci_ops member, map_bus, which can do access checks and any
      necessary setup.  It returns the address to use for the configuration space
      access.  The access types supported are 32-bit only accesses or correct
      byte, word, or dword sized accesses.
      Tested-by: NThierry Reding <treding@nvidia.com>
      Signed-off-by: NRob Herring <robh@kernel.org>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: NThierry Reding <treding@nvidia.com>
      1f94a94f
  22. 14 11月, 2014 1 次提交
  23. 11 6月, 2014 1 次提交
  24. 28 5月, 2014 1 次提交
  25. 14 1月, 2014 1 次提交
  26. 29 8月, 2013 4 次提交
  27. 16 2月, 2013 1 次提交
  28. 31 1月, 2013 1 次提交