1. 07 4月, 2017 2 次提交
  2. 02 4月, 2017 1 次提交
  3. 22 2月, 2017 1 次提交
  4. 08 2月, 2017 1 次提交
  5. 20 1月, 2017 1 次提交
  6. 23 11月, 2016 1 次提交
  7. 12 11月, 2016 1 次提交
  8. 18 10月, 2016 1 次提交
  9. 27 9月, 2016 4 次提交
  10. 19 8月, 2016 1 次提交
  11. 17 5月, 2016 4 次提交
  12. 20 4月, 2016 2 次提交
  13. 09 3月, 2016 3 次提交
  14. 18 2月, 2016 1 次提交
  15. 10 2月, 2016 1 次提交
  16. 07 1月, 2016 1 次提交
  17. 24 12月, 2015 1 次提交
  18. 13 11月, 2015 1 次提交
  19. 04 11月, 2015 1 次提交
    • C
      dt-bindings: rockchip-thermal: Add the pinctrl states in this document · 9aba783a
      Caesar Wang 提交于
      The "init" pinctrl is defined we'll set
      pinctrl to this state before probe and then "default" after probe.
      Add the "init" and "sleep" pinctrl as the OTP gpio state, since we need
      switch the pin to gpio state before the TSADC controller is reset.
      
      AFAIK, the TSADC controller is reset, the tshut polarity will be
      a *low* signal in a short period of time for some devices.
      
      Says:
      The TSADC get the temperature on rockchip thermal.
      
      If T(current temperature) < (setting temperature), the OTP output the
      *high* signal.
      If T(current temperature) > (setting temperature), the OTP output the
      *low* Signal.
      
      In some cases, the OTP pin is connected to the PMIC, maybe the
      PMIC can accept the reset response time to avoid this issue.
      
      In other words, the system will be always reboot if we make the
      OTP pin is connected the others IC to control the power.
      Acked-by: NRob Herring <robh@kernel.org>
      Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
      Reviewed-by: NDouglas Anderson <dianders@chromium.org>
      Signed-off-by: NEduardo Valentin <edubezval@gmail.com>
      9aba783a
  20. 30 9月, 2015 2 次提交
  21. 18 9月, 2015 2 次提交
    • P
      of: thermal: Mark cooling-*-level properties optional · 9fa04fbe
      Punit Agrawal 提交于
      The cooling-{min,max}-level properties are marked as optional in
      Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt and the usage
      in various device tree matches this, i.e., some cooling device in the
      device trees provide these properties while others do not.
      
      Make the bindings in
      Documentation/devicetree/bindings/thermal/thermal.txt consistent with
      the cpufreq-dt bindings by marking the cooling-*-level properties as
      optional.
      Signed-off-by: NPunit Agrawal <punit.agrawal@arm.com>
      Cc: Eduardo Valentin <edubezval@gmail.com>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
      Cc: Kumar Gala <galak@codeaurora.org>
      Signed-off-by: NRob Herring <robh@kernel.org>
      9fa04fbe
    • P
      of: thermal: Fix inconsitency between cooling-*-state and cooling-*-level · eb168b70
      Punit Agrawal 提交于
      The device trees in the kernel as well as the binding description in
      Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt use the
      cooling-{min,max}-level property.
      
      Fix the inconsistency with the binding description in
      Documentation/devicetree/bindings/thermal/thermal.txt by changing
      cooling-*-state properties to cooling-*-level.
      Signed-off-by: NPunit Agrawal <punit.agrawal@arm.com>
      Cc: Eduardo Valentin <edubezval@gmail.com>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
      Cc: Kumar Gala <galak@codeaurora.org>
      Signed-off-by: NRob Herring <robh@kernel.org>
      eb168b70
  22. 04 6月, 2015 1 次提交
  23. 05 5月, 2015 2 次提交
  24. 08 4月, 2015 1 次提交
  25. 04 2月, 2015 1 次提交
    • P
      Documentation: DT bindings: add more Tegra chip compatible strings · 193c9d23
      Paul Walmsley 提交于
      Align compatible strings for several IP blocks present on Tegra chips
      with the latest doctrine from the DT maintainers:
      
      http://marc.info/?l=devicetree&m=142255654213019&w=2
      
      The primary objective here is to avoid checkpatch warnings, per:
      
      http://marc.info/?l=linux-tegra&m=142201349727836&w=2
      
      DT binding text files have been updated for the following IP blocks:
      
      - PCIe
      - SOR
      - SoC timers
      - AHB "gizmo"
      - APB_MISC
      - pinmux control
      - UART
      - PWM
      - I2C
      - SPI
      - RTC
      - PMC
      - eFuse
      - AHCI
      - HDA
      - XUSB_PADCTRL
      - SDHCI
      - SOC_THERM
      - AHUB
      - I2S
      - EHCI
      - USB PHY
      
      N.B. The nvidia,tegra20-timer compatible string is removed from the
      nvidia,tegra30-timer.txt documentation file because it's already
      mentioned in the nvidia,tegra20-timer.txt documentation file.
      
      This second version takes into account the following requests from
      Rob Herring <robherring2@gmail.com>:
      
      - Per-IP block patches have been combined into a single patch
      
      - Explicit documentation about which compatible strings are actually
        matched by the driver has been removed.  In its place is implicit
        documentation that loosely follows Rob's prescribed format:
      
        "Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where
         <chip> is tegra30, tegra132, ..." [...]  "You should attempt to
         document known values of <chip> if you use it"
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Alexandre Courbot <gnurou@gmail.com>
      Cc: Dylan Reid <dgreid@chromium.org>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Hans de Goede <hdegoede@redhat.com>
      Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
      Cc: Jingchang Lu <jingchang.lu@freescale.com>
      Cc: John Crispin <blogic@openwrt.org>
      Cc: Kumar Gala <galak@codeaurora.org>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Mikko Perttunen <mperttunen@nvidia.com>
      Cc: Murali Karicheri <m-karicheri2@ti.com>
      Cc: Paul Walmsley <pwalmsley@nvidia.com>
      Cc: Pawel Moll <pawel.moll@arm.com>
      Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
      Cc: Peter Hurley <peter@hurleysoftware.com>
      Cc: Sean Paul <seanpaul@chromium.org>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Takashi Iwai <tiwai@suse.de>
      Cc: Tejun Heo <tj@kernel.org>
      Cc: "Terje Bergström" <tbergstrom@nvidia.com>
      Cc: Thierry Reding <thierry.reding@gmail.com>
      Cc: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
      Cc: Wolfram Sang <wsa@the-dreams.de>
      Cc: Zhang Rui <rui.zhang@intel.com>
      Cc: dri-devel@lists.freedesktop.org
      Cc: linux-i2c@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-pci@vger.kernel.org
      Cc: linux-pm@vger.kernel.org
      Cc: linux-pwm@vger.kernel.org
      Cc: linux-tegra@vger.kernel.org
      Acked-by: NEduardo Valentin <edubezval@gmail.com>
      Signed-off-by: NRob Herring <robh@kernel.org>
      193c9d23
  26. 01 2月, 2015 1 次提交
  27. 29 1月, 2015 1 次提交