Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

When trying to add a gpio-hog, we enter a weird loop where the gpio-ranges
is needed when gpiochip_add_data() is called but in the current implementation
the ranges are added from the driver afterwards.

A simple solution is to rely on the DR gpio-ranges attribute and remove the
call to gpiochip_add_pin_range().
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add a Git tree on @kernel.org for maintaining the Samsung pinctrl
drivers.  The tree will be maintained in a shared model between current
Samsung pinctrl maintainers.  Pull requests will be going to Linus
Walleij.

Also add the patchwork for linux-samsung-soc mailing list which will be
used for handling the patches.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NTomasz Figa <tomasz.figa@gmail.com>
Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Fix some inverted bit numbers in some pinctrl groups and add missing pins
and groups to be in pair with the GXBB pinctrl pins definition.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

With real-time preemption, regmap functions cannot be used in the
implementation of irq_chip since they use spinlocks which may sleep.

Move the setting of the mux for IRQs to an irq_bus_sync_unlock handler
where we are allowed to sleep.
Signed-off-by: NJohn Keeping <john@metanate.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

We need to avoid calling regmap functions from irq handlers, so the next
commit is going to move the call to rockchip_set_mux() into an
irq_bus_sync_unlock handler.  But we can't return an error from there so
we still need to check the settings from rockchip_irq_set_type() and we
will use this new rockchip_verify_mux() function from there.
Signed-off-by: NJohn Keeping <john@metanate.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This lock is used from rockchip_irq_set_type() which is part of the
irq_chip implementation and thus must use raw_spinlock_t as documented
in Documentation/gpio/driver.txt.
Signed-off-by: NJohn Keeping <john@metanate.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

regmap_update_bits does its own locking and everything else accessed
here is a local variable so there is no need to lock around it.
Signed-off-by: NJohn Keeping <john@metanate.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Merge tag 'sh-pfc-for-v4.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.12

  - Fixes and cleanups.

On some Cherry Trail devices the ASL uses the GMMR GPIO to access
GPIOs so as to serialize MMIO accesses to GPIO registers with the
OS, because:

"Due to a silicon issue, a shared lock must be used to prevent concurrent
accesses across the 4 GPIO controllers.

See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
errata #CHT34, for further information."

This commit adds support for this opregion, this fixes a number of
ASL errors on my Ezpad mini3 tablet and makes the otg port device/host
muxing which is controlled in firmware on this model work properly.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Rockchip finally named the SOC as RV1108, so change it.
Signed-off-by: NAndy Yan <andy.yan@rock-chips.com>
[adapted rk1108 dtsi to keep bisectability]
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Rockchip finally named the SOC as RV1108, so change it.
Also move the compatible list to one compatible per line.
Signed-off-by: NAndy Yan <andy.yan@rock-chips.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Currently we are trying to enable/disable the clk of irq's gpio bank when
unmask/mask irq. But the kernel's "lazy disable approach" will skip masking
irq when the irq chip doesn't support irq_disable ops.

So we may hit this case:
	irq_enable-> enable clk
	irq_disable-> noop
	irq_enable-> enable clk again
	irq_disable-> noop
Signed-off-by: NJeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

At first these drivers were written as tristate, but the module
usecases are actually not tested.  Make all of them boolean.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Since commit 3e030b0b ("pinctrl: uniphier: allow to have pinctrl
node under syscon node"), this driver has kept compatibility for the
old DT files.  Several releases have passed since then, so remove
the obsoleted compatibles and clean up the code.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This adds support for the missing PWM pins on Meson GXL SoCs, namely:
- PWM_A
- PWM_B
- PWM_C
- PWM_F (GPIOX_7 and GPIOCLK_1 can be selected as output)
- PWM_AO_A (GPIOAO_3 and GPIOAO_8 can be selected as output)
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: NNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Update the sh_pfc_soc_info pointer after calling the SoC-specific
initialization function, as it may have been updated to e.g. handle
different SoC revisions.  This makes sure the correct subdriver name is
printed later.

Fixes: 0c151062 ("sh-pfc: Add support for SoC-specific initialization")
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Somehow the QSPI and SCIF_CLK fragments were inserted at the wrong
positions.  Restore sort order (alphabetically, per group).
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Fix typos in hscif2_clk_b_mux[] and hscif4_ctrl_mux[].

Fixes: a56069c4 ("pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and functions")
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

The sunxi pinctrl driver currently implement an irq_chip for handling
interrupts; due to how irq_chip handling is done, it's necessary for the
irq_chip methods to be invoked from hardirq context, even on a a
real-time kernel.  Because the spinlock_t type becomes a "sleeping"
spinlock w/ RT kernels, it is not suitable to be used with irq_chips.

A quick audit of the operations under the lock reveal that they do only
minimal, bounded work, and are therefore safe to do under a raw spinlock.
Signed-off-by: NJulia Cartwright <julia@ni.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The sirf atlas7 pinctrl drivers currently implement an irq_chip for
handling interrupts; due to how irq_chip handling is done, it's
necessary for the irq_chip methods to be invoked from hardirq context,
even on a a real-time kernel.  Because the spinlock_t type becomes a
"sleeping" spinlock w/ RT kernels, it is not suitable to be used with
irq_chips.

A quick audit of the operations under the lock reveal that they do only
minimal, bounded work, and are therefore safe to do under a raw spinlock.
Signed-off-by: NJulia Cartwright <julia@ni.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The amd pinctrl drivers currently implement an irq_chip for handling
interrupts; due to how irq_chip handling is done, it's necessary for the
irq_chip methods to be invoked from hardirq context, even on a a
real-time kernel.  Because the spinlock_t type becomes a "sleeping"
spinlock w/ RT kernels, it is not suitable to be used with irq_chips.

A quick audit of the operations under the lock reveal that they do only
minimal, bounded work, and are therefore safe to do under a raw spinlock.
Signed-off-by: NJulia Cartwright <julia@ni.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The bcm pinctrl drivers currently implement an irq_chip for handling
interrupts; due to how irq_chip handling is done, it's necessary for the
irq_chip methods to be invoked from hardirq context, even on a a
real-time kernel.  Because the spinlock_t type becomes a "sleeping"
spinlock w/ RT kernels, it is not suitable to be used with irq_chips.

A quick audit of the operations under the lock reveal that they do only
minimal, bounded work, and are therefore safe to do under a raw spinlock.
Signed-off-by: NJulia Cartwright <julia@ni.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The sysfs and debugfs entries for pin control drivers work better when
the individual pins are given real names, even if they are all just
"gpio0", "gpio1", etc.
Signed-off-by: NTimur Tabi <timur@codeaurora.org>
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

To prevent external signal crosstalk, some pins need to
enable input schmitt, like i2c pins, 32k-input pin and so on.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Allwinner pin controllers are also GPIO controllers.

Currently, if GPIOLIB is forgot to be chosen, the build of
pinctrl-sunxi.c will fail for lacking a lot of gpiochip_* functions.

Select GPIOLIB to ensure this driver can be built.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
Add support for the pins controlled by the R_PIO controller.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Allwinner A64 SoC has also a dedicated pin controller for Port L GPIOs,
which is called "Port Controller (CPUs-PORT)" in SoC User Manual.

Add a binding for this pin controller, like the ones in A23/33 and H3.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The compatible for Allwinner H5 pin controller is wrong written as
allwinner,sun50i-h5-r-pinctrl, however, it's really a generic pinctrl
rather than a "r" one.

Fix this compatible string.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

ARM64 Allwinner SoCs used to have every pinctrl driver selected in
ARCH_SUNXI. Change this to make their default value to (ARM64 &&
ARCH_SUNXI).
Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: NAndre Przywara <andre.przywara@arm.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Just fix spelling typos in comments.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Port D and port E GPIO loopback modes are commonly enabled via hardware
straps for use with front-panel buttons.  When the BMC is powered
off or fails to boot, the front-panel buttons are directly connected to
the host chipset via the loopback to allow direct power-on and reset
control. Once the BMC has booted, the loopback mode must be disabled for
the BMC to take over control of host power-on and reset.

Disabling these loopback modes requires writing to the hardware strap
register which violates the current design of assuming the system
designer chose the strap settings for a specific reason and they should
be treated as read-only. Only the two bits of the strap register related
to these loopback modes are allowed to be written and comments have been
added to explain why.
Signed-off-by: NRick Altherr <raltherr@google.com>
Acked-by: NJoel Stanley <joel@jms.id.au>
Reviewed-by: NAndrew Jeffery <andrew@aj.id.au>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Note, the iomux of following pins are special, need to
be recalculated specially.
 - gpio2_b4
 - gpio2_b7
 - gpio2_c7
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Some pins are special at a bank so that add
IOMUX_RECALCED type to indicate which iomux source
of the bank need to be recalculated. If the mux
recalculateed callback and IOMUX_RECALCED type
were set, recalculate the pins' iomux by using
mux recalculated data struct.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch supports 3bit width iomux type.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The local variable drvdata is not used in samsung_gpio_set_direction.
Signed-off-by: NCharles Keepax <ckeepax@opensource.wolfsonmicro.com>
Reviewed-by: NKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NCharles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>