As we have support for this in board-rx51-peripherals.c, let's
add it to the .dts files too.

Note that the reset GPIO will eventually go to the driver.
For now let's just pull it down and skip any further reset
in case the bootloader has configured the MAC address so
NFSroot works.

Also note that after 3430-sdp are using proper GPMC timings
we can remove the tests for smsc,lan91c94 in gpmc.c.
Signed-off-by: NTony Lindgren <tony@atomide.com>

There are external pulls on these lines and enabling the
internal pulls can cause issue. This is because the internal
pulls are parallel with the external pulls. So let's clear
the internal I2C pulls.
Signed-off-by: NTony Lindgren <tony@atomide.com>

This is no longer needed as the device specific wake-up event
can now be specified with interrupts-extended property where
the second interrupt is the pinctrl-single register, such as
the UART3 RX pin.

Note that twl4030_omap3.dtsi needs to set WAKEUPENABLE for
off-idle to properly trigger the PMIC scripts. And GPIO pins
still need to set WAKEUPENABLE for wake-up events.
Signed-off-by: NTony Lindgren <tony@atomide.com>

Compared to legacy booting, we don't have wake-up events enabled
for device tree based booting. This means that if deeper idle
states are enabled, the device won't wake up to UART events and
seems like it has hung.

Let's fix that by adding the wake-up interrupt. Note that we
don't need to set the PIN_OFF_WAKEUPENABLE any longer, that's
handled by the wake-up interrupt when the serial driver does
request_irq on it.

Tested with the following on omap3-overo-summit that has the
ES2.1 omap:

#!/bin/bash

uarts=$(find /sys/class/tty/ttyO*/device/power/ -type d)
for uart in $uarts; do
        echo 3000 > $uart/autosuspend_delay_ms
done

uarts=$(find /sys/class/tty/ttyO*/power/ -type d)
for uart in $uarts; do
        echo enabled > $uart/wakeup
        echo auto > $uart/control
done

echo 1 > /sys/kernel/debug/pm_debug/enable_off_mode

# grep -i uart /proc/interrupts
 90:       1085      INTC  74  OMAP UART2
338:          5   pinctrl 366  OMAP UART2

# grep ^core_pwrdm /sys/kernel/debug/pm_debug/count
core_pwrdm (ON),OFF:1654,RET:131,INA:39,ON:1825...
Signed-off-by: NTony Lindgren <tony@atomide.com>

The sub-mailbox devices are added to the Mailbox DT nodes on
OMAP2420, OMAP2430, OMAP3, AM33xx, AM43xx, OMAP4 and OMAP5
family of SoCs. This data represents the same mailboxes that
used to be represented in hwmod attribute data previously.
The node name is chosen based on the .name field of
omap_mbox_dev_info structure used in the hwmod data.

Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Mark rxd as wakeupcapable for 115200n8 no hardware-flow control
configuration. If h/w flow control is being used, then rts/cts
appropriately should be used.
Signed-off-by: NNishanth Menon <nm@ti.com>

We've had deeper idle states working on omaps for few years now,
but only in the legacy mode. When booted with device tree, the
wake-up events did not have a chance to work until commit
3e6cee17 ("pinctrl: single: Add support for wake-up interrupts")
that recently got merged. In addition to that we also needed
commit 79d97015 ("of/irq: create interrupts-extended property")
that's now also merged.

Note that there's no longer need to specify the wake-up bit in
the pinctrl settings, the request_irq on the wake-up pin takes
care of that.
Signed-off-by: NNishanth Menon <nm@ti.com>

Now that ti,am437-padconf is available, switch over to that compatible
property. Retain pinctrl-single for legacy support.

While at it, mark the pinctrl as interrupt controller so that it can
be used with interrupts-extended property for wakeup events.
Signed-off-by: NNishanth Menon <nm@ti.com>

Now that ti,dra7-padconf is available, switch over to that compatible
property. Retain pinctrl-single for legacy support.

While at it, mark pinctrl as interrupt controller so that it can be used
with interrupts-extended property for wakeup events.
Signed-off-by: NNishanth Menon <nm@ti.com>

Now that ti,omap5-padconf is available, switch over to that compatible
property. Retain pinctrl-single for legacy support.

While at it, mark pinctrl as interrupt controller so that it can be
used with interrupts-extended property for wakeup events.
Signed-off-by: NNishanth Menon <nm@ti.com>

Add regulator-name properties for the regulators that don't have them,
allowing the kernel to display the name from the schematic rather than
the name of the regulator on the PMIC in order to improve diagnostics.
Signed-off-by: NMark Brown <broonie@kernel.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

CM-T54 CoM can be used with various custom baseboards, other
than SB-T54 (supplied with SBC-T54 single board computer).

Update model property of SBC-T54 DT to clarify this.
Signed-off-by: NDmitry Lifshitz <lifshitz@compulab.co.il>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The RFBI node for OMAP DSS was left out when adding the rest of the DSS
nodes, because it was not clear how to set up the clocks for the RFBI.

However, it seems that if there is a HWMOD for a device, we also need a
DT node for it. Otherwise, at boot, we get:

WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2542 _init+0x464/0x4e0()
omap_hwmod: dss_rfbi: doesn't have mpu register target base

Now that v3.17-rc3 contains a fix 8fd46439 ("ARM: dts:
omap54xx-clocks: Fix the l3 and l4 clock rates") for the L3 ICLK
required by the RFBI, let's add the RFBI node to get rid of the
warning.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
[tony@atomide.com: updated description per comments from Nishant]
Signed-off-by: NTony Lindgren <tony@atomide.com>

These baseboards are equipped with the Technexion TAO35030 SOM. So
they include this dtsi. The common parts are extracted into an "common"
dtsi file. The main difference between both boards is, that the *lcd
has DSS support enabled for the LCD.

Some HEAD acoustics specific features are:

- LED handling
- Special FPGA/DSP audio driver (not included in this series)
- powerdown GPIO
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Thorsten Eisbein <thorsten.eisbein@head-acoustics.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This baseboard is equipped with the Technexion TAO35030 SOM. So
includes this dtsi. Some Thunder specific features are:

- LCD panel
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Thorsten Eisbein <thorsten.eisbein@head-acoustics.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The Technexion TAO3530 is a OMAP3530 based SOM. This patch adds the
basic support for it as an dtsi file which can be included by
baseboard equipped with this SOM. E.g. the Technexion Thunder
baseboard.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Thorsten Eisbein <thorsten.eisbein@head-acoustics.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

DRA72x-evm uses TPS65917 PMIC. Add the node.

NOTE: LDO2 is actually unused, but the usage if any is expected to be
between 1.8 to 3.3v IO voltage. So define the node.

NOTE: Interrupt used is crossbar number based.
Tested-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Tested-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

I2C1 bus is used for the following peripherals
	P8 connector (MLB)
	TLV320AIC3106 Audio codec
	J15 LCD header
	24WC256 eeprom
	TMP102AIDRLT temperature sensor
	PCF8575 GPIO expander
	PCA9306 i2c voltage translator -> Goes to P9 for comm interface
	P2 expansion connector
	TPS65917 PMIC

The slowest speed of all the peripherals seems to be 400KHz.
Tested-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Tested-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Commit 43fef47f (mfd: twl4030-power: Add a configuration to turn
off oscillator during off-idle) added support for configuring the PMIC
to cut off resources during deeper idle states to save power.

This however caused regression for n900 display power that needed the
PMIC configuration to be disabled with commit d937678a (ARM: dts:
Revert enabling of twl configuration for n900).

Turns out the root cause of the problem is that we must use
TWL4030_RESCONFIG_UNDEF instead of DEV_GRP_NULL to avoid disabling
regulators that may have been enabled before the init function
for twl4030-power.c runs. With TWL4030_RESCONFIG_UNDEF we let the
regulator framework control the regulators like it should. Here we
need to only configure the sys_clken and sys_off_mode triggers for
the regulators that cannot be done by the regulator framework as
it's not running at that point.

This allows us to enable the PMIC configuration for n900.

Fixes: 43fef47f (mfd: twl4030-power: Add a configuration to turn off oscillator during off-idle)

Cc: stable@vger.kernel.org # v3.16
Signed-off-by: NTony Lindgren <tony@atomide.com>
Tested-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This patch is important for the MicroSOM implementation due to the
following details -

1. VIH of the Atheros phy is 1.7V.
2. NVCC_ENET which is the power domain of the MDIO pad is driven by the
   PHY's LDO (i.e. either 1.8v or 2.5v).
3. The MicroSOM implements an onbouard 1.6kohm pull up to 3.3v (R3000).

In the case the PHY's LDO was 1.8v then there would be only a 100mV
margin for the signal to be acknowledged as high (1.8v-1.7v).
Due to that setting the pad as an open drain will let the 1.6kohm pull
that signal high to 3.3 that assures enough margins to the PHY to be
acked as '1' logic.
Signed-off-by: NRabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Similarly to DRA7, OMAP5 has l3 and l4 clock rates incorrectly calculated.
Fixed by using proper divider clock types for the clock nodes.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Reported-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Tested-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

For device tree based booting, we need to use wake-up
interrupts like we already do for some omaps. This fixes
a PM regression on beagleboard compared to legacy booting.
Tested-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The kernel has never supported clk32g as a regulator since it is a clock
and not a regulator. Fortunately nothing actually references this node so
we can just remove it.
Signed-off-by: NMark Brown <broonie@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

GPIO modules are also interrupt sources. However, they require both the
GPIO number and IRQ type to function properly.

By declaring that GPIO uses interrupt-cells=<1>, we essentially do not
allow users of the nodes to use the interrupt property appropritely.

With this change, the following now works:

interrupt-parent = <&gpio6>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;

Fixes: 6e58b8f1 ('ARM: dts: DRA7: Add the dts files for dra7 SoC and dra7-evm board')
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

For v3.14 and prior, 1-bit Hamming code ECC via software was used
for NAND on this board.
Commit c06c5270 in v3.15 changed the behaviour
to use 1-bit Hamming code via Hardware using a different ECC layout
i.e. (ROM code layout) than what is used by software ECC.

This ECC layout change causes NAND filesystems created in v3.14
and prior to be unusable in v3.15 and later. So revert back to
using software ECC scheme.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Hummingboard has no over current hardware, so disable the over current
detection for both ports.

Cubox-i has over current hardware, so appropriately configure this.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

On r8a7791, i2c6 (aka iic3) doesn't need pinmux, but the koelsch dts
refers to non-existent pinmux configuration data:

pinmux core: sh-pfc does not support function i2c6
sh-pfc e6060000.pfc: invalid function i2c6 in map table

Remove it to fix this.

Fixes: commit 1d41f36a ("ARM: shmobile:
       koelsch dts: Add VDD MPU regulator for DVFS")
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Working on Gigabit/PCIe support in U-Boot for Apalis T30 I realised
that the current device tree source includes for our modules only
happen to work due to referencing the on-carrier 5v0 supply from USB
which is not at all available on-module. The modules actually contain
TPS60150 charge pumps to generate the PMIC required 5 volts from the
one and only 3.3 volt module supply. This patch fixes this.

(Note: When back-porting this to v3.16 stable releases, simply drop the
change to tegra30-apalis.dtsi; that file was added in v3.17)

Cc: <stable@vger.kernel.org> #v3.16+
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

During the restructuring of the Rockchip Cortex-A9 dtsi files it seems
like the pinctrl settings vanished at some point from the mmc0 support.

This of course renders them unusable, so readd the necessary pinctrl
properties.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Increase max i2c bus frequency beyond the default for faster
data transfers. According to the manual, these faster speeds are
only available when the board is wired up the right way. In this case,
the vendor kernel has run at this speed for a long time.

sda-delay is needed for talking to RTC on PMIC, otherwise the i2c
controller never sees an ACK. Strangely the other PMIC i2c slave (the
main one) works fine even without this delay. I Chose value 100 to
match the vendor kernel.
Signed-off-by: NDaniel Drake <drake@endlessm.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Tested-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The ODROID kernel shows that the PMIC interrupt line is hooked up
to pin GPX3-2.

This is needed for the max77686-irq driver to create the PMIC IRQ
domain, which is needed by max77686-rtc.
Signed-off-by: NDaniel Drake <drake@endlessm.com>
Tested-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The following error is seen after a suspend/resume cycle on a mx53qsb with a
MC34708 PMIC:

root@freescale /$ echo mem > /sys/power/state
[   32.630592] PM: Syncing filesystems ... done.
[   32.643924] Freezing user space processes ... (elapsed 0.001 seconds) done.
[   32.652384] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
[   32.679156] PM: suspend of devices complete after 13.113 msecs
[   32.685128] PM: suspend devices took 0.030 seconds
[   32.696109] PM: late suspend of devices complete after 6.133 msecs
[   33.313032] mc13xxx 0-0008: Failed to read IRQ status: -110
[   33.322009] PM: noirq suspend of devices complete after 619.667 msecs
[   33.328544] Disabling non-boot CPUs ...
[   33.335031] PM: noirq resume of devices complete after 2.352 msecs
[   33.842940] mc13xxx 0-0008: Failed to read IRQ status: -110
[   33.976095] [sched_delayed] sched: RT throttling activated
[   33.984804] PM: early resume of devices complete after 642.642 msecs
[   34.352954] mc13xxx 0-0008: Failed to read IRQ status: -110
[   34.862910] mc13xxx 0-0008: Failed to read IRQ status: -110
[   34.996595] PM: resume of devices complete after 1005.367 msecs
[   35.372925] mc13xxx 0-0008: Failed to read IRQ status: -110
[   35.882911] mc13xxx 0-0008: Failed to read IRQ status: -110
[   35.955707] PM: resume devices took 1.970 seconds
[   35.960445] Restarting tasks ... done.
[   35.993386] fec 63fec000.ethernet eth0: Link is Down
[   36.392980] mc13xxx 0-0008: Failed to read IRQ status: -110
[   36.902908] mc13xxx 0-0008: Failed to read IRQ status: -110
[   36.953036] ata1: SATA link down (SStatus 0 SControl 300)
[   37.412922] mc13xxx 0-0008: Failed to read IRQ status: -110
[   37.922906] mc13xxx 0-0008: Failed to read IRQ status: -110
[   37.993379] fec 63fec000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx
[   38.432938] mc13xxx 0-0008: Failed to read IRQ status: -110
[   38.942920] mc13xxx 0-0008: Failed to read IRQ status: -110
[   39.452933] mc13xxx 0-0008: Failed to read IRQ status: -110

(flood of this error message continues forever)

Commit 5169df8b ("ARM: dts: i.MX53: add support for MCIMX53-START-R")
missed to configure the IOMUX for the PMIC IRQ pin.

Configure the PMIC IRQ pin so that the suspend/resume sequence behaves cleanly
as expected.

Cc: <stable@vger.kernel.org> # 3.16
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The current pinfunc define all uart CTS_B IO port for DCE uart 'CTS_B'
IP port. Since uart IP port 'CTS_B' is output, and it don't need to
set 'SELECT_INPUT' bit.
Signed-off-by: NFugang Duan <B38611@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The VPU on i.MX53 has two distinct clocks for register access and
internal function.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Fixes: fbf970f6 ("ARM: dts: mx53qsb: Enable VPU support")
Cc: <stable@vger.kernel.org>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Signed-off-by: NSilvio Fricke <silvio.fricke@gmail.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Previous version had an extra 'fsl' which made the pins not match
any entry.  The console message,

 vf610-pinctrl 40048000.iomuxc: no fsl,pins property in node \
    /soc/aips-bus@40000000/iomuxc@40048000/vf610-twr/esdhc1grp

is displayed without the fix.  The prior version would generally
work as u-boot sets the pins properly for sdhc.  This change allows
Linux sdhc use even if u-boot is built without sdhc support.
Signed-off-by: NBill Pringlemeir <bpringlemeir@nbsps.com>
Acked-by: NStefan Agner <stefan@agner.ch>
Fixes: 0517fe6a ("ARM: dts: vf610-twr: Add support for sdhc1")
Cc: <stable@vger.kernel.org>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This was caused by commit 5a8da524 ("ARM: dts: exynos5420: add dsi
node"), which conflicted with d51cad7d ("ARM: dts: remove display
power domain for exynos5420").

The DTS addition should never have been merged through the DRM tree in
the first place, and it lacked an ack from the platform maintainer
(who would have known that the disp_pd reference got removed).
Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The EHCI and HSIC device tree nodes were added in the wrong place.
Fix them.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch adds common part of dsi node.
Signed-off-by: NYoungJun Cho <yj44.cho@samsung.com>
Acked-by: NInki Dae <inki.dae@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>