- 20 2月, 2019 1 次提交
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由 Chen-Yu Tsai 提交于
commit d6f11e7d91f2ac85f66194fe3ef8789b49901d64 upstream. The MMC device tree bindings include properties used to signal various signalling speed modes. Until now the sunxi driver was accepting them without any further filtering, while the sunxi device trees were not actually using them. Since some of the H5 boards can not run at higher speed modes stably, we are resorting to declaring the higher speed modes per-board. Regardless, having boards declare modes and blindly following them, even without proper support in the driver, is generally a bad thing. Filter out all unsupported modes from the capabilities mask after the device tree properties have been parsed. Cc: <stable@vger.kernel.org> Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 01 8月, 2018 2 次提交
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由 Andre Przywara 提交于
Recent Linux versions refuse to print actual virtual kernel addresses, to not give a hint about the location of the kernel in a randomized virtual address space. This affects the output of the sunxi MMC controller driver, which now produces the rather uninformative line: [ 1.482660] sunxi-mmc 1c0f000.mmc: base:0x(____ptrval____) irq:8 Since the virtual base address is not really interesting in the first place, let's just drop this value. The same applies to Linux' notion of the interrupt number, which is independent from the GIC SPI number. We have the physical address as part of the DT node name, which is way more useful for debugging purposes. To keep a success message in the driver, we make this purpose explicit with the word "initialized", plus print some information that is not too obvious and that we learned while probing the device: the maximum request size and whether it uses the new timing mode. So the output turns into: [ 1.750626] sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 KB, uses new timings mode [ 1.786699] sunxi-mmc 1c11000.mmc: initialized, max. request size: 2048 KB Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Icenowy Zheng 提交于
Some Allwinner boards feature an on-board eMMC with fixed 3.3V voltage (e.g. Banana Pi M2+), and in this case both the eMMC and the SoC are capable of doing 3.3V DDR transmission. Add capability of 3.3V DDR when DDR is available (extra clock or new timing). Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 05 7月, 2018 1 次提交
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由 Stefan Mavrodiev 提交于
When mmc host controller enters suspend state, the clocks are disabled, but irqs are not. For some reason the irqchip emits false interrupts, which causes system lock loop. Debug log is: ... sunxi-mmc 1c11000.mmc: setting clk to 52000000, rounded 51200000 sunxi-mmc 1c11000.mmc: enabling the clock sunxi-mmc 1c11000.mmc: cmd 13(8000014d) arg 10000 ie 0x0000bbc6 len 0 sunxi-mmc 1c11000.mmc: irq: rq (ptrval) mi 00000004 idi 00000000 sunxi-mmc 1c11000.mmc: cmd 6(80000146) arg 3210101 ie 0x0000bbc6 len 0 sunxi-mmc 1c11000.mmc: irq: rq (ptrval) mi 00000004 idi 00000000 sunxi-mmc 1c11000.mmc: cmd 13(8000014d) arg 10000 ie 0x0000bbc6 len 0 sunxi-mmc 1c11000.mmc: irq: rq (ptrval) mi 00000004 idi 00000000 mmc1: new DDR MMC card at address 0001 mmcblk1: mmc1:0001 AGND3R 14.6 GiB mmcblk1boot0: mmc1:0001 AGND3R partition 1 4.00 MiB mmcblk1boot1: mmc1:0001 AGND3R partition 2 4.00 MiB sunxi-mmc 1c11000.mmc: cmd 18(80003352) arg 0 ie 0x0000fbc2 len 409 sunxi-mmc 1c11000.mmc: irq: rq (ptrval) mi 00004000 idi 00000002 mmcblk1: p1 sunxi-mmc 1c11000.mmc: irq: rq (null) mi 00000000 idi 00000000 sunxi-mmc 1c11000.mmc: irq: rq (null) mi 00000000 idi 00000000 sunxi-mmc 1c11000.mmc: irq: rq (null) mi 00000000 idi 00000000 sunxi-mmc 1c11000.mmc: irq: rq (null) mi 00000000 idi 00000000 and so on... This issue apears on eMMC cards, routed on MMC2 slot. The patch is tested with A20-OLinuXino-MICRO/LIME/LIME2 boards. Fixes: 9a8e1e8c ("mmc: sunxi: Add runtime_pm support") Signed-off-by: NStefan Mavrodiev <stefan@olimex.com> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 30 5月, 2018 1 次提交
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由 Ulf Hansson 提交于
To be consistent with code in other mmc host drivers, convert to check the correct PM config #ifdef in favor of using __maybe_unused. Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 29 5月, 2018 1 次提交
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由 Arnd Bergmann 提交于
The newly added runtime-pm functions cause a harmless warning when CONFIG_PM is disabled: drivers/mmc/host/sunxi-mmc.c:1452:12: error: 'sunxi_mmc_runtime_suspend' defined but not used [-Werror=unused-function] static int sunxi_mmc_runtime_suspend(struct device *dev) ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mmc/host/sunxi-mmc.c:1435:12: error: 'sunxi_mmc_runtime_resume' defined but not used [-Werror=unused-function] static int sunxi_mmc_runtime_resume(struct device *dev) This marks them as __maybe_unused to shut up the warning. Fixes: 9a8e1e8c ("mmc: sunxi: Add runtime_pm support") Signed-off-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 02 5月, 2018 7 次提交
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由 Maxime Ripard 提交于
Our set_ios hook is, when the card is power up or down, either doing a full init or put our controller back into a reset mode. Since we're also doing that in our runtime_pm hooks, and at possibly much more often, we can drop it from the set_ios, and either rely on our runtime_pm hooks or our probe to do it. Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Maxime Ripard 提交于
So far, even if our card was not in use, we didn't shut down our MMC controller, which meant that it was still active and clocking the bus. While this obviously means that we could save some power there, it also creates issues when it comes to EMC control since we'll have a perfect peak at the card clock rate. Let's implement runtime_pm with autosuspend so that we will shut down the controller when it's not been in use for quite some time. Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Maxime Ripard 提交于
In order to improve readibility and reusability, let's move the card setup to a small function called by our .set_ios hook. Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Maxime Ripard 提交于
In order to improve readibility and reusability, let's move the clock setup to a small function called by our .set_ios hook. Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Maxime Ripard 提交于
In order to improve readibility and reusability, let's move the bus width setup to a small function called by our .set_ios hook. Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Maxime Ripard 提交于
All the other functions in the driver take a struct sunxi_mmc_host pointer. Let's make it consistent. Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Maxime Ripard 提交于
Our headers sort algorithm has had pretty chaotic results. Let's fix that. Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 15 3月, 2018 3 次提交
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由 Maxime Ripard 提交于
As soon as the pm_runtime_enable hook is called, our runtime_suspend and runtime_resume hooks can be called as well. However, we only set the device drvdata that we will use after we have registered into the MMC core. Move that earlier so that we don't have a race that could lead to a crash. Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Maxime Ripard 提交于
As per Allwinner guidelines, the reset line should be deasserted before turning the clocks on. Implement it in our driver as well. Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Maxime Ripard 提交于
We've had all our resources management, and especially the clocks and reset sequence, done directly as part of the probe. As we want to implement runtime_pm, we'll obviously want to have that moved outside of the probe so that we can call do it in our runtime suspend and resume hooks without too much duplication. Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 15 12月, 2017 1 次提交
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由 Arvind Yadav 提交于
platform_get_irq() can fail here and we must check its return value. Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 11 12月, 2017 1 次提交
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由 Adam Borowski 提交于
It had an U+FFFD: not a corrupted character but a literal well-formed replacement marker. Signed-off-by: NAdam Borowski <kilobyte@angband.pl> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 30 10月, 2017 1 次提交
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由 Wolfram Sang 提交于
This error message can go because a) currently nothing else than EPROBE_DEFER is returned and b) if this is going to change a much more detailed error message should come from mmc_regulator_get_supply() anyhow. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 30 8月, 2017 9 次提交
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由 Maxime Ripard 提交于
We might be into some troubles if the bootloader misconfigured the MMC controller. We currently only de-assert the reset line at probe time, which means that if the device was already out of reset, we're going to keep whatever state was set already. Switch to a reset instead of the deassert to have a device in a pristine state when we start operating. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chen-Yu Tsai 提交于
sunxi_mmc_clk_set_phase expects the actual card clock rate to be passed to it. When the internal divider code was reworked in change ("mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode"), this requirement was missed, and the module clock rate was passed in instead. This broke 8 bit DDR MMC on old controllers, as the module clock rate is double the card clock rate, for which we have no valid delay settings. Fix this by applying the internal divider to the clock rate right after we configure it in hardware. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Icenowy Zheng 提交于
The A83T MMC support code introduces the timings mode switch, however such a switch doesn't exist on new SoCs with only new timings mode. Only execute the switch if the SoC really have the timings mode switch, to fix the regression shown on new timings mode only SoCs (A64, H5, etc). Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Reviewed-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chen-Yu Tsai 提交于
Some SoCs do not support clk delays for MMC in the clock control unit. These include the old controllers in A10/A10s/A13/R8, and the new eMMC controller in A64. The config structure for these controllers do not specify clk_delays, but the check for this was replaced in change "mmc: sunxi: Support controllers that can use both old and new timings". This patch adds back the check for clk_delays, and also adds comments for both checks in sunxi_mmc_clk_set_phase(). Signed-off-by: NChen-Yu Tsai <wens@csie.org> Tested-by: NIcenowy Zheng <icenowy@aosc.io> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chen-Yu Tsai 提交于
The third MMC controller (MMC2) on the Allwinner A83T SoC is slightly different. It supports a wider 8-bit bus, has a dedicated controllable reset pin for eMMC, and a "new timing mode" which is supposed to deliver better signals and thus better performance. Add a compatible for this one to use the new timing mode not found in the other controllers. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NRob Herring <robh@kernel.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chen-Yu Tsai 提交于
The MMC controller can support DDR52 transfers under the new timing mode. According to the BSP kernel, the module clock has to be double the card clock, regardless of the bus width. The default timings in the hardware can be used. This also reworks the code setting the internal divider, getting rid of a extra conditional. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chen-Yu Tsai 提交于
On the SoCs that introduced the new timing mode for MMC controllers, both the old (where the clock delays are set in the CCU) and new (where the clock delays are set in the MMC controller) timing modes are available, and we have to support them both. However there are two bits that control which mode is active. One is in the CCU, the other is in the MMC controller. The settings on both sides must be the same, or nothing will work. The sunxi-ng clock driver provides an API to query and set the active timing mode. At probe time, we try to set the active mode to the "new timing mode". If it succeeds, we can then use the MMC controller in the new mode. If not, we fall back to the old mode. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Julia Lawall 提交于
The mmc_host_ops structure is only stored in the ops field of an mmc_host structure, which is declared as const. Thus the mmc_host_ops structure itself can be const. Done with the help of Coccinelle. // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct mmc_host_ops i@p = { ... }; @ok1@ struct mmc_host *mmc; identifier r.i; position p; @@ mmc->ops = &i@p @bad@ position p != {r.p,ok1.p}; identifier r.i; struct mmc_host_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct mmc_host_ops i = { ... }; // </smpl> Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Philipp Zabel 提交于
Commit a53e35db ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: linux-mmc@vger.kernel.org Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 17 7月, 2017 1 次提交
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由 Chen-Yu Tsai 提交于
The register for the "new timing mode" also has bit fields for setting output and sample timing phases. According to comments in Allwinner's BSP kernel, the default values are good enough. Keep the default values already in the hardware when setting new timing mode, instead of overwriting the whole register. Fixes: 9a37e53e ("mmc: sunxi: Enable the new timings for the A64 MMC controllers") Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Cc: <stable@vger.kernel.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 25 4月, 2017 2 次提交
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由 Heiner Kallweit 提交于
Use new core function mmc_get_dma_dir(). Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Icenowy Zheng 提交于
The controller's errors are usually normal (for example, for MMC or SDIO cards, some errors are expected to happen; and for boards without a dedicated card detect pin the error info will even flood console and hide other normal messages) and hard to understand. Change their print level to debug, thus it won't be shown to generic users. Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 13 2月, 2017 7 次提交
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由 Maxime Ripard 提交于
Add a bit more debug messages that can be helpful when debugging the clock setup. Also fill the actual_clock field in struct mmc_host to report properly the current frequency in debugfs. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Tested-by: NFlorian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Maxime Ripard 提交于
The MMC2 controller on the A64 is kind of a special beast. While the general controller design is the same than the other MMC controllers in the SoC, it also has a bunch of features and changes that prevent it to be driven in the same way. It has for example a different bus width limit, a different maximum frequency, and, for some reason, the maximum buffer size of a DMA descriptor. Add a new compatible specifically for this controller. Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Tested-by: NFlorian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Maxime Ripard 提交于
The A64 MMC controllers need DATA0 to be masked while updating the clock, otherwise any subsequent command will result in a timeout. It's not really clear at this point what DATA0 is exactly, but this behaviour is present in Allwinner's tree, and has been suggested by Allwinner engineers as fixes for the timeout. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Tested-by: NFlorian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Maxime Ripard 提交于
The A64 MMC controllers need to set a "new timings" bit when a new rate is set. The actual meaning of that bit is not clear yet, but not setting it leads to some corner-case issues, like the CMD53 failing, which is used to implement SDIO packet aggregation. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Tested-by: NFlorian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Maxime Ripard 提交于
Experience have shown that the using the autocalibration could severely degrade the performances of the MMC bus. Allwinner is using in its BSP a delay set to 0 for all the modes but HS400. Remove the calibration code for now, and add comments to document our findings. Reviewed-by: NAndre Przywara <andre.przywara@arm.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Tested-by: NFlorian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Maxime Ripard 提交于
The MMC core assumes that the code will gate the clock when the bus frequency is set to 0, which we've been ignoring so far. Handle that. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Tested-by: NFlorian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Maxime Ripard 提交于
The SD specification documents that the clock frequency should only be changed once gated (Section 3.2.3 - SD Clock Frequency Change Sequence). The current code first modifies the parent clock, gates it and then modifies the internal divider. This means that since the parent clock rate might be changed, the bus clock might be changed as well before it is gated, which breaks the specification. Move the gating before the parent rate modification. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Tested-by: NFlorian Vaussard <florian.vaussard@heig-vd.ch> Acked-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 29 11月, 2016 1 次提交
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由 Maxime Ripard 提交于
VMMC is an optional regulator, which means that mmc_regulator_get_supply will only return an error in case of a deferred probe, but not when the regulator is not set in the DT. However, the sunxi driver assumes that VMMC is always there, and doesn't check the value of the regulator pointer before using it, which obviously leads to a (close to) null pointer dereference. Add proper checks to prevent that. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Acked-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 27 9月, 2016 1 次提交
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由 Icenowy Zheng 提交于
A64 SoC features a MMC controller which need only the mod clock, and can calibrate delay by itself. This patch adds support for the new MMC controller IP core. Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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