The SD specification documents that the clock frequency should only be
changed once gated (Section 3.2.3 - SD Clock Frequency Change Sequence).

The current code first modifies the parent clock, gates it and then
modifies the internal divider. This means that since the parent clock rate
might be changed, the bus clock might be changed as well before it is
gated, which breaks the specification.

Move the gating before the parent rate modification.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: NFlorian Vaussard <florian.vaussard@heig-vd.ch>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>