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  1. 06 4月, 2015 1 次提交
  3. 01 4月, 2015 1 次提交
  5. 26 3月, 2015 1 次提交
  7. 17 3月, 2015 1 次提交
  9. 25 2月, 2015 1 次提交
  11. 29 1月, 2015 3 次提交
  13. 14 1月, 2015 1 次提交
  15. 09 1月, 2015 1 次提交
  17. 24 11月, 2014 2 次提交
  19. 18 11月, 2014 1 次提交
  21. 29 9月, 2014 1 次提交
  23. 15 9月, 2014 1 次提交
  25. 23 7月, 2014 4 次提交
    • D
      clocksource: exynos_mct: Only use 32-bits where possible · 3252a646
      由 Doug Anderson 提交于 
      The MCT has a nice 64-bit counter.  That means that we _can_ register
as a 64-bit clocksource and sched_clock.  ...but that doesn't mean we
should.

The 64-bit counter is read by reading two 32-bit registers.  That
means reading needs to be something like:
- Read upper half
- Read lower half
- Read upper half and confirm that it hasn't changed.

That wouldn't be terrible, but:
- THe MCT isn't very fast to access (hundreds of nanoseconds).
- The clocksource is queried _all the time_.

In total system profiles of real workloads on ChromeOS, we've seen
exynos_frc_read() taking 2% or more of CPU time even after optimizing
the 3 reads above to 2 (see below).

The MCT is clocked at ~24MHz on all known systems.  That means that
the 32-bit half of the counter rolls over every ~178 seconds.  This
inspired an optimization in ChromeOS to cache the upper half between
calls, moving 3 reads to 2.  ...but we can do better!  Having a 32-bit
timer that flips every 178 seconds is more than sufficient for Linux.
Let's just use the lower half of the MCT.

Times on 5420 to do 1000000 gettimeofday() calls from userspace:
* Original code:                      1323852 us
* ChromeOS cache upper half:          1173084 us
* ChromeOS + ldmia to optimize:       1045674 us
* Use lower 32-bit only (this code):  1014429 us

As you can see, the time used doesn't increase linearly with the
number of reads and we can make 64-bit work almost as fast as 32-bit
with a bit of assembly code.  But since there's no real gain for
64-bit, let's go with the simplest and fastest implementation.

Note: with this change roughly half the time for gettimeofday() is
spent in exynos_frc_read().  The rest is timer / system call overhead.

Also note: this patch disables the use of the MCT on ARM64 systems
until we've sorted out how to make "cycles_t" always 32-bit.  Really
ARM64 systems should be using arch timers anyway.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Acked-by Vincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      3252a646
    • C
      clocksource: Kconfig: Let EM_TIMER_STI depend on HAS_IOMEM · 40c96312
      由 Chen Gang 提交于 
      In 'em_sti.c', it will call devm_ioremap_resource() which need
HAS_IOMEM. So need let EM_TIMER_STI depend on HAS_IOMEM, too.

The related error (with allmodconfig under score):

  LD      init/built-in.o
em_sti.c:(.text.em_sti_probe+0x84): undefined reference to `devm_ioremap_resource'
make: *** [vmlinux] Error 1
Signed-off-by: NChen Gang <gang.chen.5i5j@gmail.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      40c96312
    • M
      clocksource: Add support for the Mediatek SoCs · ecb3530d
      由 Matthias Brugger 提交于 
      This patch adds a clock source and clock event for the timer found
on the Mediatek SoCs.

The Mediatek General Purpose Timer block provides five 32 bit timers and
one 64 bit timer.

Two 32 bit timers are used by this driver:
TIMER1: clock events supporting periodic and oneshot events
TIMER2: clock source configured as a free running counter

The General Purpose Timer block can be run with two clocks. A 13 MHz system
clock and the RTC clock running at 32 KHz. This implementation uses the system
clock with no clock source divider.

The interrupts are shared between the different timers and have to be read back
from a register. We just enable one interrupt for the clock event. The clock
event timer is used by all cores.
Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      ecb3530d
    • K
      clocksource: sh_mtu2: Tidy up Kconfig typo for MTU2 · 7e139187
      由 Kuninori Morimoto 提交于 
      It should be "MTU2" instead of "TMU2"
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: NWolfram Sang <wsa@sang-engineering.com>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      7e139187
  27. 22 6月, 2014 1 次提交
  29. 27 5月, 2014 1 次提交
    • A
      ARM: vexpress: refine dependencies for new code · b33cdd28
      由 Arnd Bergmann 提交于 
      The versatile express changes for 3.16 introduced a number of
build regressions for randconfig kernels by not tracking dependencies
between the components right.

This patch tries to rectify that:

* the mach-vexpress code cannot link without the syscfg driver,
  which in turn needs MFD_VEXPRESS_SYSREG
* various drivers call devm_regmap_init_vexpress_config(), which
  has to be exported so it can be used by loadable modules
* the configuration bus uses OF DT helper functions that are not
  available to platforms disable CONFIG_OF
* The sysreg driver exports GPIOs through gpiolib, which can
  be disabled on some platforms.
* The clocksource code cannot be built on platforms that don't
  use modern timekeeping but rely on gettimeoffset.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      b33cdd28
  31. 23 5月, 2014 1 次提交
    • X
      clocksource: Add Freescale FlexTimer Module (FTM) timer support · 2529c3a3
      由 Xiubo Li 提交于 
      The Freescale FlexTimer Module time reference is a 16-bit counter
that can be used as an unsigned or signed increase counter.

CNTIN defines the starting value of the count and MOD defines the
final value of the count. The value of CNTIN is loaded into the FTM
counter, and the counter increments until the value of MOD is reached,
at which point the counter is reloaded with the value of CNTIN. That's
also when an overflow interrupt will be generated.

Here using the 'evt' prefix or postfix as clock event device and
the 'src' as clock source device.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Jingchang Lu <b35083@freescale.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      2529c3a3
  33. 16 5月, 2014 1 次提交
  35. 22 3月, 2014 1 次提交
    • G
      clocksource: CMT, MTU2, TMU and STI should depend on GENERIC_CLOCKEVENTS · 87291a92
      由 Geert Uytterhoeven 提交于 
      If GENERIC_CLOCKEVENTS=n:

drivers/clocksource/sh_cmt.c:54:28: error: field 'ced' has incomplete type
drivers/clocksource/sh_cmt.c: In function 'sh_cmt_interrupt':
drivers/clocksource/sh_cmt.c:407:23: error: 'CLOCK_EVT_MODE_ONESHOT' undeclared (first use in this function)

drivers/clocksource/sh_mtu2.c:44:28: error: field 'ced' has incomplete type
drivers/clocksource/sh_mtu2.c: In function 'ced_to_sh_mtu2':
drivers/clocksource/sh_mtu2.c:184:70: warning: initialization from incompatible pointer type [enabled by default]
drivers/clocksource/sh_mtu2.c: At top level:
drivers/clocksource/sh_mtu2.c:188:16: warning: 'enum clock_event_mode' declared inside parameter list [enabled by default]

drivers/clocksource/sh_tmu.c:45:28: error: field 'ced' has incomplete type
drivers/clocksource/sh_tmu.c: In function 'sh_tmu_interrupt':
drivers/clocksource/sh_tmu.c:207:21: error: 'CLOCK_EVT_MODE_ONESHOT' undeclared (first use in this function)

drivers/clocksource/em_sti.c:44:28: error: field 'ced' has incomplete type
drivers/clocksource/em_sti.c: In function 'ced_to_em_sti':
drivers/clocksource/em_sti.c:251:69: warning: initialization from incompatible pointer type [enabled by default]
drivers/clocksource/em_sti.c: At top level:
drivers/clocksource/em_sti.c:255:16: warning: 'enum clock_event_mode' declared inside parameter list [enabled by default]
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Cc: Magnus Damm <damm@opensource.se>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: http://lkml.kernel.org/r/1395324352-9146-1-git-send-email-geert@linux-m68k.orgSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      87291a92
  37. 12 3月, 2014 1 次提交
  39. 05 2月, 2014 1 次提交
  41. 11 12月, 2013 2 次提交
  43. 21 11月, 2013 1 次提交
  45. 23 10月, 2013 2 次提交
  47. 26 9月, 2013 2 次提交
  49. 06 8月, 2013 1 次提交
  51. 03 7月, 2013 1 次提交
    • S
      clocksource: arm_global_timer: Add ARM global timer support · c1b40e44
      由 Stuart Menefy 提交于 
      This is a simple driver for the global timer module found in the Cortex
A9-MP cores from revision r1p0 onwards. This should be able to perform
the functions of the system timer and the local timer in an SMP system.

The global timer has the following features:
    The global timer is a 64-bit incrementing counter with an
auto-incrementing feature. It continues incrementing after sending
interrupts. The global timer is memory mapped in the private memory
region.
    The global timer is accessible to all Cortex-A9 processors in the
cluster. Each Cortex-A9 processor has a private 64-bit comparator that
is used to assert a private interrupt when the global timer has reached
the comparator value. All the Cortex-A9 processors in a design use the
banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
Controller as a Private Peripheral Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Rob Herring <robherring2@gmail.com>
CC: Linus Walleij <linus.walleij@linaro.org>
CC: Will Deacon <will.deacon@arm.com>
CC: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      c1b40e44
  53. 02 7月, 2013 1 次提交
  55. 12 6月, 2013 2 次提交
  57. 06 6月, 2013 1 次提交
  59. 29 4月, 2013 1 次提交