Nodes are sorted by their register start address. Move gpio_intc to the
correct position.
No functional changes intended.

Fixes: 7d32bc03 ("ARM: dts: meson8b: enable gpio interrupt controller")
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Meson6, Meson8 and Meson8b use a similar IP block which has access to
512 bytes of efuse data.
During SoC manufacturing some calibration settings for the CVBS
connector and the internal temperature sensor are written to this efuse.
On some boards it additionally stores for example the MAC addresses.

The efuse is enabled on Meson8 and Meson8b but kept disabled on Meson6
since we do not have a clock driver there (which is required to read
data from the efuse).
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Add gpio interrupt controller node to the meson8b boards
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Meson6, Meson8 and Meson8b are using the same MMC controller IP. This
adds the MMC controller node to meson.dtsi so it can be used by all
SoCs.

The controller itself is a bit special, because it has multiple slots.
Each slot is accessed through a sub-node of the controller. However,
currently the driver for this hardware only supports one slot.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The SoC type and version information is encoded in different register
blocks.
The SoC type information is part of the "assist" registers.
The misc version information is part of the "bootrom" registers.
On Meson8, Meson8b and Meson8m2 there is additionally information about
the minor version. This information is stored in the "analog top"
registers.

Add the nodes for these register blocks so we can decode the SoC type
and version information.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This patch fixes the Meson6, Meson8 and Meson8b USB controllers dts nodes
which interrupts are level type instead of edge type.
This avoids errors like "usb 1-1-port1: cannot reset (err = -110)" and
similars on Odroid-C1+ board.

Fixes: e29b1cf8 ("ARM: dts: meson: add USB support on Meson8 and Meson8b")
Signed-off-by: NEmiliano Ingrassia <ingrassia@epigenesys.com>
Tested-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: NLinus Lüssing <linus.luessing@c0d3.blue>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The UART bindings needs specifying a SoC family, use the meson6 family
for the UART nodes like the other nodes.
Switch to the stable UART bindings for meson6 by adding a XTAL node and
using the proper compatible strings.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

All 32bit Meson SoCs contain 128KiB SRAM. This SRAM is used when
suspending the device (the the ARM Power Firmware on
Meson8/Meson8b/Meson8m2 saves the DDR settings there) and to boot the
secondary CPU cores.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

According to the vendor kernel sources these also exist (at the same
address) on Meson6 and Meson8. This can be found by running
$ grep -R "define PWM_PWM_[A-D]" arch/arm/
in the Amlogic GPL kernel tree (arm-src-kernel-2015-01-15-321cfb5a46).
pwm_ef does not seem to exist on older SoCs, so we keep it in
meson8b.dtsi for now.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This adds the DWC2 USB controller nodes and the corresponding USB2 PHY
nodes to meson.dtsi (as the same - or at least a very similar) IP block
is used on all SoCs (at the same physical address).
Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the
DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be
initialized by the dwc2 driver.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

All supported Meson SoCs have a random number generator in CBUS.
Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number
register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two
32-bit random number registers. The existing meson-rng driver only
supports the lower 32-bit - but it still works fine on the older SoCs
apart from this small limitation.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This adds the SAR ADC to meson.dtsi and configures the clocks on Meson8
and Meson8b to allow boards to use it. Some boards use it to connect a
button to it.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This makes meson.dtsi easier to read as we are not using magic numbers
for the GIC interrupt type (GIC_SPI) and the interrupt polarity
(IRQ_TYPE_EDGE_RISING).
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The Amlogic Meson SoCs have most of the internal peripherals organized
in busses. Use them to make the dts easier to read and to avoid
duplicated register (bus) offset definitions.

The bus information is taken from the vendor kernel:
	#define IO_CBUS_PHY_BASE        0xc1100000  ///2M
	#define IO_AOBUS_PHY_BASE       0xc8100000  ///1M

There are more internal busses (such as the abp bus which seems to
contain audio, HDMI and Mali registers), but since we don't have
drivers for them yet these are not added (yet).
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
[khilman: minor whitespace fix]
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The DTS erronously uses the wrong reg mapping and IRQ numbers for some
UART, WDT and timer nodes. Fix this.
Reported-by: NJohn Wehle <john@feith.com>
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The DTS erronously uses the wrong reg mapping and IRQ numbers for some
UART, WDT and timer nodes. Fix this.
Reported-by: NJohn Wehle <john@feith.com>
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add a node for the Ethernet controller to Meson DTS file and
enable it on the Geniatech ATV1200 board.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: NCarlo Caione <carlo@endlessm.com>

This adds a node for the SPI Flash Controller to the Amlogic Meson
DTS.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Acked-by: NMark Brown <broonie@kernel.org>

This adds a node for the IR remote control receiver to the Amlogic
Meson DTS.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>

Add nodes for I2C controllers A,B,AO, which are available in both
Meson6 and Meson8.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: NCarlo Caione <carlo@caione.org>

This enables the L2 cache controller available in Amlogic SoCs.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NCarlo Caione <carlo@caione.org>

Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NCarlo Caione <carlo@caione.org>

The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex
A9 and an ARM Mali-400 GPU.
This patch adds two basic DTSI for the preliminary support of Meson and
Meson6 SoCs. Another DTS is also added for supporting the atv1200 board,
produced by Geniatech inc.
Signed-off-by: NCarlo Caione <carlo@caione.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>