This patch adds the basic platform file to support the pin controller
found on the Amlogic Meson GXBB SoCs.
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

In the Amlogic Meson8 / Meson8b platforms we have two different buses:
cbus and aobus, corresponding to 2 different power domains (regular and
always-on). On each bus a different set of registers is mapped to manage
muxes, GPIOs and in general to control a clear subset of the pins.

Considering this architecture, having two different pinctrl devices, one
for each bus / power domain, makes much more sense than just having one
single device.

Right now we have one single pin controller driver that uses two
different domains (represented by 'gpio' and 'gpio-ao' sub-nodes in the
DTS) to manage the set of registers on the two buses. This dual-domain
configuration is hardcoded into the driver that strictly requires one
domain for each bus in the same pin controller device.

With this patch we refactor the driver to allow splitting the driver in
two parts. This change is needed to have a proper description of the HW
in the device-tree where we want to introduce aobus and cbus.
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds support for the AmLogic Meson8b SoC.
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Acked-by: NBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch introduces a new PIN macro and few small modifications to
simplify and shorten the Meson pinctrl drivers and cleanup the support
file for the AmLogic Meson8 SoC.
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Acked-by: NBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This is a driver for the pinmux and GPIO controller available in
Amlogic Meson SoCs. It currently supports only Meson8, however the
common code should be generic enough to work also for other SoCs after
having defined the proper set of functions and groups.

GPIO interrupts are not supported at the moment due to lack of
documentation.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>