- 31 5月, 2016 4 次提交
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由 Kevin Hilman 提交于
Add EE domain pins for ethernet interface. Acked-by: NCarlo Caione <carlo@endlessm.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Kevin Hilman 提交于
Add EE domain pins for UART A, B & C. Acked-by: NCarlo Caione <carlo@endlessm.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Kevin Hilman 提交于
Add EE domain pins for eMMC and SD card. Acked-by: NCarlo Caione <carlo@endlessm.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Kevin Hilman 提交于
Add pins for some more AO domain devices: UART_AO_B and I2C master & slave. Acked-by: NCarlo Caione <carlo@endlessm.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 11 5月, 2016 2 次提交
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由 Alexander Müller 提交于
Fix pinctrl eth_tx_en bit index according to Hardkernel ODROID-C1 datasheet. Signed-off-by: NAlexander Müller <serveralex@gmail.com> Acked-by: NCarlo Caione <carlo@endlessm.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Carlo Caione 提交于
This patch adds the basic platform file to support the pin controller found on the Amlogic Meson GXBB SoCs. Signed-off-by: NCarlo Caione <carlo@endlessm.com> Reviewed-by: NKevin Hilman <khilman@baylibre.com> Tested-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 21 4月, 2016 1 次提交
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由 Laxman Dewangan 提交于
Use devm_pinctrl_register() for pin control registration. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Lee Jones <lee.jones@linaro.org> Acked-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 01 4月, 2016 1 次提交
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由 Irina Tirdea 提交于
Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map, since it does not depend on device tree despite the current name. This will enforce a consistent naming in pinctr-utils.c and will make it clear it can be called from outside device tree (e.g. from ACPI handling code). Signed-off-by: NIrina Tirdea <irina.tirdea@intel.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 09 3月, 2016 3 次提交
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由 Carlo Caione 提交于
In the Amlogic Meson8 / Meson8b platforms we have two different buses: cbus and aobus, corresponding to 2 different power domains (regular and always-on). On each bus a different set of registers is mapped to manage muxes, GPIOs and in general to control a clear subset of the pins. Considering this architecture, having two different pinctrl devices, one for each bus / power domain, makes much more sense than just having one single device. Right now we have one single pin controller driver that uses two different domains (represented by 'gpio' and 'gpio-ao' sub-nodes in the DTS) to manage the set of registers on the two buses. This dual-domain configuration is hardcoded into the driver that strictly requires one domain for each bus in the same pin controller device. With this patch we refactor the driver to allow splitting the driver in two parts. This change is needed to have a proper description of the HW in the device-tree where we want to introduce aobus and cbus. Signed-off-by: NCarlo Caione <carlo@endlessm.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Carlo Caione 提交于
Separate functions for pins controlled by different pin controllers. Signed-off-by: NCarlo Caione <carlo@endlessm.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Paul Gortmaker 提交于
The Kconfig currently controlling compilation of this code is: drivers/pinctrl/Kconfig:config PINCTRL_MESON drivers/pinctrl/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modularity so that when reading the driver there is no doubt it is builtin-only. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. We don't replace module.h with init.h since the file already has that. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Antoine Tenart <antoine.tenart@free-electrons.com> Cc: linux-gpio@vger.kernel.org Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 05 1月, 2016 1 次提交
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由 Linus Walleij 提交于
This makes the driver use the data pointer added to the gpio_chip to store a pointer to the state container instead of relying on container_of(). Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 19 11月, 2015 1 次提交
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由 Linus Walleij 提交于
The name .dev in a struct is normally reserved for a struct device that is let us say a superclass to the thing described by the struct. struct gpio_chip stands out by confusingly using a struct device *dev to point to the parent device (such as a platform_device) that represents the hardware. As we want to give gpio_chip:s real devices, this is not working. We need to rename this member to parent. This was done by two coccinelle scripts, I guess it is possible to combine them into one, but I don't know such stuff. They look like this: @@ struct gpio_chip *var; @@ -var->dev +var->parent and: @@ struct gpio_chip var; @@ -var.dev +var.parent and: @@ struct bgpio_chip *var; @@ -var->gc.dev +var->gc.parent Plus a few instances of bgpio that I couldn't figure out how to teach Coccinelle to rewrite. This patch hits all over the place, but I *strongly* prefer this solution to any piecemal approaches that just exercise patch mechanics all over the place. It mainly hits drivers/gpio and drivers/pinctrl which is my own backyard anyway. Cc: Haavard Skinnemoen <hskinnemoen@gmail.com> Cc: Rafał Miłecki <zajec5@gmail.com> Cc: Richard Purdie <rpurdie@rpsys.net> Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Cc: Alek Du <alek.du@intel.com> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Takashi Iwai <tiwai@suse.com> Acked-by: NDmitry Torokhov <dmitry.torokhov@gmail.com> Acked-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: NLee Jones <lee.jones@linaro.org> Acked-by: NJiri Kosina <jkosina@suse.cz> Acked-by: NHans-Christian Egtvedt <egtvedt@samfundet.no> Acked-by: NJacek Anaszewski <j.anaszewski@samsung.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 10 6月, 2015 1 次提交
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由 Masahiro Yamada 提交于
Currently, pinctrl_register() just returns NULL on error, so the callers can not know the exact reason of the failure. Some of the pinctrl drivers return -EINVAL, some -ENODEV, and some -ENOMEM on error of pinctrl_register(), although the error code might be different from the real cause of the error. This commit reworks pinctrl_register() to return the appropriate error code and modifies all of the pinctrl drivers to use IS_ERR() for the error checking and PTR_ERR() for getting the error code. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NPatrice Chotard <patrice.chotard@st.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NHeiko Stuebner <heiko@sntech.de> Tested-by: NMika Westerberg <mika.westerberg@linux.intel.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Acked-by: NLee Jones <lee@kernel.org> Acked-by: NSören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: NRay Jui <rjui@broadcom.com> Acked-by: NAntoine Tenart <antoine.tenart@free-electrons.com> Acked-by: NHongzhou Yang <hongzhou.yang@mediatek.com> Acked-by: NWei Chen <Wei.Chen@csr.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 19 5月, 2015 1 次提交
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由 Carlo Caione 提交于
The num_pins field in the struct meson_domain_data must include also the missing pins in the Meson8b SoC, otherwise the GPIO <-> pin mapping is broken on this platform. Avoid also the dinamic allocation for GPIOs. Signed-off-by: NCarlo Caione <carlo@endlessm.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 07 4月, 2015 3 次提交
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由 Carlo Caione 提交于
This patch adds support for the AmLogic Meson8b SoC. Signed-off-by: NCarlo Caione <carlo@endlessm.com> Acked-by: NBeniamino Galvani <b.galvani@gmail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Carlo Caione 提交于
Add the compatible string for Meson8b in Meson pinctrl documentation and add new information for Meson8b in source code comments. Signed-off-by: NCarlo Caione <carlo@endlessm.com> Acked-by: NBeniamino Galvani <b.galvani@gmail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Carlo Caione 提交于
This patch introduces a new PIN macro and few small modifications to simplify and shorten the Meson pinctrl drivers and cleanup the support file for the AmLogic Meson8 SoC. Signed-off-by: NCarlo Caione <carlo@endlessm.com> Acked-by: NBeniamino Galvani <b.galvani@gmail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 26 1月, 2015 1 次提交
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由 Beniamino Galvani 提交于
This is a driver for the pinmux and GPIO controller available in Amlogic Meson SoCs. It currently supports only Meson8, however the common code should be generic enough to work also for other SoCs after having defined the proper set of functions and groups. GPIO interrupts are not supported at the moment due to lack of documentation. Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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