Initialize the XUSB-related clocks with appropriate parents and rates
for both Tegra114 and Tegra124.
Signed-off-by: NJim Lin <jilin@nvidia.com>
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Currently the Tegra1x4 clock init code hard-codes the mux setting
for xusb_hs_src and treats it as a fixed-factor clock.  It is,
however, a mux which can be parented by either xusb_ss_src/2 or
pll_u_60M.  Add the fixed-factor clock xusb_ss_div2 and put an
entry in periph_clks[] for the xusb_hs_src mux.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The Tegra124 clock driver currently provides 3 clocks that don't actually
exist; 2 for NAND and one for UART5/UARTE. Delete these.

Cc: <stable@vger.kernel.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Tegra124 does not have gr2d and gr3d clocks. They have been replaced by the
vic03 and gpu clocks respectively.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with
6 parents.  Add support for tegra_clk_sdmmc*_8 and switch Tegra114
and Tegra124 to use these clocks instead.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>

The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents.
Change thte id to tegra_clk_host1x_8 so that the correct clock gets
registered.
Signed-off-by: NMark Zhang <markz@nvidia.com>
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>

Set correct pll_d2_out0 divider and correct the p div values for pll_d2.
Signed-off-by: NDavid Ung <davidu@nvidia.com>
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>

PLLD was using the same mnp table as PLLP.  Fix it to use its own
table which is different from PLLP's.
Signed-off-by: NRhyland Klein <rklein@nvidia.com>
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>

This table had settings for 216MHz, but PLLP is (and is supposed to be)
configured at 408MHz.  If that table is used and PLLP_BASE_OVRRIDE is
not set, the kernel will panic in clk_pll_recalc_rate().
Signed-off-by: NGabe Black <gabeblack@google.com>
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>

The Tegra CAR module implements both a clock and reset controller. So
far, the driver exposes the clock feature via the common clock API and
the reset feature using a custom API. This patch adds an implementation
of the common reset framework API (include/linux/reset*.h). The legacy
reset implementation will be removed once all drivers have been
converted.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NThierry Reding <treding@nvidia.com>
Acked-By: NPeter De Schrijver <pdeschrijver@nvidia.com>

This clock is needed to ensure the FUSE registers can be accessed
without freezing the system.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>

Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>

Hook the functions for CPU hotplug support. After the CPU is hot
unplugged, the flow controller will handle to clock gate the CPU clock.
But still need to implement an empty function to avoid warning message.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>

Implement clock support for Tegra124.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>