1. 28 7月, 2015 1 次提交
    • B
      clk: change clk_ops' ->determine_rate() prototype · 0817b62c
      Boris Brezillon 提交于
      Clock rates are stored in an unsigned long field, but ->determine_rate()
      (which returns a rounded rate from a requested one) returns a long
      value (errors are reported using negative error codes), which can lead
      to long overflow if the clock rate exceed 2Ghz.
      
      Change ->determine_rate() prototype to return 0 or an error code, and pass
      a pointer to a clk_rate_request structure containing the expected target
      rate and the rate constraints imposed by clk users.
      
      The clk_rate_request structure might be extended in the future to contain
      other kind of constraints like the rounding policy, the maximum clock
      inaccuracy or other things that are not yet supported by the CCF
      (power consumption constraints ?).
      Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
      CC: Jonathan Corbet <corbet@lwn.net>
      CC: Tony Lindgren <tony@atomide.com>
      CC: Ralf Baechle <ralf@linux-mips.org>
      CC: "Emilio López" <emilio@elopez.com.ar>
      CC: Maxime Ripard <maxime.ripard@free-electrons.com>
      Acked-by: NTero Kristo <t-kristo@ti.com>
      CC: Peter De Schrijver <pdeschrijver@nvidia.com>
      CC: Prashant Gaikwad <pgaikwad@nvidia.com>
      CC: Stephen Warren <swarren@wwwdotorg.org>
      CC: Thierry Reding <thierry.reding@gmail.com>
      CC: Alexandre Courbot <gnurou@gmail.com>
      CC: linux-doc@vger.kernel.org
      CC: linux-kernel@vger.kernel.org
      CC: linux-arm-kernel@lists.infradead.org
      CC: linux-omap@vger.kernel.org
      CC: linux-mips@linux-mips.org
      CC: linux-tegra@vger.kernel.org
      [sboyd@codeaurora.org: Fix parent dereference problem in
      __clk_determine_rate()]
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      Tested-by: NRomain Perier <romain.perier@gmail.com>
      Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
      [sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate
      clocks without parents or a rate determining op]
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      0817b62c
  2. 07 7月, 2015 1 次提交
  3. 09 4月, 2015 1 次提交
  4. 24 3月, 2015 3 次提交
    • G
      clk: qcom: Introduce parent_map tables · 293d2e97
      Georgi Djakov 提交于
      In the current parent mapping code, we can get duplicate or inconsistent
      indexes, which leads to discrepancy between the number of elements in the
      array and the number of parents. Until now, this was solved with some
      reordering but this is not always possible.
      
      This patch introduces index tables that are used to define the relations
      between the PLL source and the hardware mux configuration value.
      To accomplish this, here we do the following:
       - Define a parent_map struct to map the relations between PLL source index
       and register configuration value.
       - Add a qcom_find_src_index() function for finding the index of a clock
       matching the specific PLL configuration.
       - Update the {set,get}_parent RCG functions use the newly introduced
       parent_map struct.
       - Convert all existing drivers to the new parent_map tables.
      Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      293d2e97
    • G
      clk: qcom: Fix clk_get_parent function return value · 7f218978
      Georgi Djakov 提交于
      According to the common clock framework API, the clk_get_parent() function
      should return u8. Currently we are returning negative values on error. Fix
      this and use the default parent in case of an error.
      Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      7f218978
    • A
      clk: qcom: fix RCG M/N counter configuration · 0b21503d
      Archit Taneja 提交于
      Currently, a RCG's M/N counter (used for fraction division) is
      set to either 'bypass' (counter disabled) or 'dual edge' (counter
      enabled) based on whether the corresponding rcg struct has a mnd
      field specified and a non-zero N.
      
      In the case where M and N are the same value, the M/N counter is
      still enabled by code even though no division takes place.
      Leaving the RCG in such a state can result in improper behavior.
      This was observed with the DSI pixel clock RCG when M and N were
      both set to 1.
      
      Add an additional check (M != N) to enable the M/N counter only
      when it's needed for fraction division.
      Signed-off-by: NArchit Taneja <architt@codeaurora.org>
      Fixes: bcd61c0f (clk: qcom: Add support for root clock
      generators (RCGs))
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      0b21503d
  5. 03 2月, 2015 1 次提交
  6. 04 12月, 2014 1 次提交
  7. 23 9月, 2014 1 次提交
  8. 30 5月, 2014 3 次提交
  9. 17 1月, 2014 1 次提交