- 28 7月, 2015 2 次提交
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由 Boris Brezillon 提交于
Some determine_rate implementations are not returning an error when they failed to adapt the rate according to the rate request. Fix them so that they return an error instead of silently returning 0. Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> CC: Jonathan Corbet <corbet@lwn.net> CC: Tony Lindgren <tony@atomide.com> CC: Ralf Baechle <ralf@linux-mips.org> CC: "Emilio López" <emilio@elopez.com.ar> CC: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Tero Kristo <t-kristo@ti.com> CC: Peter De Schrijver <pdeschrijver@nvidia.com> CC: Prashant Gaikwad <pgaikwad@nvidia.com> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Thierry Reding <thierry.reding@gmail.com> CC: Alexandre Courbot <gnurou@gmail.com> CC: linux-doc@vger.kernel.org CC: linux-kernel@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-omap@vger.kernel.org CC: linux-mips@linux-mips.org CC: linux-tegra@vger.kernel.org Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Boris Brezillon 提交于
Clock rates are stored in an unsigned long field, but ->determine_rate() (which returns a rounded rate from a requested one) returns a long value (errors are reported using negative error codes), which can lead to long overflow if the clock rate exceed 2Ghz. Change ->determine_rate() prototype to return 0 or an error code, and pass a pointer to a clk_rate_request structure containing the expected target rate and the rate constraints imposed by clk users. The clk_rate_request structure might be extended in the future to contain other kind of constraints like the rounding policy, the maximum clock inaccuracy or other things that are not yet supported by the CCF (power consumption constraints ?). Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> CC: Jonathan Corbet <corbet@lwn.net> CC: Tony Lindgren <tony@atomide.com> CC: Ralf Baechle <ralf@linux-mips.org> CC: "Emilio López" <emilio@elopez.com.ar> CC: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: NTero Kristo <t-kristo@ti.com> CC: Peter De Schrijver <pdeschrijver@nvidia.com> CC: Prashant Gaikwad <pgaikwad@nvidia.com> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Thierry Reding <thierry.reding@gmail.com> CC: Alexandre Courbot <gnurou@gmail.com> CC: linux-doc@vger.kernel.org CC: linux-kernel@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-omap@vger.kernel.org CC: linux-mips@linux-mips.org CC: linux-tegra@vger.kernel.org [sboyd@codeaurora.org: Fix parent dereference problem in __clk_determine_rate()] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Tested-by: NRomain Perier <romain.perier@gmail.com> Signed-off-by: NHeiko Stuebner <heiko@sntech.de> [sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate clocks without parents or a rate determining op] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 14 7月, 2015 1 次提交
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由 Stephen Boyd 提交于
The error paths in this file leak memory and mappings and test for pointers being valid after dereferencing them. Fix these problems and properly free resources on errors. Fix some stylistic things too like using sizeof(*ptr) and fitting more code on a single line. Note that we don't unregister clocks here. That needs a clk_composite_unregister() API that we don't have right now. Acked-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Cc: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 08 7月, 2015 5 次提交
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由 Stephen Boyd 提交于
The list isn't used after of_clk_init() is called, so we don't need to keep an empty list around after init. Put the list on the stack. Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Stephen Boyd 提交于
Dan Carpenter reports that we don't check the allocation here for failure. Add a failure check and free any previously allocated providers from the clk_provider_list. Reported-by: NDan Carpenter <dan.carpenter@oracle.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Georgi Djakov 提交于
Add support for SR2 type pll operations. SR2 is optimized for Time Interval Error (TIE) or absolute jitter. Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Stephen Boyd 提交于
Remove useless ifdefs around function prototypes to silence the following sparse warnings when the configs aren't enabled. drivers/clk/at91/clk-h32mx.c:95:13: warning: symbol 'of_sama5d4_clk_h32mx_setup' was not declared. Should it be static? drivers/clk/at91/clk-utmi.c:159:13: warning: symbol 'of_at91sam9x5_clk_utmi_setup' was not declared. Should it be static? Plus, using __init and extern in function prototypes doesn't do anything, so just drop it throughout this file. Acked-by: NBoris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Pankaj Dev 提交于
Incorrect register offset used for sthi407 clockgenC Signed-off-by: NPankaj Dev <pankaj.dev@st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Fixes: 51306d56 ("clk: st: STiH407: Support for clockgenC0") Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 07 7月, 2015 21 次提交
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由 Georgi Djakov 提交于
Make const both the array and the strings, so they can be moved to .rodata section. Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Matthias Brugger 提交于
X-Gene clocks implement it's name in the clock private struct. This is a duplication of the name field. We can delete the field and rely on the common implementation to retrieve the name. Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Sergej Sawazki 提交于
The file clk-gpio-gate.c does not only contain the gate clock, but also the mux clock. Rename the file to clk-gpio.c. Cc: Jyri Sarha <jsarha@ti.com> Signed-off-by: NSergej Sawazki <ce3a@gmx.de> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Sergej Sawazki 提交于
Add a common clock driver for basic gpio controlled clock multiplexers. This driver can be used for devices like 5V41068A or 831721I from IDT or for discrete multiplexer circuits. The 'select' pin selects one of two parent clocks. Cc: Jyri Sarha <jsarha@ti.com> Signed-off-by: NSergej Sawazki <ce3a@gmx.de> [sboyd@codeaurora.org: Fix error paths to free memory and do it in the correct order] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Sergej Sawazki 提交于
Do not output an error message if requesting gpio failes with EPROBE_DEFER. Cc: Jyri Sarha <jsarha@ti.com> Signed-off-by: NSergej Sawazki <ce3a@gmx.de> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Sergej Sawazki 提交于
Include export.h for EXPORT_SYMBOL_GPL, no need to include module.h. Cc: Jyri Sarha <jsarha@ti.com> Signed-off-by: NSergej Sawazki <ce3a@gmx.de> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Sascha Hauer 提交于
On the MT8173 the clocks are provided by different units. To enable the critical clocks we must be sure that all parent clocks are already registered, otherwise the parents of the critical clocks end up being unused and get disabled later. To find a place where all parents are registered we try each time after we've registered some clocks if all known providers are present now and only then we enable the critical clocks Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com> [sboyd@codeaurora.org: Marked function and data __init] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Heiko Stuebner 提交于
Describe the clock tree and software resets of the rk3368 ARM64 SoC Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Heiko Stuebner 提交于
Both soc series' have inverters on the hsadc and camera interface clock paths. So define them using the newly added inverter type. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Heiko Stuebner 提交于
The review for the new inverter clock type uncovered some issues (missing headers and name handling) that are also present in the mmc-phase clock type, I got (to much) inspiration from. Fix these there too. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Heiko Stuebner 提交于
Most Rockchip socs have optional phase inverters connected to some clocks that move the clock-phase by 180 degrees. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> [sboyd@codeaurora.org: Dropped lazy part of commit text] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Heiko Stuebner 提交于
A clock branch consisting of a mux and divider with non-standard divider values. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Heiko Stuebner 提交于
The macros calculate the correct offset from the id in the parameter. If this parameter does not consist of a single number, the calculation will return wrong registers in the best case or create unaligned accesses in the worst case. So protect the calculations against such values. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Heiko Stuebner 提交于
The video input processor (vip) was called camera interface (cif) on older socs which seems to have resulted in a copy'n'paste error when creating the rk3288 camera clocks. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Heiko Stuebner 提交于
The dwmac ethernet controller on the rk3288 supports phys connected via rgmii and rmii. With rgmii phys it is expected that the mac clock is provided externally while with rmii phys the clock can be external but also generated from the plls. In the later case it of course needs be at 50MHz, which gets set from the dwmac_rk driver. As most devices use a rgmii phy it never surfaced so far that the mac clk mux, doesn't go up one lever to the pll clock in the rmii case with internal clock generation, as it is missing the CLK_SET_RATE_PARENT flag, and thus will not set the correct frequency in most cases. Fixes: b9e4ba54 ("clk: rockchip: add clock controller for rk3288") Cc: stable@vger.kernel.org Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Gabriel Fernandez 提交于
This patch fixes the mux bit-setting for ClockgenA9. Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Fixes: 13e6f2da ("clk: st: STiH407: Support for A9 MUX Clocks") Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Pankaj Dev 提交于
Add the CLK_GET_RATE_NOCACHE flag to all the clocks with recalc ops, so that they reflect Hw rate after CPS wake-up when a clk_get_rate() is called Signed-off-by: NPankaj Dev <pankaj.dev@st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Giuseppe Cavallaro 提交于
While proving lock, the following warning happens and it is fixed after initializing lock in the setup function INFO: trying to register non-static key. the code is fine but needs lockdep annotation. turning off the locking correctness validator. CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.27-02861-g39df285-dirty #33 [<c00154ac>] (unwind_backtrace+0x0/0xf4) from [<c0011b50>] (show_stack+0x10/0x14) [<c0011b50>] (show_stack+0x10/0x14) from [<c00689ac>] (__lock_acquire+0x900/0xb14) [<c00689ac>] (__lock_acquire+0x900/0xb14) from [<c0069394>] (lock_acquire+0x68/0x7c) [<c0069394>] (lock_acquire+0x68/0x7c) from [<c04958f8>] (_raw_spin_lock_irqsave+0x48/0x5c) [<c04958f8>] (_raw_spin_lock_irqsave+0x48/0x5c) from [<c0381e6c>] (clk_gate_endisable+0x28/0x88) [<c0381e6c>] (clk_gate_endisable+0x28/0x88) from [<c0381ee0>] (clk_gate_enable+0xc/0x14) [<c0381ee0>] (clk_gate_enable+0xc/0x14) from [<c0386c68>] (flexgen_enable+0x28/0x40) [<c0386c68>] (flexgen_enable+0x28/0x40) from [<c037f260>] (__clk_enable+0x5c/0x9c) [<c037f260>] (__clk_enable+0x5c/0x9c) from [<c037f558>] (clk_enable+0x18/0x2c) [<c037f558>] (clk_enable+0x18/0x2c) from [<c064a1dc>] (st_lpc_of_register+0xc0/0x248) [<c064a1dc>] (st_lpc_of_register+0xc0/0x248) from [<c0649e44>] (clocksource_of_init+0x34/0x58) [<c0649e44>] (clocksource_of_init+0x34/0x58) from [<c0637ddc>] (sti_timer_init+0x10/0x18) [<c0637ddc>] (sti_timer_init+0x10/0x18) from [<c06343f8>] (time_init+0x20/0x30) [<c06343f8>] (time_init+0x20/0x30) from [<c0632984>] (start_kernel+0x20c/0x2e8) [<c0632984>] (start_kernel+0x20c/0x2e8) from [<40008074>] (0x40008074) Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Fixes: b1165170 ("clk: st: STiH407: Support for Flexgen Clocks") Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Gabriel Fernandez 提交于
This patch fixes the value for disabling the FSYN channel clock. The 'is_enabled' returned value is also fixed. Signed-off-by: NPankaj Dev <pankaj.dev@st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Gabriel Fernandez 提交于
Remove this duplicated code due to a bad copy / paste. Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Hai Li 提交于
Since the parent rate has been recalculated, pixel RCG clock should rely on it to find the correct M/N values during set_rate, instead of calling __clk_round_rate() to its parent again. Signed-off-by: NHai Li <hali@codeaurora.org> Tested-by: NArchit Taneja <architt@codeaurora.org> Fixes: 99cbd064 ("clk: qcom: Support display RCG clocks") [sboyd@codeaurora.org: Silenced unused parent variable warning] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 03 7月, 2015 4 次提交
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由 David Dueck 提交于
Do not leak memory and free irqs in case of an error. Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: NDavid Dueck <davidcdueck@googlemail.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Daniel Thompson 提交于
If stm32f4_rcc_lookup() is called with primary == 0 and secondary == 192 then it will read beyond the end of the table array due to an out-by-one error in the range check. In addition to the fixing the inequality we also modify the r.h.s. to make it even more explicit that we are comparing against the size of table in bits. Reported-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NDaniel Thompson <daniel.thompson@linaro.org> Acked-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com> Fixes: 358bdf89 ("clk: stm32: Add clock driver for STM32F4[23]xxx devices") Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Ray Jui 提交于
A 32-bit variable should be type casted to 64-bit before arithmetic operation and assigning it to a 64-bit variable Reported-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NRay Jui <rjui@broadcom.com> Fixes: 5fe225c1 ("clk: iproc: add initial common clock support") Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Ray Jui 提交于
of_property_read_string_index takes array of pointers and assign them to strings read from device tree property. No additional memory allocation is needed prior to calling of_property_read_string_index. In fact, since the array of pointers will be re-assigned to other strings, any memory that it points to prior to calling of_property_read_string_index will be leaked Reported-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NRay Jui <rjui@broadcom.com> Fixes: 5fe225c1 ("clk: iproc: add initial common clock support") Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 23 6月, 2015 3 次提交
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由 Dan Carpenter 提交于
The error handling was a bit messy and buggy. It freed "pll_clock" then dereferenced it, and then freed it again. I've re-written it in normal kernel style. Fixes: 42ff8e8008c8 ('h8300: clock driver') Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
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由 Yoshinori Sato 提交于
Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>
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由 Daniel Thompson 提交于
The driver supports decoding and statically modelling PLL state (i.e. we inherit state from bootloader) and provides support for all peripherals that support simple one-bit gated clocks. The covers all peripherals whose clocks come from the AHB, APB1 or APB2 buses. It has been tested on an STM32F429I-Discovery board. The clock counts for TIM2, USART1 and SYSTICK are all set correctly and the wall clock looks OK when checked with a stopwatch. I have also tested a prototype driver for the RNG hardware. The RNG clock is correctly enabled by the framework (also did inverse test and proved that by changing DT to configure the wrong clock bit then we observe the RNG driver to fail). Signed-off-by: NDaniel Thompson <daniel.thompson@linaro.org> Reviewed-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com> [sboyd@codeaurora.org: Silence sparse warnings] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 22 6月, 2015 4 次提交
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由 Huacai Chen 提交于
Currently, code of Loongson-2/3 is under loongson directory and code of Loongson-1 is under loongson1 directory. Besides, there are Kconfig options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is very ugly and confusing. Since Loongson-2/3 are both 64-bit general- purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names and Kconfig symbols from loongson/loongson1 to loongson64/loongson32. [ralf@linux-mips.org: Resolve a number of simple conflicts.] Signed-off-by: NHuacai Chen <chenhc@lemote.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/9790/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Paul Burton 提交于
Add support for the clocks provided by the CGU in the Ingenic JZ4780 SoC, making use of the SoC-agnostic CGU code to do the heavy lifting. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Co-authored-by: NPaul Cercueil <paul@crapouillou.net> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10157/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Paul Burton 提交于
The jz4740-cgu driver already has access to the CGU, so it makes sense to move the few remaining accesses to the CGU from arch/mips/jz4740 there too. Move the jz4740_clock_{suspend,resume} functions there for such consistency. The arch/mips/jz4740/clock.c file now contains nothing more of use & so is removed. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10158/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Paul Burton 提交于
The jz4740-cgu driver already has access to the CGU, so it makes sense to move the few remaining accesses to the CGU from arch/mips/jz4740 there too. Move the jz4740_clock_udc_{dis,en}able_auto_suspend functions there for such consistency. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10154/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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