1. 28 7月, 2015 1 次提交
    • B
      clk: change clk_ops' ->determine_rate() prototype · 0817b62c
      Boris Brezillon 提交于
      Clock rates are stored in an unsigned long field, but ->determine_rate()
      (which returns a rounded rate from a requested one) returns a long
      value (errors are reported using negative error codes), which can lead
      to long overflow if the clock rate exceed 2Ghz.
      
      Change ->determine_rate() prototype to return 0 or an error code, and pass
      a pointer to a clk_rate_request structure containing the expected target
      rate and the rate constraints imposed by clk users.
      
      The clk_rate_request structure might be extended in the future to contain
      other kind of constraints like the rounding policy, the maximum clock
      inaccuracy or other things that are not yet supported by the CCF
      (power consumption constraints ?).
      Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
      CC: Jonathan Corbet <corbet@lwn.net>
      CC: Tony Lindgren <tony@atomide.com>
      CC: Ralf Baechle <ralf@linux-mips.org>
      CC: "Emilio López" <emilio@elopez.com.ar>
      CC: Maxime Ripard <maxime.ripard@free-electrons.com>
      Acked-by: NTero Kristo <t-kristo@ti.com>
      CC: Peter De Schrijver <pdeschrijver@nvidia.com>
      CC: Prashant Gaikwad <pgaikwad@nvidia.com>
      CC: Stephen Warren <swarren@wwwdotorg.org>
      CC: Thierry Reding <thierry.reding@gmail.com>
      CC: Alexandre Courbot <gnurou@gmail.com>
      CC: linux-doc@vger.kernel.org
      CC: linux-kernel@vger.kernel.org
      CC: linux-arm-kernel@lists.infradead.org
      CC: linux-omap@vger.kernel.org
      CC: linux-mips@linux-mips.org
      CC: linux-tegra@vger.kernel.org
      [sboyd@codeaurora.org: Fix parent dereference problem in
      __clk_determine_rate()]
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      Tested-by: NRomain Perier <romain.perier@gmail.com>
      Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
      [sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate
      clocks without parents or a rate determining op]
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      0817b62c
  2. 15 5月, 2015 1 次提交
  3. 17 4月, 2015 1 次提交
  4. 03 2月, 2015 1 次提交
  5. 04 12月, 2014 1 次提交
  6. 28 5月, 2014 1 次提交
    • A
      clk: bcm/kona: implement determine_rate() · c2152d0e
      Alex Elder 提交于
      Implement the clk->determine_rate method for Broadcom Kona peripheral
      clocks.  This allows a peripheral clock to be re-parented in order to
      satisfy a rate change request.  This takes the place of the previous
      kona_peri_clk_round_rate() functionality, though that function remains
      because it is used by the new one.
      
      The parent clock that allows the peripheral clock to produce a rate
      closest to the one requested is the one selected, though the current
      parent is used by default.
      Signed-off-by: NAlex Elder <elder@linaro.org>
      Signed-off-by: NMike Turquette <mturquette@linaro.org>
      c2152d0e
  7. 01 5月, 2014 6 次提交
  8. 25 2月, 2014 1 次提交
    • A
      clk: bcm281xx: add initial clock framework support · 1f27f152
      Alex Elder 提交于
      Add code for device tree support of clocks in the BCM281xx family of
      SoCs.  Machines in this family use peripheral clocks implemented by
      "Kona" clock control units (CCUs).  (Other Broadcom SoC families use
      Kona style CCUs as well, but support for them is not yet upstream.)
      
      A BCM281xx SoC has multiple CCUs, each of which manages a set of
      clocks on the SoC.  A Kona peripheral clock is composite clock that
      may include a gate, a parent clock multiplexor, and zero, one
      or two dividers.  There is a variety of gate types, and many gates
      implement hardware-managed gating (often called "auto-gating").
      Most dividers divide their input clock signal by an integer value
      (one or more).  There are also "fractional" dividers which allow
      division by non-integer values.  To accomodate such dividers,
      clock rates and dividers are generally maintained by the code in
      "scaled" form, which allows integer and fractional dividers to
      be handled in a uniform way.
      
      If present, the gate for a Kona peripheral clock must be enabled
      when a change is made to its multiplexor or one of its dividers.
      Additionally, dividers and multiplexors have trigger registers which
      must be used whenever the divider value or selected parent clock is
      changed.  The same trigger is often used for a divider and
      multiplexor, and a BCM281xx peripheral clock occasionally has two
      triggers.
      
      The gate, dividers, and parent clock selector are treated in this
      code as "components" of a peripheral clock.  Their functionality is
      implemented directly--e.g. the common clock framework gate
      implementation is not used for a Kona peripheral clock gate.  (This
      has being considered though, and the intention is to evolve this
      code to leverage common code as much as possible.)
      
      The source code is divided into three general portions:
      
          drivers/clk/bcm/clk-kona.h
          drivers/clk/bcm/clk-kona.c
              These implement the basic Kona clock functionality,
              including the clk_ops methods and various routines to
              manipulate registers and interpret their values.  This
              includes some functions used to set clocks to a desired
              initial state (though this feature is only partially
              implemented here).
      
          drivers/clk/bcm/clk-kona-setup.c
              This contains generic run-time initialization code for
              data structures representing Kona CCUs and clocks.  This
              encapsulates the clock structure initialization that can't
              be done statically.  Note that there is a great deal of
              validity-checking code here, making explicit certain
              assumptions in the code.   This is mostly useful for adding
              new clock definitions and could possibly be disabled for
              production use.
      
          drivers/clk/bcm/clk-bcm281xx.c
              This file defines the specific CCUs used by BCM281XX family
              SoCs, as well as the specific clocks implemented by each.
              It declares a device tree clock match entry for each CCU
              defined.
      
          include/dt-bindings/clock/bcm281xx.h
              This file defines the selector (index) values used to
              identify a particular clock provided by a CCU.  It consists
              entirely of C preprocessor constants, to be used by both the
              C source and device tree source files.
      Signed-off-by: NAlex Elder <elder@linaro.org>
      Reviewed-by: NTim Kryger <tim.kryger@linaro.org>
      Reviewed-by: NMatt Porter <mporter@linaro.org>
      Acked-by: NMike Turquette <mturquette@linaro.org>
      Signed-off-by: NMatt Porter <mporter@linaro.org>
      1f27f152