While adding clock support for Exynos5260, the infrastructure to
register multiple clock controllers was introduced. Factor out the
support for registering multiple clock controller from Exynos5260
clock code to common samsung clock code so that it can be used by
other Exynos SoC which have multiple clock controllers.
Signed-off-by: NNaveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: NThomas Abraham <thomas.ab@samsung.com>
Tested-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

PLL145xx is similar to PLL35xx and PLL1460x is almost similar
to PLL46xx with minor differences in bit positions. Hence,
reuse the functions defined for pll_35xx and pll_46xx to
support 145xx and 1460x PLLs respectively.
Signed-off-by: NNaveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: NThomas Abraham <thomas.ab@samsung.com>
Tested-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This patch adds clock driver of Exynos4415 SoC based on Cortex-A9 using
common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked Loops) and generates system clocks for CPU,
busses and function clocks for individual IPs.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NSeung-Woo Kim <sw0312.kim@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

S3C2412, S3C2443 and their derivatives contain a special software-reset
register in their system-controller.

Therefore register a restart handler for those.

Tested on a s3c2416-based board, s3c2412 compile-tested.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>

There is no need to init .owner field.

Based on the patch from Peter Griffin <peter.griffin@linaro.org>
"mmc: remove .owner field for drivers using module_platform_driver"

This patch removes the superflous .owner field for drivers which
use the module_platform_driver API, as this is overriden in
platform_driver_register anyway."
Signed-off-by: NKiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The 'div_core2' clock and the 'arm_clk' divider clocks are instances of
the same divider clock. So remove the 'arm_clk' clock instance.
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
[tomasz.figa@gmail.com: Fixed remaining occurences of 'arm_clk'.]
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>

sclk_g3d clock doesn't have enable/disable bits, but the driver hijacked
g3d gate clock bits for this purpose and didn't provide real g3d clock
at all. This patch fixes this issue by adding proper definition for g3d
clock and removing incorrect access to GATE_IP_G3D register in sclk_g3d.
In addition CLK_SET_RATE_PARENT flag is dropped from sclk_g3d, because
it does not make any sense and most likely has been added by mistake.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
[tomasz.figa@gmail.com: Adjusted commit message.]
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>

This patch adds support for exporting mout_hdmi and mout_mixer to device
tree. Access to those clocks is required to correctly setup HDMI module
on Exynos 4210 and 4x12 SoCs.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
CC: Mike Turquette <mturquette@linaro.org>
CC: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>

This patch adds missing smmu_g2d clock implementation and updates
comment about Exynos4 clocks from 278-282 range. Those clocks are
available on all Exynos4 SoC series, so the misleading comment has been
removed.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>

Add clock provider for clocks in DMC domain including EPLL and BPLL. The
DMC clocks are necessary for Exynos3 devfreq driver.

The DMC clock domain uses different address space (0x105C0000) than
standard clock domain (0x10030000 - 0x10050000). The difference is huge
enough to add new DT node for the clock provider, rather than extending
existing address space.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>

The parent name added in parent list as
mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, is different
than the defined parent due to typo.
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: NChander Kashyap <k.chander@samsung.com>
Signed-off-by: NPankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>

As per Exynos3250 user manual mmc0/1 mux selection has 4 bit wide.
Signed-off-by: NPankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>

Update shift and width field of div_spi0_isp clock as per Exynos3250
user manual.
Signed-off-by: NPankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>

As per user manual of Exynos3250 SRC_CAM can select
div_cam_blk_320 if it's value is 0xC, so placing
div_cam_blk_320 at proper index in parent list of mout_cam_blk.
Signed-off-by: NPankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>

Register the PLL configuration data for APLL and KPLL on Exynos5420. This
configuration data table specifies PLL coefficients for supported PLL
clock speeds when a 24MHz clock is supplied as the input clock source
for these PLLs.

Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Reviewed-by: NAmit Daniel Kachhap <amit.daniel@samsung.com>
Tested-by: NArjun K.V <arjun.kv@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Prior to suspending the system, we need to ensure that certain
clock source and gate registers are unmasked.

while at it, add these clks to save/restore list also.
Signed-off-by: NVikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Array of struct of_device_id may be be const as expected by
of_match_table field and of_find_matching_node_and_match() function.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Enable ARMCLK down feature on Exynos3250 SoC. The frequency of
ARMCLK will be reduced upon entering idle mode (WFI or WFE).

The feature behaves like very fast cpufreq ondemand governor.

The patch uses simillar settings as Exynos5250 (clk-exynos5250.c),
except it disables clock up feature.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Enable ARMCLK down feature on all Exynos4 SoCs. The frequency of
ARMCLK will be reduced upon entering idle mode (WFI or WFE).

The feature behaves like very fast cpufreq ondemand governor. In idle
mode this reduces energy consumption on full frequency chosen by
cpufreq governor by approximately:
 - Trats2:  6.5% (153 mA -> 143 mA)
 - Trats:  33.0% (180 mA -> 120 mA)
 - Gear1:  27.0% (180 mA -> 130 mA)

The patch uses simillar settings as Exynos5250 (clk-exynos5250.c),
except it disables clock up feature and on Exynos4412 ARMCLK down is
enabled for all 4 cores.

Tested on Trats board (Exynos4210), Trats2 board (Exynos4412) and
Samsung Gear 1 (Exynos4212).
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: NDaniel Drake <drake@endlessm.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch introduces a driver that handles configuration of CLKOUT pin
of Exynos SoCs that can be used to output certain clocks from inside of
the SoC to a dedicated output pin.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds definitions of clocks that are used to drive clock
output signals of particular CMU sub-blocks that are then fed to PMU and
handled by Exynos CLKOUT driver added in further patch.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds missing definitions of clocks from CPU and DMC clock
domains, which are necessary to properly represent CLKOUT clock hierarchy
added in further patch.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Since there is no more support for board files, this patch removes
legacy non-DT support from the clock driver as well, including
unnecessary clkdev aliases.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds a driver for clock controller being a part of Audio
Subsystem present on S5PV210 and compatible SoCs. It is used to provide
clocks for other IP blocks of this subsystem.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds new, Common Clock Framework-based clock driver for Samsung
S5PV210 and compatible SoCs. The driver is just added, without enabling it yet.
Signed-off-by: NMateusz Krawczuk <m.krawczuk@partner.samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
[t.figa: Added support for other SoC variants and clock output. Fixed
remaining minor issues.]
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Adds IDs for MUX clocks to be used by power domain for MFC
for doing re-parenting while pd on/off.
Signed-off-by: NArun Kumar K <arun.kk@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Exynos4 has saveral PPMUs and each of them has operation clock which
can be gated through CMU's SFR control.

New clocks are listed below. All clocks are added as a gate-typed clock.

CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L,
CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1,
CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU,
CLK_PPMUACP,
Signed-off-by: NJonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NMyungjoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Ensure the clock provider is not registered until after all its related
clocks were created and are ready to use. Currently there are races
possible and any (of_)clk_get() call right after a clock provider's
clk_init_cb callback call may fail.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The "aclk66_peric" clock is a gate clock with a whole bunch of gates
underneath it.  This big gate isn't very useful to include in our
clock tree.  If any of the children need to be turned on then the big
gate will need to be on anyway.  ...and there are plenty of other "big
gates" that aren't described in our clock tree, some of which shut off
collections of clocks that have no relationship in the hierarchy so
are hard to model.

"aclk66_peric" is causing earlyprintk problems since it gets disabled
as part of the boot process, so let's just remove it.

Strangely (and for no good reason) this clock is exported as part of
the common clock bindings.  Remove it since there are no in-kernel
device trees using it and no reason anyone out of tree should refer to
it either.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Change bit from 2 to 9 for tv (mixer) sysmmu clock.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Reviewed-by: NSachin Kamat <sachin.kamat@samsung.com>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

In the move to this clock driver the hookups for the SPI clocks were
dropped, which causes my system Cragganmore (s3c6410 based) to be unable
to locate any spibus clocks. This patch adds them back in.

When taking the clock from the epll clock (SCLK) the rates on the SPI
bus are incorrect, this needs further debugging but the hookup here
should be correct and the problem should be else where.

The USBCLK case has been dropped because this requires the USB PHY to be
enabled.
Signed-off-by: NCharles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

ISP special clocks have dedicated gating registers and so MUX SRC_MASK
register should not be used. This patch fixes the problem of
Exynos4x12-based boards freezing on system suspend, because those
mux outputs need not to be masked while suspending.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Cc: Mike Turquette <mturquette@linaro.org>

Without these aliases clock lookup fails in s3c2410fb,
s3cmci, s3c2410-nand, s3c24xx-i2s, and i2c-s3c2410 drivers.
Signed-off-by: NVasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

There's a several typos in a driver: 2410 instead of S3C2410
and wrong argument to ARRAY_SIZE(). They prevent s3c2410
from properly booting.
Signed-off-by: NVasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: NTarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: NVyacheslav Tyrtov <v.tyrtov@samsung.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Fixes the following warning:
WARNING: drivers/built-in.o(.text.unlikely+0x2c50): Section mismatch in reference from the function exynos4_clk_sleep_init() to the (unknown reference) .init.data:(unknown)
   The function exynos4_clk_sleep_init() references
   the (unknown reference) __initdata (unknown).
   This is often because exynos4_clk_sleep_init lacks a __initdata
   annotation or the annotation of (unknown) is wrong.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Reported-by: Nkbuild test robot <fengguang.wu@intel.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

"clk: samsung: clk-s3c2410-dlck: do not use PNAME macro as it declares
__initdata" had a typo in it which caused build failure. Trivial fix.
Signed-off-by: NOlof Johansson <olof@lixom.net>

The originally used PNAME macro from the core samsung clock infrastructure
declares the created array as initdata, creating section mismatch warnings
in the dclk driver.

Thus declare them directly, removing these warning.
Reported-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch adds the missing sysmmu clocks for Display and
ISP blocks.
Signed-off-by: NCho KyongHo <pullip.cho@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Now with common clock support added for exynos5250 it is necessary to
move this code to exynos5250 common clock driver as clock registers
should be handled there. This change is tested in exynos5250 based
arndale platform.

Cc: Abhilash Kesavan <a.kesavan@samsung.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsugn.com>
Reviewed-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: NAmit Daniel Kachhap <amit.daniel@samsung.com>
[t.figa: Rebased onto current kernel sources.]
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>