- 31 10月, 2014 3 次提交
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由 Naveen Krishna Ch 提交于
While adding clock support for Exynos5260, the infrastructure to register multiple clock controllers was introduced. Factor out the support for registering multiple clock controller from Exynos5260 clock code to common samsung clock code so that it can be used by other Exynos SoC which have multiple clock controllers. Signed-off-by: NNaveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com> Reviewed-by: NThomas Abraham <thomas.ab@samsung.com> Tested-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Naveen Krishna Ch 提交于
PLL145xx is similar to PLL35xx and PLL1460x is almost similar to PLL46xx with minor differences in bit positions. Hence, reuse the functions defined for pll_35xx and pll_46xx to support 145xx and 1460x PLLs respectively. Signed-off-by: NNaveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com> Reviewed-by: NThomas Abraham <thomas.ab@samsung.com> Tested-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds clock driver of Exynos4415 SoC based on Cortex-A9 using common clock framework. The CMU (Clock Management Unit) of Exynos4415 controls PLLs(Phase Locked Loops) and generates system clocks for CPU, busses and function clocks for individual IPs. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com> Signed-off-by: NSeung-Woo Kim <sw0312.kim@samsung.com> Acked-by: NKyungmin Park <kyungmin.park@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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- 14 10月, 2014 1 次提交
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由 Chris Zhong 提交于
This is the initial version of the RK808 PMIC. This is a power management IC for multimedia products. It provides regulators that are able to supply power to processor cores and other components. The chip provides other modules including RTC, Clockout. Signed-off-by: NChris Zhong <zyw@rock-chips.com> Reviewed-by: NDoug Anderson <dianders@chromium.org> Tested-by: NDoug Anderson <dianders@chromium.org> Tested-by: NHeiko Stuebner <heiko@sntech.de> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Samuel Ortiz <sameo@linux.intel.com> says: Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Olof Johansson <olof@lixom.net> Cc: Dmitry Torokhov <dtor@chromium.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Li Zhong <zhong@linux.vnet.ibm.com> Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 06 10月, 2014 1 次提交
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由 Robert Jarzmik 提交于
Fix the building of pxa clock drivers so that the files are actually compiled if and only if COMMON_CLK was selected by the architecture. This prevents conflicts with mach-pxa clock legacy implementation. Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 02 10月, 2014 1 次提交
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由 Masahiro Yamada 提交于
In these Makefiles, at least one of "obj-y" and "obj-" is non-empty, hence built-in.o is always created without such a trick. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: NPeter Foley <pefoley2@pefoley.com> Acked-by: NMike Turquette <mturquette@linaro.org> Acked-by: Simon Horman <horms+renesas@verge.net.au> [shmobile] Acked-by: David S. Miller <davem@davemloft.net> [networking] Signed-off-by: NMichal Marek <mmarek@suse.cz>
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- 01 10月, 2014 6 次提交
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由 Heiko Stübner 提交于
S3C2412, S3C2443 and their derivatives contain a special software-reset register in their system-controller. Therefore register a restart handler for those. Tested on a s3c2416-based board, s3c2412 compile-tested. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
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由 Heiko Stübner 提交于
Add infrastructure to write the correct value to the restart register and register the restart notifier for both rk3188 (including rk3066) and rk3288. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
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由 Jianqun 提交于
The relation of i2s nodes as follows: i2s_src 0 0 594000000 0 i2s_frac 0 0 11289600 0 i2s_pre 0 0 11289600 0 sclk_i2s0 0 0 11289600 0 i2s0_clkout 0 0 11289600 0 hclk_i2s0 1 1 99000000 0 sclk_i2s0 is the master clock, when to set rate of sclk_i2s0, should allow to set its parent's rate, by add flag CLK_SET_RATE_PARENT for "i2s_frac", "i2s_pre", "i2s0_clkout" and "sclk_i2s0". Tested on rk3288 board using max98090, with command "aplay <music.wav>" Change-Id: I12faad082566532b65a7de8c0a6845e1c17870e6 Signed-off-by: NJianqun <jay.xu@rock-chips.com> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Robert Jarzmik 提交于
Move pxa27x clock drivers from arch/arm/mach-pxa to driver/clk. In the move : - convert to new clock framework legacy clocks - provide clocks as before for platform data based boards - provide clocks through devicetree Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Robert Jarzmik 提交于
Add a the common code used by all PXA variants. This is the first step in the transition from architecture defined clocks (in arch/arm/mach-pxa) towards clock framework. The goal is to have the same features (and not all the features) of the existing clocks, and enable the transition of PXA to device-tree. All PXA rely on a "CKEN" type clock, which : - has a gate (bit in CKEN register) - is generated from a PLL, generally divided - has an alternate low power clock Each variant will specialize the CKEN clock : - pxa25x have no low power clock - pxa27x in low power use always the 13 MHz ring oscillator - pxa3xx in low power have specific dividers for each clock The device-tree provides a list of CLK_* (ex: CLK_USB or CLK_I2C) to get a handle on the clock. While pxa-clock.h will describe all the clocks of all the variants, each variant will only use a subset of it. Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Mark Brown 提交于
The gpio-gate clock uses the gpiod_ APIs but does not directly include the header for them causing build failures in some configurations including ARM allnoconfig. Include the header directly. Signed-off-by: NMark Brown <broonie@kernel.org> Acked-by: NJyri Sarha <jsarha@ti.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 29 9月, 2014 5 次提交
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由 Peter Ujfalusi 提交于
It is safe to call the pm sync calls in interrupt context in this driver. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NTero Kristo <t-kristo@ti.com>
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由 Behan Webster 提交于
As written, the __init for ti_clk_get_div_table is in the middle of the return type. The gcc documentation indicates that section attributes should be added to the end of the function declaration: extern void foobar (void) __attribute__ ((section ("bar"))); However gcc seems to be very permissive with where attributes can be placed. clang on the other hand isn't so permissive, and fails if you put the section definition in the middle of the return type: drivers/clk/ti/divider.c:298:28: error: expected ';' after struct static struct clk_div_table ^ ; drivers/clk/ti/divider.c:298:1: warning: 'static' ignored on this declaration [-Wmissing-declarations] static struct clk_div_table ^ drivers/clk/ti/divider.c:299:9: error: type specifier missing, defaults to 'int' [-Werror,-Wimplicit-int] __init *ti_clk_get_div_table(struct device_node *node) ~~~~~~ ^ drivers/clk/ti/divider.c:345:9: warning: incompatible pointer types returning 'struct clk_div_table *' from a function with result type 'int *' [-Wincompatible-pointer-types] return table; ^~~~~ drivers/clk/ti/divider.c:419:9: warning: incompatible pointer types assigning to 'const struct clk_div_table *' from 'int *' [-Wincompatible-pointer-types] *table = ti_clk_get_div_table(node); ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~ 3 warnings and 2 errors generated. By convention, most of the kernel code puts section attributes between the return type and function name. In the case where the return type is a pointer, it's important to place the '*' on left of the __init. This updated code works for both gcc and clang. Signed-off-by: NBehan Webster <behanw@converseincode.com> Reviewed-by: NMark Charlebois <charlebm@gmail.com> Reviewed-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NTero Kristo <t-kristo@ti.com>
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I "forgot" to update the dtb and the kernel crashed: |Unable to handle kernel NULL pointer dereference at virtual address 0000002e |PC is at __clk_get_flags+0x4/0xc |LR is at ti_dt_clockdomains_setup+0x70/0xe8 because I did not have the clock nodes. of_clk_get() returns an error pointer which is not checked here. Acked-by: NNishanth Menon <nm@ti.com> Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: NTero Kristo <t-kristo@ti.com>
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由 Tero Kristo 提交于
of_clk_add_provider makes an internal copy of the parent_names property while its called, thus it is no longer needed after this call and can be freed. Signed-off-by: NTero Kristo <t-kristo@ti.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
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由 Tero Kristo 提交于
Previously, the TI clock driver initialized all the clocks hierarchically under each separate clock provider node. Now, each clock that requires IO access will instead check their parent node to find out which IO range to use. This patch allows the TI clock driver to use a few new features provided by the generic of_clk_init, and also allows registration of clock nodes outside the clock hierarchy (for example, any external clocks.) Signed-off-by: NTero Kristo <t-kristo@ti.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Jyri Sarha <jsarha@ti.com> Cc: Stefan Assmann <sassmann@kpanic.de> Acked-by: NTony Lindgren <tony@atomide.com>
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- 28 9月, 2014 5 次提交
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由 Wei Yan 提交于
hix5hd2 add I2C clocks (I2C0~i2C5) Signed-off-by: NWei Yan <sledge.yanwei@huawei.com> Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
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由 Guoxiong Yan 提交于
hix5hd2 add watchdog0 clocks Signed-off-by: NGuoxiong Yan <yanguoxiong@huawei.com> Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
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由 Jiancheng Xue 提交于
Signed-off-by: NJiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
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由 Zhangfei Gao 提交于
Support clk of sata, usb and ethernet Signed-off-by: NJiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
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由 Xiubo Li 提交于
Setting 'flags' to zero will be certainly a misleading way to avoid warning of 'flags' may be used uninitialized. uninitialized_var is a correct way because the warning is a false possitive. Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 27 9月, 2014 16 次提交
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由 Heiko Stuebner 提交于
This adds the necessary soc-specific divider values and switches the armclk to use the newly introduced cpuclk type. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NDoug Anderson <dianders@chromium.org> Tested-by: NDoug Anderson <dianders@chromium.org>
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由 Heiko Stuebner 提交于
When changing the armclk on Rockchip SoCs it is supposed to be reparented to an alternate parent before changing the underlying pll and back after the change. Additionally there exist clocks that are very tightly bound to the armclk whose divider values are set according to the armclk rate. Add a special clock-type to handle all that. The rate table and divider values will be supplied from the soc-specific clock controllers. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NDoug Anderson <dianders@chromium.org> On a rk3288-board: Tested-by: NDoug Anderson <dianders@chromium.org>
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由 Heiko Stuebner 提交于
Rockchip SoCs contain clocks tightly bound to the armclk, where the best rate / divider is supplied by the vendor after careful measuring. Often this ideal rate may be greater than the current rate. Therefore prevent the ccf from trying to set these dividers itself by setting them to read-only. In the case of the rk3066, this also includes the aclk_cpu, which makes it necessary to also split its direct child-clocks (pclk_cpu, hclk_cpu, ...) into individual definitions for rk3066 and rk3188. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NDoug Anderson <dianders@chromium.org> Tested-by: NDoug Anderson <dianders@chromium.org>
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由 Heiko Stuebner 提交于
aclk_cpu_pre on the rk3188 can either be sourced from the armclk or the gpll. To reduce complexity on apll changes caused by cpufreq, reparent it always to the gpll source. If really necessary it could be reparented back on a per board level using the assigned-clocks mechanism. Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Jianqun 提交于
In RK3288, APLL lock status bit is in GRF_SOC_STATUS1, but in RK3188, is GRFSOC_STATUS0. Signed-off-by: NJianqun <jay.xu@rock-chips.com> Also name the constant accordingly as GRF_SOC_STATUS1 to prevent confusion. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NDoug Anderson <dianders@chromium.org> Tested-by: NDoug Anderson <dianders@chromium.org>
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由 Heiko Stuebner 提交于
The register providing the pll lock status is at a different address on the rk3066. The error became apparent while working on cpufreq support for the rockchip SoCs. Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Doug Anderson 提交于
The Rockchip PLL code switches into slow mode (AKA bypass more AKA 24MHz mode) before actually changing the PLL. This keeps anyone from using the PLL while it's changing. However, in all known Rockchip SoCs nobody should ever see the 24MHz when changing the PLL supplying the armclk because we should reparent children to an alternate (faster than 24MHz) PLL. One problem is that the code to switch to an alternate parent was running in PRE_RATE_CHANGE. ...and the code to switch to slow mode was _also_ running in PRE_RATE_CHANGE. That meant there was no real guarantee that we would switch to an alternate parent before switching to 24MHz mode. Let's move the switch to "slow mode" straight into rockchip_rk3066_pll_set_rate(). That means we're guaranteed that the 24MHz is really a last-resort. Note that without this change on real systems we were the code to switch to an alternate parent at 24MHz. In some older versions of that code we'd appy a (temporary) / 5 to the 24MHz causing us to run at 4.8MHz. That wasn't enough to service USB interrupts in some cases and could lead to a system hang. Signed-off-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Chen-Yu Tsai 提交于
The MBUS clock on sun8i is slightly different from the old mod0 clocks. The divider is 3 bits wider, while also needing a divider table for the higher 4 values, which all set the same divider. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The MMC clock we thought we had until now are actually not one but three different clocks. The main one is unchanged, and will have three outputs: - The clock fed into the MMC - a sample and output clocks, to deal with when should we output/sample data to/from the MMC bus The phase control we had are actually controlling the two latter clocks, but the main MMC one is unchanged. We can adjust the phase with a 3 bits value, from 0 to 7, 0 meaning a 180 phase shift, and the other values being the number of periods from the MMC parent clock to outphase the clock of. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Acked-by: NHans de Goede <hdegoede@redhat.com>
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由 Maxime Ripard 提交于
Move the MBUS clock to the module clocks file. It's pretty trivial, but still requires to enable the clocks to make sure it won't get disabled. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Acked-by: NHans de Goede <hdegoede@redhat.com>
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由 Maxime Ripard 提交于
Since we know have the ability to declare factors clock outside of clk-sunxi, create a new mod0 driver to deal with the mod0 clocks. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Acked-by: NHans de Goede <hdegoede@redhat.com>
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由 Maxime Ripard 提交于
Even though the mbus clock is a regular module clock, given its nature, it needs to be enabled all the time. Introduce a new compatible, to differentiate it from the other module clocks. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Acked-by: NHans de Goede <hdegoede@redhat.com>
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由 Maxime Ripard 提交于
Until now, the factors clock probing was done directly by sunxi_init_clocks, with the factors registration being called directly with the clocks data passed as an argument. This approch has shown its limits when we added more clocks, since we couldn't really split code with such a logic in smaller files, and led to a huge file having all the clocks. Introduce an intermediate probing function, so that factor clocks will be able to directly be called by CLK_OF_DECLARE, which will in turn ease the split into several files. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Acked-by: NHans de Goede <hdegoede@redhat.com>
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由 Maxime Ripard 提交于
The current phase API doesn't look into the actual hardware to get the phase value, but will rather get it from a variable only set by the set_phase function. This will cause issue when the client driver will never call the set_phase function, where we can end up having a reported phase that will not match what the hardware has been programmed to by the bootloader or what phase is programmed out of reset. Add a new get_phase function for the drivers to implement so that we can get this value. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NHans de Goede <hdegoede@redhat.com>
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由 Mike Turquette 提交于
A common operation for a clock signal generator is to shift the phase of that signal. This patch introduces a new function to the clk.h API to dynamically adjust the phase of a clock signal. Additionally this patch introduces support for the new function in the common clock framework via the .set_phase call back in struct clk_ops. Signed-off-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NHans de Goede <hdegoede@redhat.com>
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由 Jyri Sarha 提交于
The added gpio-gate-clock is a basic clock that can be enabled and disabled trough a gpio output. The DT binding document for the clock is also added. For EPROBE_DEFER handling the registering of the clock has to be delayed until of_clk_get() call time. Signed-off-by: NJyri Sarha <jsarha@ti.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 26 9月, 2014 2 次提交
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由 Kiran Padwal 提交于
There is no need to init .owner field. Based on the patch from Peter Griffin <peter.griffin@linaro.org> "mmc: remove .owner field for drivers using module_platform_driver" This patch removes the superflous .owner field for drivers which use the module_platform_driver API, as this is overriden in platform_driver_register anyway." Signed-off-by: NKiran Padwal <kiran.padwal@smartplayin.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Kever Yang 提交于
This patch add the clock node in PD_VIDEO Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NDoug Anderson <dianders@chromium.org> Tested-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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