1. 18 9月, 2009 2 次提交
  2. 11 9月, 2009 1 次提交
    • J
      drm/i915: framebuffer compression for pre-GM45 · 80824003
      Jesse Barnes 提交于
      This patch adds framebuffer compression (good for about ~0.5W power
      savings in the best case) support for pre-GM45 chips.  GM45+ have a new,
      more flexible FBC scheme that will be added in a separate patch.
      
      FBC can't always be enabled: the compressed buffer must be physically
      contiguous and reside in stolen space.  So if you have a large display
      and a small amount of stolen memory, you may not be able to take
      advantage of FBC.  In some cases, a BIOS setting controls how much
      stolen space is available.  Increasing this to 8 or 16M can help.
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: NEric Anholt <eric@anholt.net>
      80824003
  3. 05 9月, 2009 3 次提交
    • Z
      drm/i915: fix tiling on IGDNG · 553bd149
      Zhenyu Wang 提交于
      It seems that on IGDNG the same swizzling setup always applys.
      And front buffer tiling needs to set address swizzle in display
      arb control too.
      
      Fix plane tricle feed setting in v1 which should be disable bit,
      and always setup address swizzle to let hardware care for buffer
      tiling in all cases.
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      Signed-off-by: NEric Anholt <eric@anholt.net>
      553bd149
    • J
      drm/i915: add dynamic clock frequency control · 652c393a
      Jesse Barnes 提交于
      There are several sources of unnecessary power consumption on Intel
      graphics systems. The first is the LVDS clock. TFTs don't suffer from
      persistence issues like CRTs, and so we can reduce the LVDS refresh rate
      when the screen is idle. It will be automatically upclocked when
      userspace triggers graphical activity. Beyond that, we can enable memory
      self refresh. This allows the memory to go into a lower power state when
      the graphics are idle. Finally, we can drop some clocks on the gpu
      itself. All of these things can be reenabled between frames when GPU
      activity is triggered, and so there should be no user visible graphical
      changes.
      Signed-off-by: NJesse Barnes <jesse.barnes@intel.com>
      Signed-off-by: NMatthew Garrett <mjg@redhat.com>
      Signed-off-by: NEric Anholt <eric@anholt.net>
      652c393a
    • S
      drm/i915: Support IGD EOS · 04302965
      Shaohua Li 提交于
      In the event that any one of the DAC analog outputs (R,G,B) were driven
      at full-scale (white video) or some analog level close to full-scale
      voltage, and if the video cable were then disconnected, the analog video
      voltage level would exceed the maximum electrical overstress limit of the
      native (thin-oxide) transistors thus causing a long-term reliability concern.
      The electrical overstress condition occurs in this particular case.
      
      This patch address the IGD EOS (electrical overstress condition) issue.
      When the EOS interrupt occurs, OS should disable DAC and then disable EOS,
      then the normal hotplug operation follows.
      
      TODO: it appears the normal unplug interrupt is missed as reported by Li Peng,
      need more checks here.
      Signed-off-by: NShaohua Li <shaohua.li@intel.com>
      Signed-off-by: NEric Anholt <eric@anholt.net>
      04302965
  4. 30 7月, 2009 3 次提交
  5. 15 7月, 2009 1 次提交
    • J
      drm/i915: FIFO watermark calculation fixes · dff33cfc
      Jesse Barnes 提交于
      I discovered several bugs in the FIFO code that was recently applied.
      Some of them fell into the "how did this ever work" category, since in
      some cases we were using the wrong FIFO size values, and the
      calculations ended up being way off.
      
      This patch fixes all the bugs I found, and works well on my GM45, 915GM
      and 855GM test machines; but as usual with these sorts of patches
      broader testing is definitely requested (in particular this patch
      affects 830, 845 and 865 for which I don't have test hardware).
      
      Overall, the patch clarifies the watermark calculation function by
      adding some comments and debug info, and making the variable names a
      bit clearer.  The "get FIFO size" portion of the code has also been
      corrected, so we should be able to properly detect the FIFO allocations
      for each pipe, for use in the watermark calculation.
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: NEric Anholt <eric@anholt.net>
      dff33cfc
  6. 02 7月, 2009 2 次提交
  7. 23 6月, 2009 1 次提交
  8. 19 6月, 2009 1 次提交
  9. 05 6月, 2009 3 次提交
  10. 27 5月, 2009 1 次提交
    • E
      drm/i915: Fix tiling pitch handling on 8xx. · e76a16de
      Eric Anholt 提交于
      The pitch field is an exponent on pre-965, so we were rejecting buffers
      on 8xx that we shouldn't have.  915 got lucky in that the largest legal
      value happened to match (8KB / 512 = 0x10), but 8xx has a smaller tile width.
      Additionally, we programmed that bad value into the register on 8xx, so the
      only pitch that would work correctly was 4096 (512-1023 pixels), while others
      would probably give bad rendering or hangs.
      Signed-off-by: NEric Anholt <eric@anholt.net>
      
      fd.o bug #20473.
      e76a16de
  11. 23 5月, 2009 1 次提交
  12. 15 5月, 2009 1 次提交
  13. 17 4月, 2009 1 次提交
  14. 02 4月, 2009 2 次提交
    • J
      drm/i915: add VGA hotplug support for 945+ · 5ca58282
      Jesse Barnes 提交于
      Add VGA port hotplug detection to the i915 driver.  When KMS is enabled,
      plugging in or removing a VGA cable from the VGA connector will
      generate a uevent, which indicates to userspace that it should re-probe
      outputs on this device (to determine modes, etc.).
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      [anholt: dropped extra PORT_HOTPLUG_STAT clear with ack from jbarnes]
      Signed-off-by: NEric Anholt <eric@anholt.net>
      5ca58282
    • D
      drm/i915: fix up tiling/fence reg setup on i8xx class hw · 8d7773a3
      Daniel Vetter 提交于
      This fixes all the tiling problems with the 2d ddx. glxgears still doesn't work.
      Changes:
      
      - fix a copy&paste error in i8xx fence reg setup. It resulted in an at most a
        512KB offset of the fence reg window, so was only visible sometimes.
      - add tests for stride and object size constrains (also for i915 and 1965 class
        hw). Userspace seems to have an of-by-one bug there, which changes the fence
        size by at most 512KB due to an overflow.
      - because i8xx hw is quite old (and therefore not as well-tested) I left 2 debug
        WARN_ONs in the i8xx fence reg setup code to hopefully catch any further
        overflows in the bit-fields. Lastly there's one small change to make the
        alignment checks more consistent.
      
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=20289Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: NEric Anholt <eric@anholt.net>
      8d7773a3
  15. 28 3月, 2009 3 次提交
  16. 12 3月, 2009 1 次提交
  17. 08 2月, 2009 2 次提交
  18. 07 1月, 2009 2 次提交
  19. 29 12月, 2008 1 次提交
  20. 04 12月, 2008 1 次提交
  21. 11 11月, 2008 1 次提交
  22. 18 10月, 2008 3 次提交