This patch puts in place the machinery to attempt to reset the GPU. This
will be used when attempting to recover from a GPU hang.
Signed-off-by: NOwain G. Ainsworth <oga@openbsd.org>
Signed-off-by: NBen Gamari <bgamari.foss@gmail.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

We set a periodic timer to check on the GPU, resetting it every time a
batch is completed. If the timer elapses, we check acthd. If acthd
hasn't changed in two timer periods, we assume the chip is wedged.

This is implemented in such a way that it leaves the option open to
employ adaptive timer intervals in the future. One could wait until
several timer periods have elapsed before declaring the chip dead. If
the chip comes back after several periods but before the "dead"
threshold, the timer interval or dead threshold could be raised.

It is important to note that while checking for active requests, we need
to account for the fact that requests are removed from the list (i.e.
retired) in a deferred work queue handler. This means that merely
checking for an empty request_list is insufficient; the list could be
non-empty yet the GPU still idle, causing the hangcheck timer to
incorrectly mark the GPU as wedged (it took me a while to figure that
out---sigh...)
Signed-off-by: NBen Gamari <bgamari.foss@gmail.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

We'll need it in i915_irq.c for checking whether there are outstanding
requests. Also, the function really ought to return a bool, not an int.
Signed-off-by: NBen Gamari <bgamari.foss@gmail.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

We move the display-specific code into it's own functions, called
from the general GPU state save/restore functions. This will be needed
later by the GPU reset code.
Signed-off-by: NBen Gamari <bgamari.foss@gmail.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

i915_wait_request() only checks mm.wedged after it interacts with the
hardware, generally causing the driver to lock up waiting for a wedged
chip. Make sure we check mm.wedged as the first thing we do.
Reported-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NBen Gamari <bgamari.foss@gmail.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

BLC_PWM_CTL2 is for 965+ only, so add device model check for
legacy backlight control.

For native backlight control, it maps the backlight value (0~255)
in opregion ASLE[BCLP] to backlight duty cycle (0~max_backlight)
and set into control register.

It also add support for IGD device, which follows opregion spec.
Signed-off-by: NLi Peng <peng.li@intel.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

Arrandale has new window based method for panel fitting.
This one enables full screen aspect scaling on LVDS. It fixes
standard mode display failure on LVDS for Arrandale.

Cc: Stable Team <stable@kernel.org>
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

This is not required on newer stepping hardware to get
reliable force detect status. Removing this fixes screen
blank flicker in CRT detect on IGDNG.

Cc: Stable Team <stable@kernel.org>
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

IGDNG LVDS SSC uses 120Mhz freq. This fixes one
1600x900 LVDS panel black issue on IGDNG with SSC enabled.

Cc: Stable Team <stable@kernel.org>
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

New register for PCH LVDS on IGDNG should be used.
This is a copy-n-paste typo. This fixes possible dual
channel LVDS panel failure on IGDNG.

Cc: Stable Team <stable@kernel.org>
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

We want the compressed line length buffer address, not the framebuffer
address.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

drm_ht_remove_item() does not handle removing an absent item and the hlist
in particular is incorrectly initialised. The easy remedy is simply skip
calling i915_gem_free_mmap_offset() unless we have actually created the
offset and associated ht entry.

This also fixes the mishandling of a partially constructed offset which
leaves pointers initialized after freeing them along the
i915_gem_create_mmap_offset() error paths.

In particular this should fix the oops found here:
https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/415357/comments/8Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NEric Anholt <eric@anholt.net>
Cc: stable@kernel.org

Ever since we enabled GEM, the pre-9xx chipsets (particularly 865) have had
serious stability issues.  Back in May a wbinvd was added to the DRM to
work around much of the problem.  Some failure remained -- easily visible
by dragging a window around on an X -retro desktop, or by looking at bugzilla.

The chipset flush was on the right track -- hitting the right amount of
memory, and it appears to be the only way to flush on these chipsets, but the
flush page was mapped uncached.  As a result, the writes trying to clear the
writeback cache ended up bypassing the cache, and not flushing anything!  The
wbinvd would flush out other writeback data and often cause the data we wanted
to get flushed, but not always.  By removing the setting of the page to UC
and instead just clflushing the data we write to try to flush it, we get the
desired behavior with no wbinvd.

This exports clflush_cache_range(), which was laying around and happened to
basically match the code I was otherwise going to copy from the DRM.
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NBrice Goglin <Brice.Goglin@ens-lyon.org>
Cc: stable@kernel.org

This patch adds framebuffer compression (good for about ~0.5W power
savings in the best case) support for pre-GM45 chips.  GM45+ have a new,
more flexible FBC scheme that will be added in a separate patch.

FBC can't always be enabled: the compressed buffer must be physically
contiguous and reside in stolen space.  So if you have a large display
and a small amount of stolen memory, you may not be able to take
advantage of FBC.  In some cases, a BIOS setting controls how much
stolen space is available.  Increasing this to 8 or 16M can help.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

With all the other lid pieces in place, it's easy to generate a uevent
for the LVDS connector just like we do for other outputs.  Should make
lid open/close fit in with the rest of a userland based output
reconfiguration scheme.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

We can't load or hotplug detect LVDS like we can other outputs, but if
there's a lid device present we can use it as a proxy.  This allows the
LFP state to be determined at ->detect time, making configurations
requiring manual intervention today "just work" assuming the lid device
status is correct.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

Some laptop platforms will disable pipes and/or planes at lid close time
and not restore them when the lid is opened again.  So catch the lid
event, and if the lid was opened, force a mode restore.

Fixes fdo bug #21230.
Acked-by: NMatthew Garrett <mjg@redhat.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

Test on the IGD chip, which is a G33-like graphic device.
Signed-off-by: NLi Peng <peng.li@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

When the output device is LVDS, maybe the pixel clock of adjusted_mode will be
less than that in mode. In such case it will set the incorrect multipler factor
in DPLL_MD register.
So the dpll_md_reg will be reset when the output type is non-SDVO

https://bugs.freedesktop.org/show_bug.cgi?id=22761Signed-off-by: NZhao Yakui <yakui.zhao@intel.com>
Reviewd-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NEric Anholt <eric@anholt.net>

Add the missing clone_mask for SDVO-VGA(RGB1)
Signed-off-by: NZhao Yakui <yakui.zhao@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

When the sdvo device is detected as SDVO-LVDS, we will check whether the
brightness is supported by issue SDVO enhancement command.
If it is supported, we will add the brightness property and then brightness
can be adjusted.
Signed-off-by: NZhao Yakui <yakui.zhao@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

When the sdvo device is detected as SDVO-TV, we will check whether the
sepecific picture enhancement is supported. If it is supported, we will
add the corresponnding property for SDVO-TV. We will add the following
property for the SDVO-TV enhancements if they are supported:
 * Contrast/Brightness/Saturation/Hue.
 * left/right/top/bottom margin: This is implemented by using the
   horizontal/vertical overscan enhancements. When the overscan
   enhancements are supported, the above properties will be added. This is
   to be compatible with what we have done in integrated-TV.
 * horizontal pos/vertical pos.

http://bugs.freedesktop.org/show_bug.cgi?id=22891Signed-off-by: NZhao Yakui <yakui.zhao@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Otherwise, some other userland writing into its buffer may race to land
writes either after the CPU thinks it's got a coherent view, or after its
GTT entries have been redirected to point at the scratch page.  Either
result is unpleasant.
Signed-off-by: NEric Anholt <eric@anholt.net>

Signed-off-by: NFabian Henze <hoacha@quantentunnel.de>
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

The driver gets the bridge device in a number of places, upcoming
vga arb code paths need the bridge device, however they need it in
under a lock, and the pci lookup can allocate memory. So clean
this code up before then and get the bridge once for the driver lifetime.
Signed-off-by: NDave Airlie <airlied@redhat.com>

Fixes (again) whole-system lockups due to GPU lockups.
Signed-off-by: NEric Anholt <eric@anholt.net>

According to the docs, the ringbuffer is not allowed to wrap in the middle
of an instruction.

G45 PRM, Vol 1b, p101:
  While the “free space” wrap may allow commands to be wrapped around the
  end of the Ring Buffer, the wrap should only occur between commands.
  Padding (with NOP) may be required to follow this restriction.

Do as commanded.

[Having seen bug reports where there is evidence of split commands, but
apparently the GPU has continued on merrily before a bizarre and untimely
death, this may or may not fix a few random hangs.]
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
CC: Eric Anholt <eric@anholt.net>
Signed-off-by: NEric Anholt <eric@anholt.net>

Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

mac Mini's have a single DDC line on the DVI connector, shared between the
analog link and the digital link. So, if DDC isn't detected on GPIOE (the
usual SDVO DDC link), try GPIOA (the usual VGA DDC link) when there isn't a
VGA monitor connected.
Signed-off-by: NKeith Packard <keithp@keithp.com>
Signed-off-by: NZhao Yakui <yakui.zhao@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

It seems that on IGDNG the same swizzling setup always applys.
And front buffer tiling needs to set address swizzle in display
arb control too.

Fix plane tricle feed setting in v1 which should be disable bit,
and always setup address swizzle to let hardware care for buffer
tiling in all cases.
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NEric Anholt <eric@anholt.net>

And clean up a small whitespace goof-up in the same function, while
I was looking at it.
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NEric Anholt <eric@anholt.net>

Signed-off-by: NEric Anholt <eric@anholt.net>
Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>

Signed-off-by: NKyle McMartin <kyle@redhat.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

There are several sources of unnecessary power consumption on Intel
graphics systems. The first is the LVDS clock. TFTs don't suffer from
persistence issues like CRTs, and so we can reduce the LVDS refresh rate
when the screen is idle. It will be automatically upclocked when
userspace triggers graphical activity. Beyond that, we can enable memory
self refresh. This allows the memory to go into a lower power state when
the graphics are idle. Finally, we can drop some clocks on the gpu
itself. All of these things can be reenabled between frames when GPU
activity is triggered, and so there should be no user visible graphical
changes.
Signed-off-by: NJesse Barnes <jesse.barnes@intel.com>
Signed-off-by: NMatthew Garrett <mjg@redhat.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

In the event that any one of the DAC analog outputs (R,G,B) were driven
at full-scale (white video) or some analog level close to full-scale
voltage, and if the video cable were then disconnected, the analog video
voltage level would exceed the maximum electrical overstress limit of the
native (thin-oxide) transistors thus causing a long-term reliability concern.
The electrical overstress condition occurs in this particular case.

This patch address the IGD EOS (electrical overstress condition) issue.
When the EOS interrupt occurs, OS should disable DAC and then disable EOS,
then the normal hotplug operation follows.

TODO: it appears the normal unplug interrupt is missed as reported by Li Peng,
need more checks here.
Signed-off-by: NShaohua Li <shaohua.li@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Currently SDVO TV only support NTSC-M format. In this patch
we introduce PAL and SECAM formats available and create seting-format
property at init time. When user dynamically chose preferred
format by xrandr command, it will refine all modelines
provided by SDVO device, then instruct SDVO device to execute.
At the same time the property is added for SDVO-TV so that the SDVO-TV mode can be changed
by using xrandr.

https://bugs.freedesktop.org/show_bug.cgi?id=22891Signed-off-by: NMa Ling <ling.ma@intel.com>
review-by: NZhao Yakui <yakui.zhao@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

For integrated TV there are 3 connector types: S-VIDEO, Composite and
Component(YprPb). Those tv formats whose component flag is true should
be assigned to Component connector, others are for S-VIDEO and Composite.
The patch intends to find appropriate tv format for each connector.
In such case it will return the correct modeline to user space. Otherwise
it will return the incorrect modeline when S-video/composite is connected.
Signed-off-by: NMa Ling <ling.ma@intel.com>
reviewed-by: NZhao Yakui <yakui.zhao@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Add a debugfs file to dump the entire register range. Here we
assume that reading write-only/reserved registers won't make the chip
angry. Seems to hold true, thankfully.
Signed-off-by: NBen Gamari <bgamari.foss@gmail.com>
Signed-off-by: NEric Anholt <eric@anholt.net>