Adding EZchip NPS400 support.
Internal interrupts are handled by Multi Thread Manager (MTM)
Once interrupt is serviced MTM is acked for deactivating the interrupt.
External interrupts are handled by MTM as well as at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by: NNoam Camus <noamc@ezchip.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NVineet Gupta <vgupta@synopsys.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>

The Allwinner A10 compatibles were following a slightly different compatible
patterns than the rest of the SoCs for historical reasons. Change the compatibles
to match the other pattern in the irq controller driver for consistency.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

The documented value of #interrupt-cells is 1.
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

That documentation was mostly useful when we didn't have any
documentation for those SoCs, which is not the case anymore. Remove
this, since it should live in the DT anyway.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Cc: Mark Rutland <mark.rutland@arm.com>

A10 and A13 have a different set of available interrupt sources, reflect
this in the documentation.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

During the introduction of the Allwinner SoC platforms, sunxi was
initially meant as a generic name for all the variants of the Allwinner
SoC.

It was ok at the time of the support of only the A10 and A13 that
looks pretty much the same, but it's beginning to be troublesome with
the future addition of the Allwinner A31 (sun6i) that is quite
different, and would introduce some weird logic, where sunxi would
actually mean in some case sun4i and sun5i but without sun6i...

Moreover, it makes the compatible strings naming scheme not consistent
with other architectures, where usually for this kind of compability, we
just use the oldest SoC name that has this IP, so let's do just this.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
CC: Thomas Gleixner <tglx@linutronix.de>