The framework only asserts (for now) that the reset gpio is not active.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Correct what appears to be a typo in the name of the sd-uhs-sdr50.

Also fix mixed tab/space indentation.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Resetting the switch is something the driver does, not the framework.
So move the parsing of this property into the driver.

There are no in kernel users of this property, so moving it does not
break anything. There is however a board which will make use of this
property making its way into the kernel.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Allow Marvell switches to be mdio devices. Currently the driver just
allocate the private structure and detects what device is on the
bus. Later patches will make them register with the DSA framework.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch adds the device tree bindings for the Western Digital's
MyBook Live memory-mapped GPIO controllers.

The gpios will be supported by gpio-mmio code of the
GPIO generic library.
Signed-off-by: NChristian Lamparter <chunkeey@googlemail.com>
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Make it possible to name the producer side of a GPIO line using
a "gpio-line-names" property array, modeled on the
"clock-output-names" property from the clock bindings.

This naming is especially useful for:

- Debugging: lines are named after function, not just opaque
  offset numbers.

- Exploration: systems where some or all GPIO lines are available
  to end users, such as prototyping, one-off's "makerspace usecases"
  users are helped by the names of the GPIO lines when tinkering.
  This usecase has been surfacing recently.

The gpio-line-names attribute is completely optional.

Example output from lsgpio on a patched Snowball tree:

GPIO chip: gpiochip6, "8000e180.gpio", 32 GPIO lines
        line  0: unnamed unused
        line  1: "AP_GPIO161" "extkb3" [kernel]
        line  2: "AP_GPIO162" "extkb4" [kernel]
        line  3: "ACCELEROMETER_INT1_RDY" unused [kernel]
        line  4: "ACCELEROMETER_INT2" unused
        line  5: "MAG_DRDY" unused [kernel]
        line  6: "GYRO_DRDY" unused [kernel]
        line  7: "RSTn_MLC" unused
        line  8: "RSTn_SLC" unused
        line  9: "GYRO_INT" unused
        line 10: "UART_WAKE" unused
        line 11: "GBF_RESET" unused
        line 12: unnamed unused

Cc: Grant Likely <grant.likely@linaro.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: David Mandala <david.mandala@linaro.org>
Cc: Lee Campbell <leecam@google.com>
Cc: devicetree@vger.kernel.org
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NMichael Welling <mwelling@ieee.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Adding EZchip NPS400 support.
Internal interrupts are handled by Multi Thread Manager (MTM)
Once interrupt is serviced MTM is acked for deactivating the interrupt.
External interrupts are handled by MTM as well as at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by: NNoam Camus <noamc@ezchip.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NVineet Gupta <vgupta@synopsys.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>

Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: NNoam Camus <noamc@ezchip.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: John Stultz <john.stultz@linaro.org>
Acked-by: NVineet Gupta <vgupta@synopsys.com>
Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Add EZchip to vendor prefixes list.
EZchip introduce the NPS platform for the ARC architecture.
Signed-off-by: NNoam Camus <noamc@ezchip.com>
Acked-by: NRob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>

ARC Timers have historically been probed directly.
As precursor to start probing Timers thru DT introduce these bindings
Note that to keep series bisectable, these bindings are not yet used in
code.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: devicetree@vger.kernel.org
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NVineet Gupta <vgupta@synopsys.com>

Add entries for all supported chip variants into the of_match list, so that
the matching driver_info can be selected when using dt.
Signed-off-by: NJulian Scheel <julian@jusst.de>
Signed-off-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>

Add device tree binding documentation for the adv7180 video decoder family.
Signed-off-by: NJulian Scheel <julian@jusst.de>
Signed-off-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>

Calling a GPIO LEDs is quite likely to work even if the kernel
has paniced, so they are ideal to blink in this situation.
This commit adds support for the new "panic-indicator"
firmware property, allowing to mark a given LED to blink on
a kernel panic.
Signed-off-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: NMatthias Brugger <mbrugger@suse.com>
Acked-by: NPavel Machek <pavel@ucw.cz>
Signed-off-by: NJacek Anaszewski <j.anaszewski@samsung.com>

It's desirable to specify which LEDs are to be blinked on a kernel
panic. Therefore, introduce a devicetree boolean property to mark
which LEDs should be treated this way, if possible.
Signed-off-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: NMatthias Brugger <mbrugger@suse.com>
Acked-by: NRob Herring <rob@kernel.org>
Acked-by: NPavel Machek <pavel@ucw.cz>
Signed-off-by: NJacek Anaszewski <j.anaszewski@samsung.com>

Some Layerscape SoCs use a simple MSI controller implementation.
It contains only two SCFG register to trigger and describe a
group 32 MSI interrupts. The patch adds bindings to describe
the controller.
Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

This patch adds the detailed corrleation between sub-blocks and power line
for Exynos5422.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NMyungJoo Ham <myungjoo.ham@samsung.com>

This patch adds NoC (Network on Chip) Probe driver which provides
the primitive values to get the performance data. The packets that the Network
on Chip (NoC) probes detects are transported over the network infrastructure.
Exynos542x bus has multiple NoC probes to provide bandwidth information about
behavior of the SoC that you can use while analyzing system performance.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Tested-by: NMarkus Reichl <m.reichl@fivetechno.de>
Tested-by: NAnand Moon <linux.amoon@gmail.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

This patch adds the detailed correlation between sub-blocks and power line
for Exynos3250, Exynos4210 and Exynos4x12.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NMyungJoo Ham <myungjoo.ham@samsung.com>
Acked-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

This patch updates the documentation for passive bus devices and adds the
detailed example of Exynos3250.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NMyungJoo Ham <myungjoo.ham@samsung.com>
Acked-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

This patch adds the documentation for generic exynos bus frequency
driver.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NMyungJoo Ham <myungjoo.ham@samsung.com>

Signed-off-by: NIyappan Subramanian <isubramanian@apm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Add device tree binding documentation for MARVELL's bluetooth sdio
(sd8897 and sd8997) chip.
Signed-off-by: NXinming Hu <huxm@marvell.com>
Signed-off-by: NAmitkumar Karwar <akarwar@marvell.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMarcel Holtmann <marcel@holtmann.org>

Add a decription of the PPI partitioning support.
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NRob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Will Deacon <will.deacon@arm.com>
Link: http://lkml.kernel.org/r/1460365075-7316-6-git-send-email-marc.zyngier@arm.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Add a pinctrl binding to specify different pin settings for high speed
modes and UHS modes.
Signed-off-by: NLars Persson <larper@axis.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Implement voltage switch, supporting modes up to SDR-50.

Based on work by Shinobu Uehara, Rob Taylor, William Towle and Ian Molton.
Signed-off-by: NBen Hutchings <ben.hutchings@codethink.co.uk>
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Add pn533-i2c phy devicetree documentation
Signed-off-by: NMichael Thalmeier <michael.thalmeier@hale.at>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

The following patch adds the required match table for device tree support
(and while at, fix the indent). It's also possible to specify the
MAC address in the DT blob.

Also add the corresponding binding documentation file.
Signed-off-by: NMichael Heimpold <mhei@heimpold.de>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch changes property port-id to reg in dsaf port node,
removes property cpld-ctrl-reg, and fixes some typos.
Signed-off-by: NYisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Extend the Tegra XUSB controller device tree binding with Tegra210
support.
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add device-tree binding documentation for the XUSB controller present
on Tegra124 and later SoCs. This controller supports USB 3.0 via an xHCI
compliant interface.

Based on work by Andrew Bresticker <abrestic@chromium.org>.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Mathias Nyman <mathias.nyman@intel.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The XUSB pad controller allows PCIe lanes to be controlled individually,
providing fine-grained control over their power state. Previous attempts
at describing the XUSB pad controller in DT had erroneously assumed that
all PCIe lanes were driven by the same PHY, and hence the PCI host
controller would reference only a single PHY.

Moving to a representation of per-lane PHYs requires that the operating
system driver for the PCI host controller have access to the set of PHY
devices that make up the connection of each root port in order to power
up and down all of the lanes as necessary.
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Extend the binding to cover the set of feature found in Tegra210.
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The NVIDIA Tegra XUSB pad controller provides a set of pads, each with a
set of lanes that are used for PCIe, SATA and USB.

A binding exists for the XUSB pad controller already, but it turned out
not to be flexible enough to describe all aspects of the controller. In
particular, the addition of XUSB support (for SuperSpeed USB) has shown
that the existing binding is no longer suitable. Mark the old binding
as deprecated and link to the new binding.
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The phy-handle, phy_id, and fixed-link properties are mutually exclusive,
and only one need be specified. Make this clear in the binding doc.

Also mark the phy_id property as deprecated, as phy-handle should be
used instead.
Signed-off-by: NDavid Rivshin <drivshin@allworx.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Use "rockchip,rk3399-evb" compatible string for Rockchip RK3399
evaluation board.
Signed-off-by: NJianqun Xu <jay.xu@rock-chips.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This adds documentation of device tree bindings for the
timers found on ARM MPS2 platform.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NVladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

NXP LPC32xx has three interrupt controllers, namely root Main
Interrupt Controller (MIC) and two supplementary Sub Interrupt
Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
are connected to MIC.
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NSylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

Add "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc" for
dwmmc on rk3399 platform.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NJianqun Xu <jay.xu@rock-chips.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Even if the Armada 37xx does not any specific setup, the device tree
binding documentation requires to use a SoC-specific version
corresponding to the platform first followed by the generic version.

This patch introduce this new compatible string and updates the
documentation accordingly.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

This patch adds documentation for the devicetree bindings used by
the DT files of Hisilicon Hip06 D03 board.

Meanwhile, reorder the soc/board name alphabetically.
Signed-off-by: NKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>