Exynos initialization code now relies on obtaining the PMU address,
so prepare a PMU node for Exynos5410.

Fixes: fce9e5bb ("ARM: EXYNOS: Add support for mapping PMU base
address via DT")
Signed-off-by: NAndreas Faerber <afaerber@suse.de>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch add I2S (Inter-IC Sound) dt node which supports 1-port
stereo (1 channels) IIS-bus for audio interface with DMA-based
operation.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NInha Song <ideal.song@samsung.com>
Tested-by: NInha Song <ideal.song@samsung.com>
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This adds cros_ec to exynos5420-peach-pit and exynos5800-peach-pi,
including:
* The keyboard
* The i2c tunnel
* The tps65090 under the i2c tunnel
* The battery under the i2c tunnel

To add extra motivation, it should be noted that tps65090 is one of
the things needed to get display-related FETs turned on for pit and
pi.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: NTushar Behera <tushar.b@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch cleans a arm-pmu node up for exynos4. Only exynos4412 series
boards have four pmu interrupts. Rest of exynos4 boards, except 4412, have only
two pmu interrupts. Thus, we can define two interrupts in the
exynos4.dtsi and extends the interrupts only exynos4412.dtsi.

Cc: Chanwoo Choi <cw00.choi@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: NChanho Park <chanho61.park@samsung.com>
Tested-by: NTushar Behera <tushar.behera@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The pwm driver requires a clocks property referencing the pwm peripheral
clk.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

udphs_clk (USB Device Controller clock) is referenced instead of
uhphs_clk (USB Host Controller clock).
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Correct the typo error for the second "uhphs_clk".
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Display domain is removed due to instability issues. Explaining
the problem below:

exynos_init_late triggers the pm_genpd_poweroff_unused which powers
off the unused power domains. This call hits before the trigger to
deferred probes.

DRM DP Panel defers the probe due to supply get failure. By the time,
deferred probe is scheduled again, Display Power Domain is powered
off by pm_genpd_poweroff_unused.

FIMD and DP drivers are accessing registers during Probe and Bind
callbacks. If display domain is enabled/disabled around register
accesses, display domain gets unstable and we are getting Power Domain
Disable fail notification. Increasing the Timeout also didn't help.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add MAX98090 audio codec, I2S interface and the sound complex
nodes to enable audio on Odroid-X2/U3 boards.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

TFLASH (SDHCI2 controller) uses internal card detect line, but it looks
that the driver fails to operate it properly. Use GPIO interrupt on
SD_CDn line for detecting SD card state.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds support for simple GPIO-based button availabled on
Exynos4 based Odroid boards. All supported boards have POWER button,
which has been defined in exynos4412-odroid-common.dtsi. X/X2 boards
also have additional user-configurable button which has been mapped to
KEY_HOME. All defined keys have been marked as possible wakeup source.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

On Odroid U2/U3 BUCK8 is used for providing power to also to P3V3
source, which is also connected to LAN9730 chip's nRESET signal. To
reset lan chip on system reboot, the BUCK8 output should not be used in
'always on' mode. This change has no impact on X/X2 boards.
Signed-off-by: NKamil Debski <k.debski@samsung.com>
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch moves some parts of exynos4412-odroidx.dts to common
exynos4412-odroid-common.dtsi file and adds support for Odroid X2 and
U2/U3 boards. X2 is same as X, but it has faster SoC module (1.7GHz
instead of 1.4GHz), while U2/U3 differs from X2 by different way of
routing signals to host USB hub. It also lacks some hw modules not yet
supported by those dts files (i.e. LCD & touch panel).
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Last megabyte of RAM is used by secure firmware and should not be accessed
by Linux kernel, so correct available memory size in DTS file.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds basic support for USB modules (host and device) on
OdroidX board.
Signed-off-by: NKamil Debski <k.debski@samsung.com>
[removed incorrect port@2 node]
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds support for common hardware modules available on all
Exynos4412-based Odroid boards, which already have complete support in
mainline kernel. This includes secure firmware calls, watchdog, g2d and
fimc (mem2mem) multimedia accelerators.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds port sub-nodes to exynos4 ehci and ohci modules, which
are required by recently merged new exynos4 usb2 phy support.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from
being reset across sleep/wake.  If we don't set it to anything then
the TPM will be reset.  U-Boot will detect this as invalid
and will reset the system on resume time. This GPIO can always be low
and not hurt anything.  It will get pulled back high again during a
normal warm reset when it will default back to an input.

To properly preserve the TPM state across suspend/resume and to make
the chrome U-Boot happy, properly set the GPIO to mask the
reset to the TPM.
Signed-off-by: NVikas Sajjan <vikas.sajjan@samsung.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from
being reset across sleep/wake.  If we don't set it to anything then
the TPM will be reset.  U-Boot will detect this as invalid
and will reset the system on resume time. This GPIO can always be low
and not hurt anything.  It will get pulled back high again during a
normal warm reset when it will default back to an input.

To properly preserve the TPM state across suspend/resume and to make
the chrome U-Boot happy, properly set the GPIO to mask the
reset to the TPM.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NVikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add clocks for usb device, or else switch to CCF, the gadget
won't work.
Reported-by: NJiri Prchal <jiri.prchal@aksignal.cz>
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Tested-by: NJiri Prchal <jiri.prchal@aksignal.cz>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Adding the optional clock property for the mfc_pd for
handling the re-parenting while pd on/off.
Signed-off-by: NArun Kumar K <arun.kk@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux.
As per the user manual, it should be CLK_MAU_EPLL.

The problem surfaced when the bootloader in Peach-pit board set
the EPLL clock as the parent of AUDSS mux. While booting the kernel,
we used to get a system hang during late boot if CLK_MAU_EPLL was
disabled.
Signed-off-by: NTushar Behera <tushar.b@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Reported-by: NKevin Hilman <khilman@linaro.org>
Tested-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add sound-card name property to Snow/Peach-Pit/Peach-Pi boards.
Signed-off-by: NTushar Behera <tushar.b@samsung.com>
Acked-by: NMark Brown <broonie@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

It's 1.6 GHz for the Cortex-A15.

Avoids warnings like "/cpus/cpu@0 missing clock-frequency property".
Signed-off-by: NAndreas Faerber <afaerber@suse.de>
Reviewed-by: NTarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

As this board use external clock for RMII interface we should specify 'rmii'
phy mode and 'rmii-clock-ext' to make ethernet working.
Signed-off-by: NEnric Balletbo i Serra <eballetbo@iseebcn.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The use of FIFO in McASP can reduce the risk of audio under/overrun and
lowers the load on the memories since the DMA will operate in bursts.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The use of FIFO in McASP can reduce the risk of audio under/overrun and
lowers the load on the memories since the DMA will operate in bursts.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

After clarification from the hardware team it was found that
this 1.8V PHY supply can't be switched OFF when SoC is Active.

Since the PHY IPs don't contain isolation logic built in the design to
allow the power rail to be switched off, there is a very high risk
of IP reliability and additional leakage paths which can result in
additional power consumption.

The only scenario where this rail can be switched off is part of Power on
reset sequencing, but it needs to be kept always-on during operation.

This patch is required for proper functionality of USB, SATA
and PCIe on DRA7-evm.

CC: Rajendra Nayak <rnayak@ti.com>
CC: Tero Kristo <t-kristo@ti.com>
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

pwm-cells should be 3. Third cell is optional PWM flags. And This flag
supported by this binding is PWM_POLARITY_INVERTED.
Signed-off-by: NJaewon Kim <jaewon02.kim@samsung.com>
Reviewed-by: NSachin Kamat <sachin.kamat@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Without the patch:
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div/l4_root_clk_div # cat clk_rate
532000000

With the patch:
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate
266000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div/l4_root_clk_div # cat clk_rate
133000000

The l3 clock derived from core DPLL is actually a divider clock,
with the default divider set to 2. l4 then derived from l3 is a fixed factor
clock, but the fixed divider is 2 and not 1. Which means the l3 clock is
half of core DPLLs h12x2 and l4 is half of l3 (as seen with this patch)
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>

The at91sam9261 doesn't actually have a slow RC oscillator, remove it from the
dtsi.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Define at91sam9261ek's slow crystal frequencies.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

mainck (CKGR_MCFR register) is actually using main_osc (CKGR_MOR register).
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

ICPLL can only take 0 or 1, it got mixed with OUT which can be in the [0-3]
range.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

ICPLL can only take 0 or 1, it got mixed with OUT which can be in the [0-3]
range.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Wildcards in compatible strings should be avoid. "marvell,armada38x"
was recently introduced but was not yet used.

The armada 385 SoC is a superset of the armada 380 SoC (with more CPUs
and more PCIe slots). So this patch replaces the use of
"marvell,armada38x" by the "marvell,armada380" string.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1403533011-21339-1-git-send-email-gregory.clement@free-electrons.comAcked-by: NAndrew Lunn <andrew@lunn.ch>
Cc: <stable@vger.kernel.org> # v3.15+
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Commit eeb84545
 ("ARM: dts: kirkwood: set Guruplug phy-connection-type to rgmii-id")
added phy-connection-type properties to ethernet PHY nodes.

Actually, the property has to be set for the ethernet port node instead.
Fix it by moving the corresponding properties to the correct nodes.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1403555115-13111-1-git-send-email-sebastian.hesselbarth@gmail.com
Fixes: eeb84545: ('ARM: dts: kirkwood: set Guruplug phy-connection-type to rgmii-id')
Cc: <stable@vger.kernel.org> # v3.16+
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Peach-pit and Peach-pi boards are almost similar, hence the DTS file
is also very similar. Sorting nodes in both these files will allow
us to figure out the difference easily.

All the node aliases are sorted in alphabetically increasing order.
There is no functional change with this patch.
Signed-off-by: NTushar Behera <tushar.b@samsung.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Peach-pi board has MAX98091 audio codec connected on HSI2C-7 bus.
Signed-off-by: NTushar Behera <tushar.b@samsung.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The following commit:
89d7e5c1 mmc: sdhci-esdhc-imx: add runtime pm support
has the effect of also disabling the hardware card detect
in runtime pm.

We switch to GPIO based detection to avoid this issue.

This patch is based on:
ARM: dts: imx51-babbage: Fix esdhc setup
Signed-off-by: NDenis Carikli <denis@eukrea.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>