- 28 11月, 2012 6 次提交
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由 Borislav Petkov 提交于
Instead of open-coding it, use the DBAM_DIMM macro in amd64_csrow_nr_pages() which we have already. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
This basically reverts 603adaf6 ("amd64_edac: fix K8 chip select reporting") because it was a clumsy workaround for DIMM sizes reporting on K8 which got superceded by a much more correct one with 41d8bfab ("amd64_edac: Improve DRAM address mapping") without removing the prior one. Remove it now finally. Reported-by: NJosh Hunt <johunt@akamai.com> Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
Rewrite CE/UE paths so that they use the same code and drop additional code duplication in handle_ue. Add a struct err_info which collects required info for the error reporting. This, in turn, helps slimming all edac_mc_handle_error() calls down to one. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
All families report a valid error address when encountering a DRAM ECC error so no need to check it. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
When injecting DRAM ECC errors over the F3xB[8,C] interface, the machine does this by injecting the error in the next non-cached access. This takes relatively long time on a normal system so that in order for us to expedite it, we disable the caches around the injection. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
amd64_get_dram_hole_info: remove local variable 'base'. sys_addr_to_dram_addr: do not clear local variable 'ret'. Also, sanitize constants formatting. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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- 24 10月, 2012 1 次提交
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由 Andrew Morton 提交于
If none of the elements in scrubrates[] matches, this loop will cause __amd64_set_scrub_rate() to incorrectly use the n+1th element. As the function is designed to use the final scrubrates[] element in the case of no match, we can fix this bug by simply terminating the array search at the n-1th element. Boris: this code is fragile anyway, see here why: http://marc.info/?l=linux-kernel&m=135102834131236&w=2 It will be rewritten more robustly soonish. Reported-by: NDenis Kirjanov <kirjanov@gmail.com> Cc: stable@vger.kernel.org Cc: Doug Thompson <dougthompson@xmission.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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- 12 6月, 2012 6 次提交
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由 Mauro Carvalho Chehab 提交于
In order to avoid loosing error events, it is desirable to group error events together and generate a single trace for several identical errors. The trace API already allows reporting multiple errors. Change the handle_error function to also allow that. The changes at the drivers were made by this small script: $file .=$_ while (<>); $file =~ s/(edac_mc_handle_error)\s*\(([^\,]+)\,([^\,]+)\,/$1($2,$3, 1,/g; print $file; Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
Remove the arch-dependent parameter, as it were not used, as the MCE tracepoint weren't implemented. It probably doesn't make sense to have an MCE-specific tracepoint, as this will cost more bytes at the tracepoint, and tracepoint is not free. The changes at the EDAC drivers were done by this small perl script: $file .=$_ while (<>); $file =~ s/(edac_mc_handle_error)\s*\(([^\;]+)\,([^\,\)]+)\s*\)/$1($2)/g; print $file; Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
The EDAC driver name doesn't help to handle EDAC errors. So, remove it from the EDAC error messages, preserving only the error_message. Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Joe Perches 提交于
Use a more common debugging style. Remove __FILE__ uses, add missing newlines, coalesce formats and align arguments. Signed-off-by: NJoe Perches <joe@perches.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
Kernel kobjects have rigid rules: each container object should be dynamically allocated, and can't be allocated into a single kmalloc. EDAC never obeyed this rule: it has a single malloc function that allocates all needed data into a single kzalloc. As this is not accepted anymore, change the allocation schema of the EDAC *_info structs to enforce this Kernel standard. Acked-by: NChris Metcalf <cmetcalf@tilera.com> Cc: Aristeu Rozanski <arozansk@redhat.com> Cc: Doug Thompson <norsk5@yahoo.com> Cc: Greg K H <gregkh@linuxfoundation.org> Cc: Borislav Petkov <borislav.petkov@amd.com> Cc: Mark Gross <mark.gross@intel.com> Cc: Tim Small <tim@buttersideup.com> Cc: Ranganathan Desikan <ravi@jetztechnologies.com> Cc: "Arvind R." <arvino55@gmail.com> Cc: Olof Johansson <olof@lixom.net> Cc: Egor Martovetsky <egor@pasemi.com> Cc: Michal Marek <mmarek@suse.cz> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Hitoshi Mitake <h.mitake@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
Now that the EDAC core supports struct device, there's no sense on having any logic at the EDAC core to simulate it. So, instead of adding such logic there, change the logic at amd64_edac to use it. Reviewed-by: NAristeu Rozanski <arozansk@redhat.com> Cc: Doug Thompson <norsk5@yahoo.com> Cc: Borislav Petkov <borislav.petkov@amd.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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- 11 6月, 2012 1 次提交
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由 Mauro Carvalho Chehab 提交于
As EDAC doesn't use struct device itself, it created a parent dev pointer called as "pdev". Now that we'll be converting it to use struct device, instead of struct devsys, this needs to be fixed. No functional changes. Reviewed-by: NAristeu Rozanski <arozansk@redhat.com> Acked-by: NChris Metcalf <cmetcalf@tilera.com> Cc: Doug Thompson <norsk5@yahoo.com> Cc: Borislav Petkov <borislav.petkov@amd.com> Cc: Mark Gross <mark.gross@intel.com> Cc: Jason Uhlenkott <juhlenko@akamai.com> Cc: Tim Small <tim@buttersideup.com> Cc: Ranganathan Desikan <ravi@jetztechnologies.com> Cc: "Arvind R." <arvino55@gmail.com> Cc: Olof Johansson <olof@lixom.net> Cc: Egor Martovetsky <egor@pasemi.com> Cc: Michal Marek <mmarek@suse.cz> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Joe Perches <joe@perches.com> Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Hitoshi Mitake <h.mitake@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Josh Boyer <jwboyer@gmail.com> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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- 29 5月, 2012 5 次提交
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由 Mauro Carvalho Chehab 提交于
Now that all drivers got converted to use the new ABI, we can drop the old one. Acked-by: NChris Metcalf <cmetcalf@tilera.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
The legacy edac ABI is going to be removed. Port the driver to use and benefit from the new API functionality. Cc: Doug Thompson <norsk5@yahoo.com> Cc: Borislav Petkov <borislav.petkov@amd.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
The number of pages is a dimm property. Move it to the dimm struct. After this change, it is possible to add sysfs nodes for the DIMM's that will properly represent the DIMM stick properties, including its size. A TODO fix here is to properly represent dual-rank/quad-rank DIMMs when the memory controller represents the memory via chip select rows. Reviewed-by: NAristeu Rozanski <arozansk@redhat.com> Acked-by: NBorislav Petkov <borislav.petkov@amd.com> Acked-by: NChris Metcalf <cmetcalf@tilera.com> Cc: Doug Thompson <norsk5@yahoo.com> Cc: Mark Gross <mark.gross@intel.com> Cc: Jason Uhlenkott <juhlenko@akamai.com> Cc: Tim Small <tim@buttersideup.com> Cc: Ranganathan Desikan <ravi@jetztechnologies.com> Cc: "Arvind R." <arvino55@gmail.com> Cc: Olof Johansson <olof@lixom.net> Cc: Egor Martovetsky <egor@pasemi.com> Cc: Michal Marek <mmarek@suse.cz> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Joe Perches <joe@perches.com> Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Hitoshi Mitake <h.mitake@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Josh Boyer <jwboyer@gmail.com> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
Almost all edac drivers initialize csrow_info->first_page, csrow_info->last_page and csrow_info->page_mask. Those vars are used inside the EDAC core, in order to calculate the csrow affected by an error, by using the routine edac_mc_find_csrow_by_page(). However, very few drivers actually use it: e752x_edac.c e7xxx_edac.c i3000_edac.c i82443bxgx_edac.c i82860_edac.c i82875p_edac.c i82975x_edac.c r82600_edac.c There also a few other drivers that have their own calculus formula internally using those vars. All the others are just wasting time by initializing those data. While initializing data without using them won't cause any troubles, as those information is stored at the wrong place (at csrows structure), it is better to remove what is unused, in order to simplify the next patch. Reviewed-by: NAristeu Rozanski <arozansk@redhat.com> Acked-by: NBorislav Petkov <borislav.petkov@amd.com> Acked-by: NChris Metcalf <cmetcalf@tilera.com> Cc: Doug Thompson <norsk5@yahoo.com> Cc: Hitoshi Mitake <h.mitake@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com> Cc: Josh Boyer <jwboyer@gmail.com> Cc: Jiri Kosina <jkosina@suse.cz> Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
On systems based on chip select rows, all channels need to use memories with the same properties, otherwise the memories on channels A and B won't be recognized. However, such assumption is not true for all types of memory controllers. Controllers for FB-DIMM's don't have such requirements. Also, modern Intel controllers seem to be capable of handling such differences. So, we need to get rid of storing the DIMM information into a per-csrow data, storing it, instead at the right place. The first step is to move grain, mtype, dtype and edac_mode to the per-dimm struct. Reviewed-by: NAristeu Rozanski <arozansk@redhat.com> Reviewed-by: NBorislav Petkov <borislav.petkov@amd.com> Acked-by: NChris Metcalf <cmetcalf@tilera.com> Cc: Doug Thompson <norsk5@yahoo.com> Cc: Borislav Petkov <borislav.petkov@amd.com> Cc: Mark Gross <mark.gross@intel.com> Cc: Jason Uhlenkott <juhlenko@akamai.com> Cc: Tim Small <tim@buttersideup.com> Cc: Ranganathan Desikan <ravi@jetztechnologies.com> Cc: "Arvind R." <arvino55@gmail.com> Cc: Olof Johansson <olof@lixom.net> Cc: Egor Martovetsky <egor@pasemi.com> Cc: Michal Marek <mmarek@suse.cz> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Joe Perches <joe@perches.com> Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Hitoshi Mitake <h.mitake@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: James Bottomley <James.Bottomley@parallels.com> Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Josh Boyer <jwboyer@gmail.com> Cc: Mike Williams <mike@mikebwilliams.com> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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- 19 3月, 2012 3 次提交
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由 Lionel Debroux 提交于
These const tables are currently marked __devinitdata, but Documentation/PCI/pci.txt says: "o The ID table array should be marked __devinitconst; this is done automatically if the table is declared with DEFINE_PCI_DEVICE_TABLE()." So use DEFINE_PCI_DEVICE_TABLE(x). Based on PaX and earlier work by Andi Kleen. Signed-off-by: NLionel Debroux <lionel_debroux@yahoo.fr> Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
Fix DRAM chip select sizes calculation for K8, revisions D and E. Reported-by: Niklas Söderlund <niklas.soderlund@ericsson.com Link: http://lkml.kernel.org/r/1320849178-23340-1-git-send-email-niklas.soderlund@ericsson.comSigned-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Ashish Shenoy 提交于
While initializing the array of csrow attribute instances, a few csrows were uninitialized. This happened because the module only performed a check for DRAM base ctl register0's and not DRAM base ctl register1's chip select enable bit. There could be systems with DIMMs populated on only single memory channel whereas the module also assumed that a dual channel dimm had double the memory size of a single memory channel instead of checking the memory on each channel. This patch fixes these above issues. Signed-off-by: NAshish Shenoy <ashenoy@riverbed.com> Signed-off-by: NPrasanna S. Panchamukhi <ppanchamukhi@riverbed.com> Link: http://lkml.kernel.org/r/4F459CFA.5090604@riverbed.comSigned-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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- 06 10月, 2011 3 次提交
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由 Dan Carpenter 提交于
Sparse complains that edac_cap was declared as dev_type and we are returning edac_type. Historically, edac_type was correct but since then we have changed it to return a bit field. Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com> Link: http://lkml.kernel.org/r/20111006063025.GA2615@mwandaSigned-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
When accessing the scrub rate control register (F3x58) on F15h, the DRAM controller selector (F1x10C[DctCfgSel]) has to point to DCT0 so that the scrub rate configuration can take effect. See Erratum 505 in the AMD F15h revision guide for more details. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
Drop third nbcfg argument which is old remains and not required anymore. No functionality change. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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- 26 4月, 2011 3 次提交
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由 Borislav Petkov 提交于
F15h CPUs may report a non-DRAM address when reporting an error address belonging to a CC6 state save area. Add a workaround to detect this condition and compute the actual DRAM address of the error as documented in the Revision Guide for AMD Family 15h Models 00h-0Fh Processors. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
F15h and later use a portion of DRAM as a CC6 storage area. BIOS programs D18F1x[17C:140,7C:40] DRAM Base/Limit accordingly by subtracting the storage area from the DRAM limit setting. However, in order for edac to consider that part of DRAM too, we need to include it into the per-node range. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
This warning was wrongfully added for a normal condition - intlvsel actually selects the destination node when node interleaving is enabled and it is not a mismatch. For a detailed example, see section 2.8.10.2 "Node Interleaving" in F10h BKDG. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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- 21 4月, 2011 1 次提交
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由 Markus Trippelsdorf 提交于
This patch removes superfluous debugging output in the sysfs scrub rate handler. It also consolidates the error handling in the scrub rate accessors. Signed-off-by: NMarkus Trippelsdorf <markus@trippelsdorf.de> Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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- 30 3月, 2011 1 次提交
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由 Borislav Petkov 提交于
We check the pointers together but at least one of them could be invalid due to failed allocation. Since we cannot continue if either of the two allocations has failed, exit early by freeing them both. Cc: <stable@kernel.org> # 38.x Reported-by: NMauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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- 17 3月, 2011 10 次提交
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由 Borislav Petkov 提交于
Those should all be unsigned. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
Fix amd64_debug_display_dimm_sizes() arguments order per convention (pvt is always first). Also, the now second arg denotes the DCT so adjust its type. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
The dram ranges make sense only as an unsigned type. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
Use the macro directly instead Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
Adjust argument types to the PCI config API's types. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
Return unsigned u8 values only. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
A node id can never be negative since we use it as an index into the DRAM ranges array. This also makes one of the BUG_ON conditions redundant. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
Add the PCI device ids required for driver registration. Remove pvt->ctl_name and use the family descriptor directly, instead. Then, bump driver version and fixup its format. Finally, enable DRAM ECC decoding on F15h. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
F15h has the same ECC symbol size options as F10h revD and later so adjust checks to that. Simplify code a bit. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 Borislav Petkov 提交于
Drop per-instance variable and compute min scrubrate dynamically. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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