- 05 2月, 2013 2 次提交
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由 Patrice Chotard 提交于
Add AB9540 sub driver to the ABx500 family, pins, pin groups and gpio range. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by: NOlof Johansson <olof@lixom.net> Signed-off-by: NPatrice Chotard <patrice.chotard@stericsson.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Patrice Chotard 提交于
Add AB8505 sub driver to the ABx5x family. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by: NOlof Johansson <olof@lixom.net> Signed-off-by: NPatrice Chotard <patrice.chotard@stericsson.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 31 1月, 2013 2 次提交
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由 Patrice Chotard 提交于
This adds a subdriver for the AB8500 pinctrl portions. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by: NOlof Johansson <olof@lixom.net> Reviewed-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NPatrice Chotard <patrice.chotard@st.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Patrice Chotard 提交于
This adds the AB8500 core driver, which will be utilized by the follow-on drivers for different ABx500 variants. Sselect the driver from the DBX500_SOC, as this chip is powering and clocking that SoC. Cc: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: NPatrice Chotard <patrice.chotard@st.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 19 1月, 2013 1 次提交
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由 Kukjin Kim 提交于
Since pinctrl-exynos can support exynos4 and exynos5 so changed the option name to PINCTRL_EXYNOS for more clarity. Cc: Thomas Abraham <Thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 18 1月, 2013 1 次提交
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由 Pritesh Raithatha 提交于
This adds a driver for the Tegra114 pinmux, and required parameterization data for Tegra114. The driver uses the common Tegra pincontrol driver utility functions to implement the majority of the driver. This driver is not compatible with the earlier NVIDIA's SoCs, hence add new compatibile as "nvidia,tegra114-pinmux". Originally written by Pritesh. ldewangan: - cleanup the patches, - remove non-require tables. - Use module_platform_driver() for driver registartion. Signed-off-by: NPritesh Raithatha <praithatha@nvidia.com> Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 02 12月, 2012 1 次提交
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由 Axel Lin 提交于
These drivers do not need to select PINCONF. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 22 11月, 2012 1 次提交
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由 Thomas Abraham 提交于
Add a new pinctrl driver for Samsung EXYNOS5440 SoC. The pin controller module in EXYNOS5440 is different from the pin controller found on other Samsung SoC. Hence, the pin controller driver for EXYNOS5440 SoC is independent of the Samsung pinctrl framework. Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 15 11月, 2012 2 次提交
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由 Arnd Bergmann 提交于
The main samsung pinctrl module references the specific exynos4210 pinctrl driver, which selects the main driver in Kconfig. Making the main driver a silent "bool" option avoid this potential build error if CONFIG_PINCTRL_SAMSUNG=y && CONFIG_PINCTRL_EXYNOS4=n: drivers/built-in.o:(.rodata+0x4e4): undefined reference to `exynos4210_pin_ctrl' Signed-off-by: NArnd Bergmann <arnd@arndb.de> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Axel Lin 提交于
Then we can remove "select PINMUX && PINCONF" from PINCTRL_TEGRA{20,30}. This simplifies the dependency. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 13 11月, 2012 1 次提交
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由 Axel Lin 提交于
Then we can remove "select PINMUX && PINCONF" from PINCTRL_IMX{23,28}. This simplifies the dependency. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 12 11月, 2012 3 次提交
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由 Barry Song 提交于
The driver supports old up SiRFprimaII SoCs, this patch makes it support the new SiRFmarco as well. SiRFmarco, as a SMP SoC, adds new SIRFSOC_GPIO_PAD_EN_CLR registers, to disable GPIO pad, we should write 1 to the corresponding bit in the new CLEAR register instead of writing 0 to SIRFSOC_GPIO_PAD_EN. Signed-off-by: NBarry Song <Baohua.Song@csr.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Thomas Petazzoni 提交于
Like the spear platform, the mvebu platform has multiple files: one core file, and then one file per SoC family. More files will be added later, as support for mach-orion5x and mach-mv78xx0 SoCs is added to pinctrl-mvebu. For those reasons, having a separate subdirectory, drivers/pinctrl/mvebu/ makes sense, and it had already been suggested by Linus Wallej when the driver was originally submitted. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Thomas Petazzoni 提交于
The mach-kirkwood and mach-dove architectures have not yet been integrated into the mach-mvebu directory, which should ultimately contain the support for all Marvell SoCs from the Engineering Business Unit. However, before this can happen, we need to let mach-kirkwood and mach-dove use the pinctrl-mvebu driver, which supports the kirkwood and dove SoC families. In order to do that, we make this driver available as soon as PLAT_ORION is selected, instead of using ARCH_MVEBU as a condition. In the long term, PLAT_ORION should disappear and be fully replaced by ARCH_MVEBU, but the plan is to make the migration step by step, by first having the existing mach-* directories for Marvell SoCs converge on several infrastructures, including the pinctrl one. Also, like the spear pinctrl driver, we put all pinctrl-mvebu Kconfig options under a if, in order to avoid having certain options (PINCTRL_DOVE, PINCTRL_KIRKWOOD, etc.) selecting an option (PINCTLR_MVEBU) which itself has a dependency (on ARCH_MVEBU). In this a construct, the dependency is in fact ignored due to the selects. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 06 11月, 2012 1 次提交
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由 Axel Lin 提交于
This patch fixes below build error when !CONFIG_OF_GPIO. CC drivers/pinctrl/pinctrl-samsung.o drivers/pinctrl/pinctrl-samsung.c: In function 'samsung_pinctrl_parse_dt_pins': drivers/pinctrl/pinctrl-samsung.c:557:19: warning: unused variable 'prop' [-Wunused-variable] drivers/pinctrl/pinctrl-samsung.c: In function 'samsung_gpiolib_register': drivers/pinctrl/pinctrl-samsung.c:797:5: error: 'struct gpio_chip' has no member named 'of_node' make[2]: *** [drivers/pinctrl/pinctrl-samsung.o] Error 1 make[1]: *** [drivers/pinctrl] Error 2 make: *** [drivers] Error 2 The samsung pinctrl driver supports only device tree enabled platforms. Thus make PINCTRL_SAMSUNG depend on OF && GPIOLIB. The reason to depend on GPIOLIB is CONFIG_OF_GPIO only available when GPIOLIB is selected. Since PINCTRL_EXYNOS4 select PINCTRL_SAMSUNG, thus also make PINCTRL_EXYNOS4 depend on OF && GPIOLIB. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 13 10月, 2012 1 次提交
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This is also include the gpio controller as the IP share both. Each soc will have to describe the SoC limitation and pin configuration via DT. This will allow to do not need to touch the C code when adding new SoC if the IP version is supported. Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- 01 10月, 2012 1 次提交
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由 Simon Arlott 提交于
The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt controller, and pinmux/control device. Original driver by Simon Arlott. Rewrite including GPIO chip device by Chris Boot. Upstreaming changes by Stephen Warren: * Wrote DT binding documentation. * Changed brcm,function to an integer to more directly match the datasheet, and to match brcm,pins being an integer. * Implemented pull-up/down pin config. * Removed read-only DT property and related code. The restriction this implemented are driven by the board, not the GPIO HW block, so don't really make sense of a HW block binding, were in general incomplete (since they could only know about the few pins hard-coded into the Raspberry Pi B board design and not the uncommitted GPIOS), and are better represented simply by not writing incorrect data into pin configuration nodes. * Don't set GPIO_IN function select in gpio_request_enable() to avoid glitches; defer this to gpio_set_direction(). Consequently, removed empty bcm2835_pmx_gpio_request_enable(). * Simplified enabled_irq_map[]; make it explicitly 1 entry per bank. * Lifted use of enabled_irq_map[] outside the per-interrupt loop in IRQ handler, thus fixing an issue where the code was indexing into enabled_irq_map[] by intra-bank GPIO ID, not global GPIO ID. * Removed locking in IRQ handler, since all other code uses spin_lock_irqsave() and so guarantees it doesn't run concurrently with the handler. * Moved duplicated BUILD_BUG_ON()s into probe(). Also check size of bcm2835_gpio_pins[]. * Remove range-checking from bcm2835_pctl_get_groups_count() since we've decided to trust the pinctrl core. * Made bcm2835_pmx_gpio_disable_free() call bcm2835_pinctrl_fsel_set() directly for simplicity. * Fixed body of dt_free_map() to match latest dt_node_to_map(). * Removed GPIO ownership check from bcm2835_pmx_enable() since the pinctrl core owns doing this. * Made irq_chip and pinctrl_gpio_range .name == MODULE_NAME so it's more descriptive. * Simplified remove(); removed call to non-existent pinctrl_remove_gpio_range(), remove early return on error. * Don't force gpiochip's base to 0. Set gpio_range.base to gpiochip's base GPIO number. * Error-handling cleanups in probe(). * Switched to module_platform_driver() rather than open-coding. * Made pin, group, and function names lower-case. * s/broadcom/brcm/ in DT property names. * s/2708/2835/. * Fixed a couple minor checkpatch warnings, and other minor cleanup. Signed-off-by: NSimon Arlott <simon@fire.lp0.eu> Signed-off-by: NChris Boot <bootc@bootc.net> Signed-off-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 22 9月, 2012 5 次提交
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由 Thomas Petazzoni 提交于
This pinctrl driver is not a full-blown pinctrl driver from scratch: it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
This pinctrl driver is not a full-blown pinctrl driver from scratch: it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Sebastian Hesselbarth 提交于
This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core. Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: NStephen Warren <swarren@wwwdotorg.org> Tested-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Sebastian Hesselbarth 提交于
This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core. Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Sebastian Hesselbarth 提交于
This patch adds a pinctrl driver core for Marvell SoCs plus DT binding documentation. This core driver will be used by SoC family specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso. Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net> Conflicts: arch/arm/Kconfig
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- 13 9月, 2012 2 次提交
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由 John Crispin 提交于
Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks of up to 32 pins. Signed-off-by: NJohn Crispin <blogic@openwrt.org> Signed-off-by: NThomas Langer <thomas.langer@lantiq.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org
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由 John Crispin 提交于
Implement support for pinctrl on lantiq/xway socs. The IO core found on these socs has the registers for pinctrl, pinconf and gpio mixed up in the same register range. As the gpio_chip handling is only a few lines, the driver also implements the gpio functionality. This obseletes the old gpio driver that was located in the arch/ folder. Signed-off-by: NJohn Crispin <blogic@openwrt.org> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org
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- 07 9月, 2012 2 次提交
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由 Thomas Abraham 提交于
Add information about the Exynos4210 pin banks and driver data which is used by the Samsung pinctrl driver. In addition to this, the support for external gpio and wakeup interrupt support is included and hooked up with the Samsung pinctrl driver. Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Thomas Abraham 提交于
Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 03 9月, 2012 3 次提交
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由 Uwe Kleine-König 提交于
This is mostly cut'n'paste from the imx51 pinctrl driver. The data was generated using sed and awk on arch/arm/plat-mxc/include/mach/iomux-mx35.h. Changes since (implicit) v1 - remove references to file names in binding documentation - remove sed commands from comments in driver - add explicit numbers for pins and functions Acked-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Acked-by: NDong Aisheng <dong.aisheng@linaro.org> Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
This adds support for the STN8815 ASIC for the Nomadik pin controller. Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Patrice Chotard 提交于
This implements a subdriver for the DB8540 ASIC for the Nomadik pin controller. Signed-off-by: NPatrice Chotard <patrice.chotard@stericsson.com> Reviewed-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 15 7月, 2012 1 次提交
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由 Tony Lindgren 提交于
Add one-register-per-pin type device tree based pinctrl driver. This driver has been tested on omap2+ series of processors, where there is either an 8 or 16-bit padconf register for each pin. Support for other similar pinmux controllers can be added. Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 04 7月, 2012 1 次提交
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由 Linus Walleij 提交于
The Kconfig entry for the COH901 pin controller depended on PINMUX_U300 which is stale, use PINCTRL_U300 as it is called these days. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 21 5月, 2012 2 次提交
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由 Dong Aisheng 提交于
ChangeLog v1->v2: * change PIN_FUNC_ID base in binding doc to 0 from 1. Acked-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Dong Aisheng 提交于
ChangeLog v1->v2: * change PIN_FUNC_ID base in binding doc to 0 from 1. Acked-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 15 5月, 2012 1 次提交
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由 Arnd Bergmann 提交于
The nomadik gpio code has been converted to pinctrl, but the nomadik platform still expects the old code to be present. Change it to use the new one instead. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
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- 11 5月, 2012 3 次提交
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由 Linus Walleij 提交于
This implements the pin configuration interface for the Nomadik pin controller. As part of the exercise we add a bit in the pin_cfg_t for the Nomadik pinctrl driver that indicates if the pin should be forced into GPIO mode. This is not done to go behind the back of the GPIO subsystem, but to ensure that default modes can be set by hogs on boot and system suspend/resume states. It was used implicitly by the old code defining all config settings and modes in a single config word but we now have a split between pinmux and pinconf leading to the need to have this. We also add a bit for explicitly setting sleepmode of the pin. This was previously handled by custom calls with the _sleep() suffix, but we now have one single interface into the configuration so we replace this with a bit indicating that the pin shall be configured into sleep mode. Some of the configuration can be refactored later to use less custom fields on the pin_cfg_t but we are currently leaving the old function calls in place so we stay compatible. ChangeLog v1->v2: - Drop a hunk changing pinmuxing for GPIO and move it over to the preceding pinmux patch. Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
Implements basic pinmux for the Nomadik pin controller. The plan is to split the existing singular pin config interface nmk_config_pin(), nmk_config_pins(), that will configure muxing and other settings at the same time, into two interfaces by splitting the code in pinmux and pinctrl and eventually deleting the old interface and its helper functions when all users are gone. nmk_gpio_set_mode() and nmk_gpio_get_mode() are two older interfaces for just configuring muxing/altfunctions that will also be replaced in the end. We take some extra care to handle the glitch-avoidance here, but it is simpler now since there is only one altsetting per pingroup so we know immediately if we need to avoid altfunc C glitches for a certain group. As part of the makeover implement the .request() and .free() calls on the GPIO chips and have them call back into the pinctrl layer to reserve GPIOs. ChangeLog v1->v2: - Rebased on pinctrl-mergebase-20120418 so we get the latest driver infrastructure where function count is done by a fixed value and we can drop a few range checks since this is now handled by the core. - Include a GPIO muxing hunk erroneously part of the pin config patch. Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
This adds a scratch pin control interface to the Nomadik pinctrl driver, and defines the pins and groups in the DB8500 ASIC. We define GPIO ranges to cover the pins exposed. The DB8500 has more pins than this but we restrict the driver to the pins that can be controlled from the combined GPIO and pin control hardware to begin with. ChangeLog v1->v2: - Base on the latest pinctrl development from pinctrl-mergebase-20120418 so we can get rid of legacy group count mechanism. Also drop the range checks for group index, this is handled by the core now. Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 02 5月, 2012 3 次提交
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由 Shawn Guo 提交于
Add pinctrl support for Freescale MXS SoCs, i.MX23 and i.MX28. The driver supports device tree probe only. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Dong Aisheng 提交于
Acked-by: NStephen Warren <swarren@wwwdotorg.org> Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Dong Aisheng 提交于
The driver has mux and config support while the gpio is still not supported. For select input setting, the driver will handle it internally and do not need user to take care of it. The pinctrl-imx core driver will parse the dts file and dynamically create the pinmux functions and groups. Each IMX SoC pinctrl driver should register pins with a pin register map including mux register and config register and select input map to core for proper operations. Acked-by: NStephen Warren <swarren@wwwdotorg.org> Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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