1. 27 9月, 2013 2 次提交
  2. 10 7月, 2013 1 次提交
  3. 13 6月, 2013 1 次提交
  4. 23 5月, 2013 1 次提交
  5. 08 4月, 2013 1 次提交
  6. 15 1月, 2013 1 次提交
  7. 25 12月, 2012 1 次提交
  8. 22 11月, 2012 2 次提交
  9. 19 9月, 2012 1 次提交
    • A
      ARM: ixp4xx: use __iomem pointers for MMIO · 13ec32f4
      Arnd Bergmann 提交于
      ARM is moving to stricter checks on readl/write functions,
      so we need to use the correct types everywhere.
      
      At the moment, this patch conflicts with other patches in linux-next,
      need to sort this out.
      
      Cc: Imre Kaloz <kaloz@openwrt.org>
      Cc: Krzysztof Halasa <khc@pm.waw.pl>
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      13ec32f4
  10. 24 5月, 2012 1 次提交
  11. 31 3月, 2012 1 次提交
    • O
      ARM: fix builds due to missing <asm/system_misc.h> includes · 86dfe446
      Olof Johansson 提交于
      This does a sweeping change fixing up all the missing system_misc.h and
      system_info.h includes from the system.h split-up change. These were the
      ones I came across when building all defconfigs in arch/arm/configs, there
      might be more but they lack adequate build coverage to be easily caught.
      
      I'm expecting to get a lot of these piecemeal by each maintainer, so we
      might just as well do one sweeping change to get them all at once.
      
      Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Sascha Hauer <kernel@pengutronix.de>
      Cc: Imre Kaloz <kaloz@openwrt.org>
      Cc: Krzysztof Halasa <khc@pm.waw.pl>
      Cc: Eric Miao <eric.y.miao@gmail.com>
      Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
      Cc: Wan ZongShun <mcuos.com@gmail.com>
      Acked-by: NKukjin Kim <kgene.kim@samsung.com>
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      86dfe446
  12. 07 3月, 2012 1 次提交
  13. 21 1月, 2012 1 次提交
  14. 05 1月, 2012 1 次提交
  15. 19 12月, 2011 1 次提交
  16. 01 11月, 2011 1 次提交
  17. 16 7月, 2011 1 次提交
  18. 24 5月, 2011 1 次提交
  19. 29 3月, 2011 2 次提交
  20. 06 2月, 2011 1 次提交
  21. 14 1月, 2011 1 次提交
  22. 23 12月, 2010 3 次提交
  23. 15 5月, 2010 1 次提交
  24. 28 1月, 2010 1 次提交
  25. 05 12月, 2009 1 次提交
  26. 22 9月, 2009 1 次提交
    • M
      ixp4xx: timer and clocks cleanups · ceb69a89
      Mikael Pettersson 提交于
      This patch does a few simple cleanups of the ixp4xx timer
      and clocksource/clockevent code in mach-ixp4xx/common.c:
      
      - ixp4xx_clocksource_init() is static and always returns 0,
        which is ignored by its only caller: make it return void
      - ixp4xx_clockevent_init(): ditto
      - ixp4xx_get_cycles() is only referenced locally: make it static
      - use the ixp4xx_timer_irq.dev_id field to pass &clockevent_ixp4xx
        to ixp4xx_timer_interrupt() via its dev_id parameter, allowing
        the code in ixp4xx_timer_interrupt() to be smaller and faster
      
      Tested on an ixp420 machine (ds101).
      Signed-off-by: NMikael Pettersson <mikpe@it.uu.se>
      Signed-off-by: NKrzysztof Hałasa <khc@pm.waw.pl>
      ceb69a89
  27. 07 9月, 2009 1 次提交
    • K
      IXP42x HSS support for setting internal clock rate · 5dbc4650
      Krzysztof Halasa 提交于
      HSS usually uses external clocks, so it's not a big deal. Internal clock
      is used for direct DTE-DTE connections and when the DCE doesn't provide
      it's own clock.
      
      This also depends on the oscillator frequency. Intel seems to have
      calculated the clock register settings for 33.33 MHz (66.66 MHz timer
      base). Their settings seem quite suboptimal both in terms of average
      frequency (60 ppm is unacceptable for G.703 applications, their primary
      intended usage(?)) and jitter.
      
      Many (most?) platforms use a 33.333 MHz oscillator, a 10 ppm difference
      from Intel's base.
      
      Instead of creating static tables, I've created a procedure to program
      the HSS clock register. The register consists of 3 parts (A, B, C).
      The average frequency (= bit rate) is:
      66.66x MHz / (A  + (B + 1) / (C + 1))
      The procedure aims at the closest average frequency, possibly at the
      cost of increased jitter. Nobody would be able to directly drive an
      unbufferred transmitter with a HSS anyway, and the frequency error is
      what it really counts.
      
      I've verified the above with an oscilloscope on IXP425. It seems IXP46x
      and possibly IXP43x use a bit different clock generation algorithm - it
      looks like the avg frequency is:
      (on IXP465) 66.66x MHz / (A  + B / (C + 1)).
      Also they use much greater precomputed A and B - on IXP425 it would
      simply result in more jitter, but I don't know how does it work on
      IXP46x (perhaps 3 least significant bits aren't used?).
      
      Anyway it looks that they were aiming for exactly +60 ppm or -60 ppm,
      while <1 ppm is typically possible (with a synchronized clock, of
      course).
      
      The attached patch makes it possible to set almost any bit rate
      (my IXP425 533 MHz quits at > 22 Mb/s if a single port is used, and the
      minimum is ca. 65 Kb/s).
      
      This is independent of MVIP (multi-E1/T1 on one HSS) mode.
      Signed-off-by: NKrzysztof Hałasa <khc@pm.waw.pl>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5dbc4650
  28. 22 4月, 2009 1 次提交
  29. 13 12月, 2008 1 次提交
  30. 06 9月, 2008 1 次提交
  31. 07 8月, 2008 2 次提交
  32. 27 7月, 2008 1 次提交
  33. 10 7月, 2008 1 次提交
  34. 18 12月, 2007 1 次提交