- 02 2月, 2016 11 次提交
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由 Jon Hunter 提交于
If the pll_u is not configured by the bootloader, then on kernel boot the following warning is seen: clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock tegra_init_from_table: Failed to enable pll_u_out1 ------------[ cut here ]------------ WARNING: at drivers/clk/tegra/clk.c:269 Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.0-rc4-next-20151214+ #1 Hardware name: NVIDIA Tegra210 P2371 reference board (E.1) (DT) task: ffffffc0bc0a0000 ti: ffffffc0bc0a8000 task.ti: ffffffc0bc0a8000 PC is at tegra_init_from_table+0x140/0x164 LR is at tegra_init_from_table+0x140/0x164 pc : [<ffffffc0008fee78>] lr : [<ffffffc0008fee78>] pstate: 80000045 sp : ffffffc0bc0abd50 x29: ffffffc0bc0abd50 x28: ffffffc00090b8a8 x27: ffffffc000a06000 x26: ffffffc0bc019780 x25: ffffffc00086a708 x24: ffffffc00086a790 x23: ffffffc0006d7188 x22: ffffffc0bc010000 x21: 000000000000016e x20: ffffffc0bc00d100 x19: ffffffc000944178 x18: 0000000000000007 x17: 000000000000000e x16: 0000000000000001 x15: 0000000000000007 x14: 000000000000000e x13: 0000000000000013 x12: 000000000000001a x11: 000000000000004d x10: 0000000000000750 x9 : ffffffc0bc0a8000 x8 : ffffffc0bc0a07b0 x7 : 0000000000000001 x6 : 0000000002d5f0f8 x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000002 x2 : ffffffc000996724 x1 : 0000000000000000 x0 : 0000000000000032 ---[ end trace cbd20ae519e92ced ]--- Call trace: [<ffffffc0008fee78>] tegra_init_from_table+0x140/0x164 [<ffffffc000900ac8>] tegra210_clock_apply_init_table+0x20/0x28 [<ffffffc0008fec40>] tegra_clocks_apply_init_table+0x18/0x24 [<ffffffc00008291c>] do_one_initcall+0x90/0x194 [<ffffffc0008cfab0>] kernel_init_freeable+0x148/0x1e8 [<ffffffc000636bb0>] kernel_init+0x10/0xdc [<ffffffc000085cd0>] ret_from_fork+0x10/0x40 clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock tegra_init_from_table: Failed to enable pll_u_out2 ------------[ cut here ]------------ pll_u can be either controlled by software or hardware and this is selected via the OVERRIDE bit in the pll_u base register. In the function tegra210_pll_init(), the OVERRIDE bit for pll_u is cleared, which selects hardware control of the pll. However, at the same time the pll_u clocks are populated in the init_table for tegra210 and so software will try to configure the pll_u if it is not already configured and hence, the above warning is seen when the pll fails to lock. Remove the pll_u clocks from the init_table so that software does not try to configure this pll on boot. Signed-off-by: NJon Hunter <jonathanh@nvidia.com> Acked-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Jon Hunter 提交于
The EMC clock sources for Tegra210 currently incorrectly include pll_c2 and pll_c3. However, both of these should have been pll_mb as shown in the TRM. If Tegra210 happens to be configured such that the pll_mb is the default clock for the EMC, as configured by the bootloader, then this will cause a system hang on boot. This is because the kernel will disable the pll_mb when disabling unused clock as it appears to be unused when it is not. Also add the additional pll_p clock source for the EMC. Signed-off-by: NJon Hunter <jonathanh@nvidia.com> Acked-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Jon Hunter 提交于
The APB2APE clock for the audio subsystem is required for powering up the audio power domain and accessing the various modules in this subsystem on Tegra210 devices. Add this clock for Tegra210. Signed-off-by: NJon Hunter <jonathanh@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Amitoj Kaur Chawla 提交于
for_each_child_of_node() performs an of_node_get() on each iteration, so before breaking out of the loop an of_node_put() is required. Found using Coccinelle. The semantic patch used for this is as follows: // <smpl> @@ expression e; local idexpression child; @@ for_each_child_of_node(root, child) { ... when != of_node_put(child) when != e = child ( return child; | + of_node_put(child); ? return ...; ) ... } // </smpl> Signed-off-by: NAmitoj Kaur Chawla <amitoj1606@gmail.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Mark Kuo 提交于
The PLLE SS coefficients are different between Tegra210 and Tegra114. Add SoC generation specific versions for Tegra114 and Tegra210 and use them in their respective ->enable() callbacks. Signed-off-by: NMark Kuo <mkuo@nvidia.com> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
While enabling PLLE on both Tegra114 and Tegra210, we should be clearing PLLE_MISC_VREG_BG_CTRL_MASK and PLLE_MISC_VREG_CTRL_MASK not setting them. This patch fixes both places where we incorrectly set instead of cleared those bits. Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Mark Kuo 提交于
Software should not disable PLLE if PLLE is already put under hardware control. Signed-off-by: NMark Kuo <mkuo@nvidia.com> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
The logic for calculating the input rate used when figuring out the proper dynamic steps for pllx was incorrect. It is supposed to be calculated using parent_rate / m but it was just using the parent rate directly, therefore using the wrong step values. Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Andrew Bresticker 提交于
Since the ->enable() callback is called with a spinlock held, we cannot call potentially blocking functions such as clk_get_rate() or clk_get_parent(), so use the unlocked versions instead. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> [rklein: Adapted from ChromeOS patch, removing pllu_enable cleanup as it isn't present upstream] Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
When adding the nvenc clock, it was partially named msenc in the code. Since the msenc clock isn't present in Tegra210 and has been replaced by the nvenc clock, its misleading to see it present. Therefore, properly rename it. Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
Some register for PLLM and PLLMB were named MISC0 but according to the TRM, they have different names. Sync up the names to make it easier to understand which register they are really referring to. Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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- 25 1月, 2016 2 次提交
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由 Rhyland Klein 提交于
Most PLL's don't actually have LOCK_ENABLE bits. However, most PLL's also had that flag set, which meant that the clk code was trying to enable locks, and inadvertantly flipping bits in other fields. For PLLM, ensure the correct register is used for the misc_register. PLL_MISC0 contains the EN_LCKDET bit which should be used for enabling the lock, and PLLM_MISC1 shouldn't be used at all. Lastly, remove some of the settings which would point to the EN_LCKDET bits for some PLLs. There is no need to enable the locks, and that is done as part of the set_defaults logic already. Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
VI-I2C has 16 bits available for its divider. Switch the divider width to 16 instead of 8 so correct rates can be set. Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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- 14 1月, 2016 1 次提交
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由 Vladimir Zapolskiy 提交于
Presumably the second COMMON_CLK_NXP config option in drivers/clk/Kconfig appeared after a merge conflict resolution, remove the wrong record of two. Signed-off-by: NVladimir Zapolskiy <vz@mleia.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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- 03 1月, 2016 2 次提交
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由 Russell King 提交于
When the clock DT property is not given, of_clk_get_parent_count() returns -ENOENT, which then tries to allocate -2 x 4 bytes of memory, which of course fails, causing the whole driver to fail to create the clock. This causes the SolidRun platforms to fail probing the SDHCI1 interface which is connected to the WiFi. Fix this by detecting errno codes, skipping the allocation, and fixing of_clk_gpio_gate_delayed_register_get() to handle a NULL parent_names array. Fixes: 80eeb1f0 ("clk: add gpio controlled clock multiplexer") Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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由 Heiko Stübner 提交于
To model the muxes downstream of fractional dividers we introduced the child property, allowing to describe a direct child clock. The first implementation seems to cause section warnings, as the core clock-tree is marked as initdata while the data pointed to from the child element is not. While there may be some way to also set that missing property in the inline notation I didn't find it, so to actually fix the issue for now move the sub-definitions into separate declarations that can have their own __initdata properties. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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- 01 1月, 2016 3 次提交
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由 Brian Norris 提交于
We might make bad memory allocations if we get (e.g.) -ENOSYS from of_clk_get_parent_count(). Noticed by Coverity. Fixes: f66541ba ("clk: gpio: Get parent clk names in of_gpio_clk_setup()") Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Cc: Jyri Sarha <jsarha@ti.com> Cc: Sergej Sawazki <ce3a@gmx.de> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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由 Sudip Mukherjee 提交于
If we fail to allocate parent_name then we are returning but we missed freeing data which has already been allocated. Signed-off-by: NSudip Mukherjee <sudip@vectorindia.org> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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由 Ulrich Hecht 提交于
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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- 25 12月, 2015 5 次提交
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由 Remi Pommarel 提交于
Register the pwm clock for bcm2835. Signed-off-by: NRemi Pommarel <repk@triplefau.lt> Reviewed-by: NEric Anholt <eric@anholt.net> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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由 Remi Pommarel 提交于
Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple parent clocks. These clocks divide the rate of a parent which can be selected by setting the proper bits in the clock control register. Previously all these parents where handled by a mux clock. But a mux clock cannot be used because updating clock control register to select parent needs a password to be xor'd with the parent index. This patch get rid of mux clock and make these clocks handle their own parent, allowing them to select the one to use. Signed-off-by: NRemi Pommarel <repk@triplefau.lt> Reviewed-by: NEric Anholt <eric@anholt.net> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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由 Remi Pommarel 提交于
Make bcm2835_clock_choose_div to optionally round up the chosen MASH divisor so that the resulting average rate will not be higher than the requested one. Signed-off-by: NRemi Pommarel <repk@triplefau.lt> Reviewed-by: NEric Anholt <eric@anholt.net> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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由 Vladimir Zapolskiy 提交于
Add support for all configurable clocks found on NXP LPC32xx SoC. The list contains several heterogenous groups of clocks: * system clocks including multiple dividers and muxes, * x397 PLL, HCLK PLL and USB PLL, * peripheral clocks inherited from rtc, hclk and pclk, * USB controller clocks: AHB slave, I2C, OTG, OHCI and device. Signed-off-by: NVladimir Zapolskiy <vz@mleia.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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由 Vladimir Zapolskiy 提交于
The change adds COMMON_CLK_NXP configuration symbol and enables it for NXP LPC18XX architecture, this is needed to reuse drivers/clk/nxp folder for NXP common clock framework drivers other than LPC18XX one. Signed-off-by: NVladimir Zapolskiy <vz@mleia.com> Acked-by: NJoachim Eastwood <manabian@gmail.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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- 24 12月, 2015 5 次提交
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由 Xing Zheng 提交于
Use the newly introduced possibility to combine the fractional dividers with their downstream muxes for all fractional dividers on currently supported RK3036 SoCs. Signed-off-by: NXing Zheng <zhengxing@rock-chips.com> Signed-off-by: NCaesar Wang <wxt@rock-chips.com> Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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由 Heiko Stuebner 提交于
Some clocks need to be enabled to accept rate changes. This patch adds a new flag CLK_SET_RATE_UNGATE that lets clk_change_rate enable the clock before trying to change the rate and disable it again afterwards. This of course doesn't effect clocks that are already running at that point, as their refcount will only temporarily increase. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Tested-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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由 Sjoerd Simons 提交于
The clock branches leading to sclk_spdif and sclk_spdif_8ch on RK3288 SoCs only feed those clocks, allow those clocks to change their parents all the way up the hierarchy. Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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由 Heiko Stuebner 提交于
Use the newly introduced possibility to combine the fractional dividers with their downstream muxes for all fractional dividers on currently supported Rockchip SoCs. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Tested-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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由 Heiko Stuebner 提交于
The fractional dividers of Rockchip SoCs contain an "auto-gating-feature" that requires the downstream mux to actually point to the fractional divider and the fractional divider gate to be enabled, for it to really accept changes to the divider ratio. The downstream muxes themselfs are not generic enough to include them directly into the fractional divider, as they have varying sources of parent clocks including not only clocks related to the fractional dividers but other clocks as well. To solve this, allow our clock branches to specify direct child clock- branches in the new child property, let the fractional divider register its downstream mux through this and add a clock notifier that temporarily switches the mux setting when it notices rate changes to the fractional divider. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Tested-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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- 23 12月, 2015 3 次提交
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由 Eric Anholt 提交于
There are a pair of SPI masters and a mini UART that were last minute additions. As a result, they didn't get integrated in the same way as the other gates off of the VPU clock in CPRMAN. Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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由 Russell King 提交于
Add support for the Dove PLL dividers, which are used to generate the clocks for the AXI bus, as well as the GPU and VMeta peripherals. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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由 Masahiro Yamada 提交于
This code is unreadable due to the blank line between if and else blocks. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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- 21 12月, 2015 1 次提交
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由 Heiko Stuebner 提交于
As commit 1d33929e ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") states, switching the PLLs to slow-mode is only necessary when rebooting using the soft-reset done through the CRU. The dwc2 controllers used create really big number of interrupts in special constellations involving usb-hubs and their number is so high, it can even overwhelm the interrupt handler if the cpu-speed os to low. Right now the PLLs are put into slow-mode in a shutdown syscore_ops callback which means it happens on all reboots (not only the soft-reset ones) and even on poweroff actions. This can result in the system not powering off and getting stuck instead, so we should move the slow-mode change nearer to the actual reboot action. For this we introduce the possiblity to also set a callback that gets called from the restart-handler directly prior to restarting the system and move the shutdown-callback to this new option. With this the slow-mode switch is done only on the necessary reboots and also has a smaller possibility of causing artifacts. Fixes: 1d33929e ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") Signed-off-by: NHeiko Stuebner <heiko.stuebner@collabora.com> Reviewed-by: NDouglas Anderson <dianders@chromium.org>
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- 17 12月, 2015 7 次提交
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由 Bill Huang 提交于
This fixes a bug in tegra_clk_register_pllss() which mistakenly assume the IDDQ register is the PLL base address. Signed-off-by: NBill Huang <bilhuang@nvidia.com> Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Bill Huang 提交于
This fixes two things. - Read the correct IDDQ register - Check the correct IDDQ bit position Signed-off-by: NBill Huang <bilhuang@nvidia.com> Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Andrew Bresticker 提交于
Without this change clk_get_rate would return the final output rather than the VCO output as it would factor in the pdiv when it shouldn't. This will cause problems for all dividers in the subtree of the VCO PLL. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
Implement clock support for Tegra210. Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Bill Huang 提交于
Super clock divider control and clock source mux of Tegra210 has changed a little against prior SoCs, this patch adds Gen5 logic to address those differences. Signed-off-by: NBill Huang <bilhuang@nvidia.com> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Bill Huang 提交于
Add some logic for Spread Spectrum control. It is used in conjuncture with SDM fractional dividers. SSC has to be disabled when we configure the divider settings. Signed-off-by: NBill Huang <bilhuang@nvidia.com> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
Add a callback to the pll_params for custom dynamic ramping functions which can be specified per PLL. Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NBill Huang <bilhuang@nvidia.com> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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