- 16 3月, 2012 2 次提交
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由 Tang Yuantian 提交于
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NTang Yuantian <b29983@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Xu Jiucheng 提交于
P1021RDB-PC Overview ----------------- 1Gbyte DDR3 (on board DDR) 16Mbyte NOR flash 32Mbyte eSLC NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory Real-time clock on I2C bus SD/MMC connector to interface with the SD memory card PCIex - x1 PCIe slot or x1 PCIe to dual SATA controller - x1 mini-PCIe slot USB 2.0 - ULPI PHY interface: SMSC USB3300 USB PHY and Genesys Logic’s GL850A - Two USB2.0 Type A receptacles - One USB2.0 signal to Mini PCIe slot eTSEC1: Connected to RGMII PHY VSC7385 eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY AR8021 DUART interface: supports two UARTs up to 115200 bps for console display Signed-off-by: NMatthew McClintock <msm@freescale.com> Signed-off-by: NXu Jiucheng <B37781@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 24 11月, 2011 6 次提交
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由 Kumar Gala 提交于
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8572 SoC template * Dropping "fsl,mpc8572-IP..." from compatibles for standard blocks Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Dropping "fsl,mpc8568-IP..." from compatibles for standard blocks Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) * and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8536 SoC template [ marked as MPC8572 compatiable to get errata handling that applies ] * Added missing cache-line-size & cache-size properties missing from L2-cache node * Added IP level IEEE 1588 / ptp timer node Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Introduce some common components that we can utilize to build up the various PQ3/85xx device trees. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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