Instantiate the L2 cache from DT. Indicate in DT where the cache
control register is so that it is possible to enable/disable write
through on the CPU.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NJason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>