1. 23 2月, 2014 2 次提交
  2. 17 4月, 2013 1 次提交
  3. 29 3月, 2012 1 次提交
  4. 24 3月, 2012 1 次提交
  5. 20 12月, 2010 1 次提交
    • N
      ARM: fix cache-feroceon-l2 after stack based kmap_atomic() · 6d3e6d36
      Nicolas Pitre 提交于
      Since commit 3e4d3af5 "mm: stack based kmap_atomic()", it is actively
      wrong to rely on fixed kmap type indices (namely KM_L2_CACHE) as
      kmap_atomic() totally ignores them and a concurrent instance of it may
      happily reuse any slot for any purpose.  Because kmap_atomic() is now
      able to deal with reentrancy, we can get rid of the ad hoc mapping here.
      
      While the code is made much simpler, there is a needless cache flush
      introduced by the usage of __kunmap_atomic().  It is not clear if the
      performance difference to remove that is worth the cost in code
      maintenance (I don't think there are that many highmem users on that
      platform anyway) but that should be reconsidered when/if someone cares
      enough to do some measurements.
      Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
      6d3e6d36
  6. 29 3月, 2009 2 次提交
  7. 16 3月, 2009 1 次提交
    • N
      [ARM] Feroceon: add highmem support to L2 cache handling code · 1bb77267
      Nicolas Pitre 提交于
      The choice is between looping over the physical range and performing
      single cache line operations, or to map highmem pages somewhere, as
      cache range ops are possible only on virtual addresses.
      
      Because L2 range ops are much faster, we go with the later by factoring
      the physical-to-virtual address conversion and use a fixmap entry for it
      in the HIGHMEM case.
      
      Possible future optimizations to avoid the pte setup cost:
      
       - do the pte setup for highmem pages only
      
       - determine a threshold for doing a line-by-line processing on physical
         addresses when the range is small
      Signed-off-by: NNicolas Pitre <nico@marvell.com>
      1bb77267
  8. 09 11月, 2008 1 次提交
  9. 01 10月, 2008 1 次提交
  10. 09 8月, 2008 1 次提交
  11. 23 6月, 2008 1 次提交
    • L
      [ARM] Feroceon: L2 cache support · 99c6dc11
      Lennert Buytenhek 提交于
      This patch adds support for the unified Feroceon L2 cache controller
      as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo
      families of ARM SoCs.
      
      Note that:
      
      - Page table walks are outer uncacheable on Kirkwood and Discovery
        Duo, since the ARMv5 spec provides no way to indicate outer
        cacheability of page table walks (specifying it in TTBR[4:3] is
        an ARMv6+ feature).
      
        This requires adding L2 cache clean instructions to
        proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to
        tlbflush.h ({flush,clean}_pmd_entry()).  The latter case is handled
        by defining a new TLB type (TLB_FEROCEON) which is almost identical
        to the v4wbi one but provides a TLB_L2CLEAN_FR flag.
      
      - The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2
        range by MVA' and 'invalidate L2 range by MVA') operations, and this
        patch uses those range operations for all Linux outer cache
        operations, as they are faster than the regular per-line operations.
      
        L2 range operations are not interruptible on this hardware, which
        avoids potential livelock issues, but can be bad for interrupt
        latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which
        allows you to select the maximum range size to operate on at once.
        (Valid range is between one cache line and one 4KiB page, and must
        be a multiple of the line size.)
      Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
      99c6dc11