omap_hwmod_44xx_data.c 140.3 KB
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/*
 * Hardware modules present on the OMAP44xx chips
 *
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 * Copyright (C) 2009-2011 Texas Instruments, Inc.
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 * Copyright (C) 2009-2010 Nokia Corporation
 *
 * Paul Walmsley
 * Benoit Cousson
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/io.h>

#include <plat/omap_hwmod.h>
#include <plat/cpu.h>
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#include <plat/i2c.h>
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#include <plat/gpio.h>
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#include <plat/dma.h>
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#include <plat/mcspi.h>
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#include <plat/mcbsp.h>
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#include <plat/mmc.h>
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#include <plat/i2c.h>
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#include "omap_hwmod_common_data.h"

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#include "cm1_44xx.h"
#include "cm2_44xx.h"
#include "prm44xx.h"
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#include "prm-regbits-44xx.h"
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#include "wd_timer.h"
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/* Base offset for all OMAP4 interrupts external to MPUSS */
#define OMAP44XX_IRQ_GIC_START	32

/* Base offset for all OMAP4 dma requests */
#define OMAP44XX_DMA_REQ_START  1

/* Backward references (IPs with Bus Master capability) */
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static struct omap_hwmod omap44xx_aess_hwmod;
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static struct omap_hwmod omap44xx_dma_system_hwmod;
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static struct omap_hwmod omap44xx_dmm_hwmod;
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static struct omap_hwmod omap44xx_dsp_hwmod;
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static struct omap_hwmod omap44xx_dss_hwmod;
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static struct omap_hwmod omap44xx_emif_fw_hwmod;
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static struct omap_hwmod omap44xx_hsi_hwmod;
static struct omap_hwmod omap44xx_ipu_hwmod;
static struct omap_hwmod omap44xx_iss_hwmod;
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static struct omap_hwmod omap44xx_iva_hwmod;
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static struct omap_hwmod omap44xx_l3_instr_hwmod;
static struct omap_hwmod omap44xx_l3_main_1_hwmod;
static struct omap_hwmod omap44xx_l3_main_2_hwmod;
static struct omap_hwmod omap44xx_l3_main_3_hwmod;
static struct omap_hwmod omap44xx_l4_abe_hwmod;
static struct omap_hwmod omap44xx_l4_cfg_hwmod;
static struct omap_hwmod omap44xx_l4_per_hwmod;
static struct omap_hwmod omap44xx_l4_wkup_hwmod;
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static struct omap_hwmod omap44xx_mmc1_hwmod;
static struct omap_hwmod omap44xx_mmc2_hwmod;
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static struct omap_hwmod omap44xx_mpu_hwmod;
static struct omap_hwmod omap44xx_mpu_private_hwmod;
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static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
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/*
 * Interconnects omap_hwmod structures
 * hwmods that compose the global OMAP interconnect
 */

/*
 * 'dmm' class
 * instance(s): dmm
 */
static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
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	.name	= "dmm",
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};

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/* dmm */
static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
	{ .irq = 113 + OMAP44XX_IRQ_GIC_START },
	{ .irq = -1 }
};

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/* l3_main_1 -> dmm */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
	.master		= &omap44xx_l3_main_1_hwmod,
	.slave		= &omap44xx_dmm_hwmod,
	.clk		= "l3_div_ck",
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	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
	{
		.pa_start	= 0x4e000000,
		.pa_end		= 0x4e0007ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* mpu -> dmm */
static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
	.master		= &omap44xx_mpu_hwmod,
	.slave		= &omap44xx_dmm_hwmod,
	.clk		= "l3_div_ck",
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	.addr		= omap44xx_dmm_addrs,
	.user		= OCP_USER_MPU,
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};

/* dmm slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
	&omap44xx_l3_main_1__dmm,
	&omap44xx_mpu__dmm,
};

static struct omap_hwmod omap44xx_dmm_hwmod = {
	.name		= "dmm",
	.class		= &omap44xx_dmm_hwmod_class,
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	.clkdm_name	= "l3_emif_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
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			.context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
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		},
	},
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	.slaves		= omap44xx_dmm_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dmm_slaves),
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	.mpu_irqs	= omap44xx_dmm_irqs,
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	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'emif_fw' class
 * instance(s): emif_fw
 */
static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
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	.name	= "emif_fw",
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};

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/* emif_fw */
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/* dmm -> emif_fw */
static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
	.master		= &omap44xx_dmm_hwmod,
	.slave		= &omap44xx_emif_fw_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
	{
		.pa_start	= 0x4a20c000,
		.pa_end		= 0x4a20c0ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

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/* l4_cfg -> emif_fw */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_emif_fw_hwmod,
	.clk		= "l4_div_ck",
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	.addr		= omap44xx_emif_fw_addrs,
	.user		= OCP_USER_MPU,
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};

/* emif_fw slave ports */
static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
	&omap44xx_dmm__emif_fw,
	&omap44xx_l4_cfg__emif_fw,
};

static struct omap_hwmod omap44xx_emif_fw_hwmod = {
	.name		= "emif_fw",
	.class		= &omap44xx_emif_fw_hwmod_class,
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	.clkdm_name	= "l3_emif_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
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			.context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
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		},
	},
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	.slaves		= omap44xx_emif_fw_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_emif_fw_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'l3' class
 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 */
static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
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	.name	= "l3",
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};

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/* l3_instr */
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/* iva -> l3_instr */
static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
	.master		= &omap44xx_iva_hwmod,
	.slave		= &omap44xx_l3_instr_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* l3_main_3 -> l3_instr */
static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
	.master		= &omap44xx_l3_main_3_hwmod,
	.slave		= &omap44xx_l3_instr_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_instr slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
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	&omap44xx_iva__l3_instr,
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	&omap44xx_l3_main_3__l3_instr,
};

static struct omap_hwmod omap44xx_l3_instr_hwmod = {
	.name		= "l3_instr",
	.class		= &omap44xx_l3_hwmod_class,
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	.clkdm_name	= "l3_instr_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
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			.context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
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			.modulemode   = MODULEMODE_HWCTRL,
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		},
	},
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	.slaves		= omap44xx_l3_instr_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l3_instr_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/* l3_main_1 */
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static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
	{ .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
	{ .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
	{ .irq = -1 }
};

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/* dsp -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
	.master		= &omap44xx_dsp_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* dss -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
	.master		= &omap44xx_dss_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* l3_main_2 -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_cfg -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l4_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* mmc1 -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
	.master		= &omap44xx_mmc1_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mmc2 -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
	.master		= &omap44xx_mmc2_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
	{
		.pa_start	= 0x44000000,
		.pa_end		= 0x44000fff,
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		.flags		= ADDR_TYPE_RT
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	},
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	{ }
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};

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/* mpu -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
	.master		= &omap44xx_mpu_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l3_div_ck",
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	.addr		= omap44xx_l3_main_1_addrs,
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	.user		= OCP_USER_MPU,
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};

/* l3_main_1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
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	&omap44xx_dsp__l3_main_1,
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	&omap44xx_dss__l3_main_1,
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	&omap44xx_l3_main_2__l3_main_1,
	&omap44xx_l4_cfg__l3_main_1,
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	&omap44xx_mmc1__l3_main_1,
	&omap44xx_mmc2__l3_main_1,
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	&omap44xx_mpu__l3_main_1,
};

static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
	.name		= "l3_main_1",
	.class		= &omap44xx_l3_hwmod_class,
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	.clkdm_name	= "l3_1_clkdm",
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	.mpu_irqs	= omap44xx_l3_main_1_irqs,
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
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			.context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
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		},
	},
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	.slaves		= omap44xx_l3_main_1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l3_main_1_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/* l3_main_2 */
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/* dma_system -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
	.master		= &omap44xx_dma_system_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* hsi -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
	.master		= &omap44xx_hsi_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* ipu -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
	.master		= &omap44xx_ipu_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* iss -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
	.master		= &omap44xx_iss_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* iva -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
	.master		= &omap44xx_iva_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
	{
		.pa_start	= 0x44800000,
		.pa_end		= 0x44801fff,
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		.flags		= ADDR_TYPE_RT
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	},
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	{ }
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};

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/* l3_main_1 -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
	.master		= &omap44xx_l3_main_1_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
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	.addr		= omap44xx_l3_main_2_addrs,
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	.user		= OCP_USER_MPU,
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};

/* l4_cfg -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l4_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* usb_otg_hs -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
	.master		= &omap44xx_usb_otg_hs_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* l3_main_2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
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	&omap44xx_dma_system__l3_main_2,
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	&omap44xx_hsi__l3_main_2,
	&omap44xx_ipu__l3_main_2,
	&omap44xx_iss__l3_main_2,
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	&omap44xx_iva__l3_main_2,
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	&omap44xx_l3_main_1__l3_main_2,
	&omap44xx_l4_cfg__l3_main_2,
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	&omap44xx_usb_otg_hs__l3_main_2,
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};

static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
	.name		= "l3_main_2",
	.class		= &omap44xx_l3_hwmod_class,
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	.clkdm_name	= "l3_2_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
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			.context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
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		},
	},
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	.slaves		= omap44xx_l3_main_2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l3_main_2_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/* l3_main_3 */
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static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
	{
		.pa_start	= 0x45000000,
		.pa_end		= 0x45000fff,
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		.flags		= ADDR_TYPE_RT
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	},
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	{ }
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};

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/* l3_main_1 -> l3_main_3 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
	.master		= &omap44xx_l3_main_1_hwmod,
	.slave		= &omap44xx_l3_main_3_hwmod,
	.clk		= "l3_div_ck",
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	.addr		= omap44xx_l3_main_3_addrs,
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	.user		= OCP_USER_MPU,
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};

/* l3_main_2 -> l3_main_3 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_l3_main_3_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_cfg -> l3_main_3 */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_l3_main_3_hwmod,
	.clk		= "l4_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
	&omap44xx_l3_main_1__l3_main_3,
	&omap44xx_l3_main_2__l3_main_3,
	&omap44xx_l4_cfg__l3_main_3,
};

static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
	.name		= "l3_main_3",
	.class		= &omap44xx_l3_hwmod_class,
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	.clkdm_name	= "l3_instr_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
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			.context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
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			.modulemode   = MODULEMODE_HWCTRL,
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		},
	},
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	.slaves		= omap44xx_l3_main_3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l3_main_3_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'l4' class
 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 */
static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
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	.name	= "l4",
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};

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/* l4_abe */
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/* aess -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
	.master		= &omap44xx_aess_hwmod,
	.slave		= &omap44xx_l4_abe_hwmod,
	.clk		= "ocp_abe_iclk",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* dsp -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
	.master		= &omap44xx_dsp_hwmod,
	.slave		= &omap44xx_l4_abe_hwmod,
	.clk		= "ocp_abe_iclk",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* l3_main_1 -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
	.master		= &omap44xx_l3_main_1_hwmod,
	.slave		= &omap44xx_l4_abe_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mpu -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
	.master		= &omap44xx_mpu_hwmod,
	.slave		= &omap44xx_l4_abe_hwmod,
	.clk		= "ocp_abe_iclk",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_abe slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
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	&omap44xx_aess__l4_abe,
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	&omap44xx_dsp__l4_abe,
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	&omap44xx_l3_main_1__l4_abe,
	&omap44xx_mpu__l4_abe,
};

static struct omap_hwmod omap44xx_l4_abe_hwmod = {
	.name		= "l4_abe",
	.class		= &omap44xx_l4_hwmod_class,
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	.clkdm_name	= "abe_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
		},
	},
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	.slaves		= omap44xx_l4_abe_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l4_abe_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/* l4_cfg */
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/* l3_main_1 -> l4_cfg */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
	.master		= &omap44xx_l3_main_1_hwmod,
	.slave		= &omap44xx_l4_cfg_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_cfg slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
	&omap44xx_l3_main_1__l4_cfg,
};

static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
	.name		= "l4_cfg",
	.class		= &omap44xx_l4_hwmod_class,
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	.clkdm_name	= "l4_cfg_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
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			.context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
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		},
	},
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	.slaves		= omap44xx_l4_cfg_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l4_cfg_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/* l4_per */
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/* l3_main_2 -> l4_per */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_l4_per_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
	&omap44xx_l3_main_2__l4_per,
};

static struct omap_hwmod omap44xx_l4_per_hwmod = {
	.name		= "l4_per",
	.class		= &omap44xx_l4_hwmod_class,
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	.clkdm_name	= "l4_per_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
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			.context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
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		},
	},
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	.slaves		= omap44xx_l4_per_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l4_per_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/* l4_wkup */
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/* l4_cfg -> l4_wkup */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_l4_wkup_hwmod,
	.clk		= "l4_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
	&omap44xx_l4_cfg__l4_wkup,
};

static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
	.name		= "l4_wkup",
	.class		= &omap44xx_l4_hwmod_class,
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	.clkdm_name	= "l4_wkup_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
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			.context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
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		},
	},
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	.slaves		= omap44xx_l4_wkup_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l4_wkup_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
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 * 'mpu_bus' class
 * instance(s): mpu_private
655
 */
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static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
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	.name	= "mpu_bus",
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};
659

660
/* mpu_private */
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/* mpu -> mpu_private */
static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
	.master		= &omap44xx_mpu_hwmod,
	.slave		= &omap44xx_mpu_private_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mpu_private slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
	&omap44xx_mpu__mpu_private,
};

static struct omap_hwmod omap44xx_mpu_private_hwmod = {
	.name		= "mpu_private",
	.class		= &omap44xx_mpu_bus_hwmod_class,
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	.clkdm_name	= "mpuss_clkdm",
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	.slaves		= omap44xx_mpu_private_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mpu_private_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * Modules omap_hwmod structures
 *
 * The following IPs are excluded for the moment because:
 * - They do not need an explicit SW control using omap_hwmod API.
 * - They still need to be validated with the driver
 *   properly adapted to omap_hwmod / omap_device
 *
 *  c2c
 *  c2c_target_fw
 *  cm_core
 *  cm_core_aon
 *  ctrl_module_core
 *  ctrl_module_pad_core
 *  ctrl_module_pad_wkup
 *  ctrl_module_wkup
 *  debugss
 *  efuse_ctrl_cust
 *  efuse_ctrl_std
 *  elm
 *  emif1
 *  emif2
 *  fdif
 *  gpmc
 *  gpu
 *  hdq1w
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 *  mcasp
 *  mpu_c0
 *  mpu_c1
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 *  ocmc_ram
 *  ocp2scp_usb_phy
 *  ocp_wp_noc
 *  prcm_mpu
 *  prm
 *  scrm
 *  sl2if
 *  slimbus1
 *  slimbus2
 *  usb_host_fs
 *  usb_host_hs
 *  usb_phy_cm
 *  usb_tll_hs
 *  usim
 */

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/*
 * 'aess' class
 * audio engine sub system
 */

static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
			   MSTANDBY_SMART_WKUP),
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	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
	.name	= "aess",
	.sysc	= &omap44xx_aess_sysc,
};

/* aess */
static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
	{ .irq = 99 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
	{ .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
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	{ .dma_req = -1 }
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};

/* aess master ports */
static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
	&omap44xx_aess__l4_abe,
};

static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
	{
		.pa_start	= 0x401f1000,
		.pa_end		= 0x401f13ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_abe -> aess */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_aess_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_aess_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
	{
		.pa_start	= 0x490f1000,
		.pa_end		= 0x490f13ff,
		.flags		= ADDR_TYPE_RT
	},
795
	{ }
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};

/* l4_abe -> aess (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_aess_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_aess_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* aess slave ports */
static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
	&omap44xx_l4_abe__aess,
	&omap44xx_l4_abe__aess_dma,
};

static struct omap_hwmod omap44xx_aess_hwmod = {
	.name		= "aess",
	.class		= &omap44xx_aess_hwmod_class,
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	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_aess_irqs,
	.sdma_reqs	= omap44xx_aess_sdma_reqs,
	.main_clk	= "aess_fck",
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	.prcm = {
821
		.omap4 = {
822
			.clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
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			.context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
824
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
	.slaves		= omap44xx_aess_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_aess_slaves),
	.masters	= omap44xx_aess_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_aess_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'bandgap' class
 * bangap reference for ldo regulators
 */

static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
	.name	= "bandgap",
};

/* bandgap */
static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
	{ .role = "fclk", .clk = "bandgap_fclk" },
};

static struct omap_hwmod omap44xx_bandgap_hwmod = {
	.name		= "bandgap",
	.class		= &omap44xx_bandgap_hwmod_class,
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	.clkdm_name	= "l4_wkup_clkdm",
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	.prcm = {
853
		.omap4 = {
854
			.clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
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		},
	},
	.opt_clks	= bandgap_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(bandgap_opt_clks),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'counter' class
 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 */

static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0004,
	.sysc_flags	= SYSC_HAS_SIDLEMODE,
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
	.name	= "counter",
	.sysc	= &omap44xx_counter_sysc,
};

/* counter_32k */
static struct omap_hwmod omap44xx_counter_32k_hwmod;
static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
	{
		.pa_start	= 0x4a304000,
		.pa_end		= 0x4a30401f,
		.flags		= ADDR_TYPE_RT
	},
889
	{ }
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};

/* l4_wkup -> counter_32k */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
	.master		= &omap44xx_l4_wkup_hwmod,
	.slave		= &omap44xx_counter_32k_hwmod,
	.clk		= "l4_wkup_clk_mux_ck",
	.addr		= omap44xx_counter_32k_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* counter_32k slave ports */
static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
	&omap44xx_l4_wkup__counter_32k,
};

static struct omap_hwmod omap44xx_counter_32k_hwmod = {
	.name		= "counter_32k",
	.class		= &omap44xx_counter_hwmod_class,
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	.clkdm_name	= "l4_wkup_clkdm",
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	.flags		= HWMOD_SWSUP_SIDLE,
	.main_clk	= "sys_32k_ck",
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	.prcm = {
913
		.omap4 = {
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			.clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
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			.context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
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		},
	},
	.slaves		= omap44xx_counter_32k_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_counter_32k_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'dma' class
 * dma controller for data exchange between memory to memory (i.e. internal or
 * external memory) and gp peripherals to memory or memory to gp peripherals
 */

static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x002c,
	.syss_offs	= 0x0028,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
	.name	= "dma",
	.sysc	= &omap44xx_dma_sysc,
};

/* dma dev_attr */
static struct omap_dma_dev_attr dma_dev_attr = {
	.dev_caps	= RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
			  IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
	.lch_count	= 32,
};

/* dma_system */
static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
	{ .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
	{ .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
	{ .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
	{ .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

/* dma_system master ports */
static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
	&omap44xx_dma_system__l3_main_2,
};

static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
	{
		.pa_start	= 0x4a056000,
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		.pa_end		= 0x4a056fff,
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		.flags		= ADDR_TYPE_RT
	},
974
	{ }
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};

/* l4_cfg -> dma_system */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_dma_system_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dma_system_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* dma_system slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
	&omap44xx_l4_cfg__dma_system,
};

static struct omap_hwmod omap44xx_dma_system_hwmod = {
	.name		= "dma_system",
	.class		= &omap44xx_dma_hwmod_class,
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	.clkdm_name	= "l3_dma_clkdm",
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	.mpu_irqs	= omap44xx_dma_system_irqs,
	.main_clk	= "l3_div_ck",
	.prcm = {
		.omap4 = {
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			.clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
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			.context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
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		},
	},
	.dev_attr	= &dma_dev_attr,
	.slaves		= omap44xx_dma_system_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dma_system_slaves),
	.masters	= omap44xx_dma_system_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_dma_system_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'dmic' class
 * digital microphone controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
	.name	= "dmic",
	.sysc	= &omap44xx_dmic_sysc,
};

/* dmic */
static struct omap_hwmod omap44xx_dmic_hwmod;
static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
	{ .irq = 114 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
	{ .dma_req = 66 + OMAP44XX_DMA_REQ_START },
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	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
	{
		.pa_start	= 0x4012e000,
		.pa_end		= 0x4012e07f,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_abe -> dmic */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_dmic_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_dmic_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
	{
		.pa_start	= 0x4902e000,
		.pa_end		= 0x4902e07f,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_abe -> dmic (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_dmic_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_dmic_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* dmic slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
	&omap44xx_l4_abe__dmic,
	&omap44xx_l4_abe__dmic_dma,
};

static struct omap_hwmod omap44xx_dmic_hwmod = {
	.name		= "dmic",
	.class		= &omap44xx_dmic_hwmod_class,
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	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_dmic_irqs,
	.sdma_reqs	= omap44xx_dmic_sdma_reqs,
	.main_clk	= "dmic_fck",
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	.prcm = {
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		.omap4 = {
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			.clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
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			.context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
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			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
	.slaves		= omap44xx_dmic_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dmic_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'dsp' class
 * dsp sub-system
 */

static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
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	.name	= "dsp",
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};

/* dsp */
static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
	{ .irq = 28 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
	{ .name = "mmu_cache", .rst_shift = 1 },
};

static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
	{ .name = "dsp", .rst_shift = 0 },
};

/* dsp -> iva */
static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
	.master		= &omap44xx_dsp_hwmod,
	.slave		= &omap44xx_iva_hwmod,
	.clk		= "dpll_iva_m5x2_ck",
};

/* dsp master ports */
static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
	&omap44xx_dsp__l3_main_1,
	&omap44xx_dsp__l4_abe,
	&omap44xx_dsp__iva,
};

/* l4_cfg -> dsp */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_dsp_hwmod,
	.clk		= "l4_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* dsp slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
	&omap44xx_l4_cfg__dsp,
};

/* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
	.name		= "dsp_c0",
	.class		= &omap44xx_dsp_hwmod_class,
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	.clkdm_name	= "tesla_clkdm",
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	.flags		= HWMOD_INIT_NO_RESET,
	.rst_lines	= omap44xx_dsp_c0_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_dsp_c0_resets),
	.prcm = {
		.omap4 = {
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			.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
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		},
	},
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

static struct omap_hwmod omap44xx_dsp_hwmod = {
	.name		= "dsp",
	.class		= &omap44xx_dsp_hwmod_class,
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	.clkdm_name	= "tesla_clkdm",
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	.mpu_irqs	= omap44xx_dsp_irqs,
	.rst_lines	= omap44xx_dsp_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_dsp_resets),
	.main_clk	= "dsp_fck",
	.prcm = {
		.omap4 = {
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			.clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
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			.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
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			.context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
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			.modulemode   = MODULEMODE_HWCTRL,
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		},
	},
	.slaves		= omap44xx_dsp_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dsp_slaves),
	.masters	= omap44xx_dsp_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_dsp_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'dss' class
 * display sub-system
 */

static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
	.rev_offs	= 0x0000,
	.syss_offs	= 0x0014,
	.sysc_flags	= SYSS_HAS_RESET_STATUS,
};

static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
	.name	= "dss",
	.sysc	= &omap44xx_dss_sysc,
};

/* dss */
/* dss master ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
	&omap44xx_dss__l3_main_1,
};

static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
	{
		.pa_start	= 0x58000000,
		.pa_end		= 0x5800007f,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l3_main_2 -> dss */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_hwmod,
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	.clk		= "dss_fck",
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	.addr		= omap44xx_dss_dma_addrs,
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
	{
		.pa_start	= 0x48040000,
		.pa_end		= 0x4804007f,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_per -> dss */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_addrs,
	.user		= OCP_USER_MPU,
};

/* dss slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
	&omap44xx_l3_main_2__dss,
	&omap44xx_l4_per__dss,
};

static struct omap_hwmod_opt_clk dss_opt_clks[] = {
	{ .role = "sys_clk", .clk = "dss_sys_clk" },
	{ .role = "tv_clk", .clk = "dss_tv_clk" },
	{ .role = "dss_clk", .clk = "dss_dss_clk" },
	{ .role = "video_clk", .clk = "dss_48mhz_clk" },
};

static struct omap_hwmod omap44xx_dss_hwmod = {
	.name		= "dss_core",
	.class		= &omap44xx_dss_hwmod_class,
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	.clkdm_name	= "l3_dss_clkdm",
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	.main_clk	= "dss_dss_clk",
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	.prcm = {
		.omap4 = {
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			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
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			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
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		},
	},
	.opt_clks	= dss_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_opt_clks),
	.slaves		= omap44xx_dss_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_slaves),
	.masters	= omap44xx_dss_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_dss_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'dispc' class
 * display controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
	.name	= "dispc",
	.sysc	= &omap44xx_dispc_sysc,
};

/* dss_dispc */
static struct omap_hwmod omap44xx_dss_dispc_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
	{ .irq = 25 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
	{ .dma_req = 5 + OMAP44XX_DMA_REQ_START },
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	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
	{
		.pa_start	= 0x58001000,
		.pa_end		= 0x58001fff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l3_main_2 -> dss_dispc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_dispc_hwmod,
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	.clk		= "dss_fck",
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	.addr		= omap44xx_dss_dispc_dma_addrs,
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
	{
		.pa_start	= 0x48041000,
		.pa_end		= 0x48041fff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_per -> dss_dispc */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_dispc_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_dispc_addrs,
	.user		= OCP_USER_MPU,
};

/* dss_dispc slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
	&omap44xx_l3_main_2__dss_dispc,
	&omap44xx_l4_per__dss_dispc,
};

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static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
	{ .role = "sys_clk", .clk = "dss_sys_clk" },
	{ .role = "tv_clk", .clk = "dss_tv_clk" },
	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
};

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static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
	.name		= "dss_dispc",
	.class		= &omap44xx_dispc_hwmod_class,
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	.clkdm_name	= "l3_dss_clkdm",
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	.mpu_irqs	= omap44xx_dss_dispc_irqs,
	.sdma_reqs	= omap44xx_dss_dispc_sdma_reqs,
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	.main_clk	= "dss_dss_clk",
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	.prcm = {
		.omap4 = {
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			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
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			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
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		},
	},
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	.opt_clks	= dss_dispc_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_dispc_opt_clks),
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	.slaves		= omap44xx_dss_dispc_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'dsi' class
 * display serial interface controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
	.name	= "dsi",
	.sysc	= &omap44xx_dsi_sysc,
};

/* dss_dsi1 */
static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
	{ .irq = 53 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
	{ .dma_req = 74 + OMAP44XX_DMA_REQ_START },
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	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
	{
		.pa_start	= 0x58004000,
		.pa_end		= 0x580041ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l3_main_2 -> dss_dsi1 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_dsi1_hwmod,
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	.clk		= "dss_fck",
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	.addr		= omap44xx_dss_dsi1_dma_addrs,
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
	{
		.pa_start	= 0x48044000,
		.pa_end		= 0x480441ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_per -> dss_dsi1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_dsi1_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_dsi1_addrs,
	.user		= OCP_USER_MPU,
};

/* dss_dsi1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
	&omap44xx_l3_main_2__dss_dsi1,
	&omap44xx_l4_per__dss_dsi1,
};

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static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
	{ .role = "sys_clk", .clk = "dss_sys_clk" },
};

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static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
	.name		= "dss_dsi1",
	.class		= &omap44xx_dsi_hwmod_class,
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	.clkdm_name	= "l3_dss_clkdm",
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	.mpu_irqs	= omap44xx_dss_dsi1_irqs,
	.sdma_reqs	= omap44xx_dss_dsi1_sdma_reqs,
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	.main_clk	= "dss_dss_clk",
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	.prcm = {
		.omap4 = {
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			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
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			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
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		},
	},
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	.opt_clks	= dss_dsi1_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi1_opt_clks),
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	.slaves		= omap44xx_dss_dsi1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* dss_dsi2 */
static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
	{ .irq = 84 + OMAP44XX_IRQ_GIC_START },
1490
	{ .irq = -1 }
1491 1492 1493 1494
};

static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
	{ .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1495
	{ .dma_req = -1 }
1496 1497 1498 1499 1500 1501 1502 1503
};

static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
	{
		.pa_start	= 0x58005000,
		.pa_end		= 0x580051ff,
		.flags		= ADDR_TYPE_RT
	},
1504
	{ }
1505 1506 1507 1508 1509 1510
};

/* l3_main_2 -> dss_dsi2 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_dsi2_hwmod,
1511
	.clk		= "dss_fck",
1512 1513 1514 1515 1516 1517 1518 1519 1520 1521
	.addr		= omap44xx_dss_dsi2_dma_addrs,
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
	{
		.pa_start	= 0x48045000,
		.pa_end		= 0x480451ff,
		.flags		= ADDR_TYPE_RT
	},
1522
	{ }
1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539
};

/* l4_per -> dss_dsi2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_dsi2_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_dsi2_addrs,
	.user		= OCP_USER_MPU,
};

/* dss_dsi2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
	&omap44xx_l3_main_2__dss_dsi2,
	&omap44xx_l4_per__dss_dsi2,
};

1540 1541 1542 1543
static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
	{ .role = "sys_clk", .clk = "dss_sys_clk" },
};

1544 1545 1546
static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
	.name		= "dss_dsi2",
	.class		= &omap44xx_dsi_hwmod_class,
1547
	.clkdm_name	= "l3_dss_clkdm",
1548 1549
	.mpu_irqs	= omap44xx_dss_dsi2_irqs,
	.sdma_reqs	= omap44xx_dss_dsi2_sdma_reqs,
1550
	.main_clk	= "dss_dss_clk",
1551 1552
	.prcm = {
		.omap4 = {
1553
			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1554
			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1555 1556
		},
	},
1557 1558
	.opt_clks	= dss_dsi2_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi2_opt_clks),
1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587
	.slaves		= omap44xx_dss_dsi2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'hdmi' class
 * hdmi controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
	.name	= "hdmi",
	.sysc	= &omap44xx_hdmi_sysc,
};

/* dss_hdmi */
static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
	{ .irq = 101 + OMAP44XX_IRQ_GIC_START },
1588
	{ .irq = -1 }
1589 1590 1591 1592
};

static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
	{ .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1593
	{ .dma_req = -1 }
1594 1595 1596 1597 1598 1599 1600 1601
};

static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
	{
		.pa_start	= 0x58006000,
		.pa_end		= 0x58006fff,
		.flags		= ADDR_TYPE_RT
	},
1602
	{ }
1603 1604 1605 1606 1607 1608
};

/* l3_main_2 -> dss_hdmi */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_hdmi_hwmod,
1609
	.clk		= "dss_fck",
1610 1611 1612 1613 1614 1615 1616 1617 1618 1619
	.addr		= omap44xx_dss_hdmi_dma_addrs,
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
	{
		.pa_start	= 0x48046000,
		.pa_end		= 0x48046fff,
		.flags		= ADDR_TYPE_RT
	},
1620
	{ }
1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637
};

/* l4_per -> dss_hdmi */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_hdmi_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_hdmi_addrs,
	.user		= OCP_USER_MPU,
};

/* dss_hdmi slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
	&omap44xx_l3_main_2__dss_hdmi,
	&omap44xx_l4_per__dss_hdmi,
};

1638 1639 1640 1641
static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
	{ .role = "sys_clk", .clk = "dss_sys_clk" },
};

1642 1643 1644
static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
	.name		= "dss_hdmi",
	.class		= &omap44xx_hdmi_hwmod_class,
1645
	.clkdm_name	= "l3_dss_clkdm",
1646 1647
	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
1648
	.main_clk	= "dss_dss_clk",
1649 1650
	.prcm = {
		.omap4 = {
1651
			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1652
			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1653 1654
		},
	},
1655 1656
	.opt_clks	= dss_hdmi_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_hdmi_opt_clks),
1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685
	.slaves		= omap44xx_dss_hdmi_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'rfbi' class
 * remote frame buffer interface
 */

static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
	.name	= "rfbi",
	.sysc	= &omap44xx_rfbi_sysc,
};

/* dss_rfbi */
static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
	{ .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1686
	{ .dma_req = -1 }
1687 1688 1689 1690 1691 1692 1693 1694
};

static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
	{
		.pa_start	= 0x58002000,
		.pa_end		= 0x580020ff,
		.flags		= ADDR_TYPE_RT
	},
1695
	{ }
1696 1697 1698 1699 1700 1701
};

/* l3_main_2 -> dss_rfbi */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_rfbi_hwmod,
1702
	.clk		= "dss_fck",
1703 1704 1705 1706 1707 1708 1709 1710 1711 1712
	.addr		= omap44xx_dss_rfbi_dma_addrs,
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
	{
		.pa_start	= 0x48042000,
		.pa_end		= 0x480420ff,
		.flags		= ADDR_TYPE_RT
	},
1713
	{ }
1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730
};

/* l4_per -> dss_rfbi */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_rfbi_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_rfbi_addrs,
	.user		= OCP_USER_MPU,
};

/* dss_rfbi slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
	&omap44xx_l3_main_2__dss_rfbi,
	&omap44xx_l4_per__dss_rfbi,
};

1731 1732 1733 1734
static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
	{ .role = "ick", .clk = "dss_fck" },
};

1735 1736 1737
static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
	.name		= "dss_rfbi",
	.class		= &omap44xx_rfbi_hwmod_class,
1738
	.clkdm_name	= "l3_dss_clkdm",
1739
	.sdma_reqs	= omap44xx_dss_rfbi_sdma_reqs,
1740
	.main_clk	= "dss_dss_clk",
1741 1742
	.prcm = {
		.omap4 = {
1743
			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1744
			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1745 1746
		},
	},
1747 1748
	.opt_clks	= dss_rfbi_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770
	.slaves		= omap44xx_dss_rfbi_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'venc' class
 * video encoder
 */

static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
	.name	= "venc",
};

/* dss_venc */
static struct omap_hwmod omap44xx_dss_venc_hwmod;
static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
	{
		.pa_start	= 0x58003000,
		.pa_end		= 0x580030ff,
		.flags		= ADDR_TYPE_RT
	},
1771
	{ }
1772 1773 1774 1775 1776 1777
};

/* l3_main_2 -> dss_venc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_venc_hwmod,
1778
	.clk		= "dss_fck",
1779 1780 1781 1782 1783 1784 1785 1786 1787 1788
	.addr		= omap44xx_dss_venc_dma_addrs,
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
	{
		.pa_start	= 0x48043000,
		.pa_end		= 0x480430ff,
		.flags		= ADDR_TYPE_RT
	},
1789
	{ }
1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809
};

/* l4_per -> dss_venc */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_venc_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_venc_addrs,
	.user		= OCP_USER_MPU,
};

/* dss_venc slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
	&omap44xx_l3_main_2__dss_venc,
	&omap44xx_l4_per__dss_venc,
};

static struct omap_hwmod omap44xx_dss_venc_hwmod = {
	.name		= "dss_venc",
	.class		= &omap44xx_venc_hwmod_class,
1810
	.clkdm_name	= "l3_dss_clkdm",
1811
	.main_clk	= "dss_dss_clk",
1812 1813
	.prcm = {
		.omap4 = {
1814
			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1815
			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1816 1817 1818 1819 1820 1821 1822
		},
	},
	.slaves		= omap44xx_dss_venc_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_venc_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

1823 1824 1825 1826 1827 1828 1829
/*
 * 'gpio' class
 * general purpose io module
 */

static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
	.rev_offs	= 0x0000,
1830
	.sysc_offs	= 0x0010,
1831
	.syss_offs	= 0x0114,
1832 1833 1834
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
1835 1836
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
1837 1838 1839
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

1840
static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1841 1842 1843
	.name	= "gpio",
	.sysc	= &omap44xx_gpio_sysc,
	.rev	= 2,
1844 1845
};

1846 1847
/* gpio dev_attr */
static struct omap_gpio_dev_attr gpio_dev_attr = {
1848 1849
	.bank_width	= 32,
	.dbck_flag	= true,
1850 1851
};

1852 1853 1854 1855
/* gpio1 */
static struct omap_hwmod omap44xx_gpio1_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
	{ .irq = 29 + OMAP44XX_IRQ_GIC_START },
1856
	{ .irq = -1 }
1857 1858
};

1859
static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1860
	{
1861 1862
		.pa_start	= 0x4a310000,
		.pa_end		= 0x4a3101ff,
1863 1864
		.flags		= ADDR_TYPE_RT
	},
1865
	{ }
1866 1867
};

1868 1869 1870 1871
/* l4_wkup -> gpio1 */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
	.master		= &omap44xx_l4_wkup_hwmod,
	.slave		= &omap44xx_gpio1_hwmod,
1872
	.clk		= "l4_wkup_clk_mux_ck",
1873
	.addr		= omap44xx_gpio1_addrs,
1874 1875 1876
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

1877 1878 1879
/* gpio1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
	&omap44xx_l4_wkup__gpio1,
1880 1881
};

1882
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1883
	{ .role = "dbclk", .clk = "gpio1_dbclk" },
1884 1885 1886 1887 1888
};

static struct omap_hwmod omap44xx_gpio1_hwmod = {
	.name		= "gpio1",
	.class		= &omap44xx_gpio_hwmod_class,
1889
	.clkdm_name	= "l4_wkup_clkdm",
1890 1891
	.mpu_irqs	= omap44xx_gpio1_irqs,
	.main_clk	= "gpio1_ick",
1892 1893
	.prcm = {
		.omap4 = {
1894
			.clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1895
			.context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1896
			.modulemode   = MODULEMODE_HWCTRL,
1897 1898
		},
	},
1899 1900 1901 1902 1903
	.opt_clks	= gpio1_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio1_slaves),
1904 1905 1906
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

1907 1908 1909 1910
/* gpio2 */
static struct omap_hwmod omap44xx_gpio2_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
	{ .irq = 30 + OMAP44XX_IRQ_GIC_START },
1911
	{ .irq = -1 }
1912 1913
};

1914
static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1915
	{
1916 1917
		.pa_start	= 0x48055000,
		.pa_end		= 0x480551ff,
1918 1919
		.flags		= ADDR_TYPE_RT
	},
1920
	{ }
1921 1922
};

1923 1924
/* l4_per -> gpio2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1925
	.master		= &omap44xx_l4_per_hwmod,
1926
	.slave		= &omap44xx_gpio2_hwmod,
1927
	.clk		= "l4_div_ck",
1928
	.addr		= omap44xx_gpio2_addrs,
1929 1930 1931
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

1932 1933 1934
/* gpio2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
	&omap44xx_l4_per__gpio2,
1935 1936
};

1937
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1938
	{ .role = "dbclk", .clk = "gpio2_dbclk" },
1939 1940 1941 1942 1943
};

static struct omap_hwmod omap44xx_gpio2_hwmod = {
	.name		= "gpio2",
	.class		= &omap44xx_gpio_hwmod_class,
1944
	.clkdm_name	= "l4_per_clkdm",
1945
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1946 1947
	.mpu_irqs	= omap44xx_gpio2_irqs,
	.main_clk	= "gpio2_ick",
1948 1949
	.prcm = {
		.omap4 = {
1950
			.clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1951
			.context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1952
			.modulemode   = MODULEMODE_HWCTRL,
1953 1954
		},
	},
1955 1956 1957 1958 1959
	.opt_clks	= gpio2_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio2_slaves),
1960 1961 1962
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

1963 1964 1965 1966
/* gpio3 */
static struct omap_hwmod omap44xx_gpio3_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
	{ .irq = 31 + OMAP44XX_IRQ_GIC_START },
1967
	{ .irq = -1 }
1968 1969
};

1970
static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1971
	{
1972 1973
		.pa_start	= 0x48057000,
		.pa_end		= 0x480571ff,
1974 1975
		.flags		= ADDR_TYPE_RT
	},
1976
	{ }
1977 1978
};

1979 1980
/* l4_per -> gpio3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1981
	.master		= &omap44xx_l4_per_hwmod,
1982
	.slave		= &omap44xx_gpio3_hwmod,
1983
	.clk		= "l4_div_ck",
1984
	.addr		= omap44xx_gpio3_addrs,
1985 1986 1987
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

1988 1989 1990
/* gpio3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
	&omap44xx_l4_per__gpio3,
1991 1992
};

1993
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1994
	{ .role = "dbclk", .clk = "gpio3_dbclk" },
1995 1996 1997 1998 1999
};

static struct omap_hwmod omap44xx_gpio3_hwmod = {
	.name		= "gpio3",
	.class		= &omap44xx_gpio_hwmod_class,
2000
	.clkdm_name	= "l4_per_clkdm",
2001
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2002 2003
	.mpu_irqs	= omap44xx_gpio3_irqs,
	.main_clk	= "gpio3_ick",
2004 2005
	.prcm = {
		.omap4 = {
2006
			.clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
2007
			.context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
2008
			.modulemode   = MODULEMODE_HWCTRL,
2009 2010
		},
	},
2011 2012 2013 2014 2015
	.opt_clks	= gpio3_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio3_slaves),
2016 2017 2018
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

2019 2020 2021 2022
/* gpio4 */
static struct omap_hwmod omap44xx_gpio4_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
	{ .irq = 32 + OMAP44XX_IRQ_GIC_START },
2023
	{ .irq = -1 }
2024 2025
};

2026
static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
2027
	{
2028 2029
		.pa_start	= 0x48059000,
		.pa_end		= 0x480591ff,
2030 2031
		.flags		= ADDR_TYPE_RT
	},
2032
	{ }
2033 2034
};

2035 2036
/* l4_per -> gpio4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2037
	.master		= &omap44xx_l4_per_hwmod,
2038
	.slave		= &omap44xx_gpio4_hwmod,
2039
	.clk		= "l4_div_ck",
2040
	.addr		= omap44xx_gpio4_addrs,
2041 2042 2043
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

2044 2045 2046
/* gpio4 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
	&omap44xx_l4_per__gpio4,
2047 2048
};

2049
static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2050
	{ .role = "dbclk", .clk = "gpio4_dbclk" },
2051 2052 2053 2054 2055
};

static struct omap_hwmod omap44xx_gpio4_hwmod = {
	.name		= "gpio4",
	.class		= &omap44xx_gpio_hwmod_class,
2056
	.clkdm_name	= "l4_per_clkdm",
2057
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2058 2059
	.mpu_irqs	= omap44xx_gpio4_irqs,
	.main_clk	= "gpio4_ick",
2060 2061
	.prcm = {
		.omap4 = {
2062
			.clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2063
			.context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2064
			.modulemode   = MODULEMODE_HWCTRL,
2065 2066
		},
	},
2067 2068 2069 2070 2071
	.opt_clks	= gpio4_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio4_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio4_slaves),
2072 2073 2074
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

2075 2076 2077 2078
/* gpio5 */
static struct omap_hwmod omap44xx_gpio5_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
	{ .irq = 33 + OMAP44XX_IRQ_GIC_START },
2079
	{ .irq = -1 }
2080 2081
};

2082 2083 2084 2085 2086 2087
static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
	{
		.pa_start	= 0x4805b000,
		.pa_end		= 0x4805b1ff,
		.flags		= ADDR_TYPE_RT
	},
2088
	{ }
2089 2090
};

2091 2092 2093 2094
/* l4_per -> gpio5 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_gpio5_hwmod,
2095
	.clk		= "l4_div_ck",
2096 2097
	.addr		= omap44xx_gpio5_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2098 2099
};

2100 2101 2102
/* gpio5 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
	&omap44xx_l4_per__gpio5,
2103 2104
};

2105
static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2106
	{ .role = "dbclk", .clk = "gpio5_dbclk" },
2107 2108
};

2109 2110 2111
static struct omap_hwmod omap44xx_gpio5_hwmod = {
	.name		= "gpio5",
	.class		= &omap44xx_gpio_hwmod_class,
2112
	.clkdm_name	= "l4_per_clkdm",
2113
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2114 2115
	.mpu_irqs	= omap44xx_gpio5_irqs,
	.main_clk	= "gpio5_ick",
2116 2117
	.prcm = {
		.omap4 = {
2118
			.clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2119
			.context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2120
			.modulemode   = MODULEMODE_HWCTRL,
2121 2122
		},
	},
2123 2124 2125 2126 2127
	.opt_clks	= gpio5_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio5_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio5_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio5_slaves),
2128 2129 2130
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

2131 2132 2133 2134
/* gpio6 */
static struct omap_hwmod omap44xx_gpio6_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
	{ .irq = 34 + OMAP44XX_IRQ_GIC_START },
2135
	{ .irq = -1 }
2136 2137
};

2138
static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2139
	{
2140 2141
		.pa_start	= 0x4805d000,
		.pa_end		= 0x4805d1ff,
2142 2143
		.flags		= ADDR_TYPE_RT
	},
2144
	{ }
2145 2146
};

2147 2148 2149 2150
/* l4_per -> gpio6 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_gpio6_hwmod,
2151
	.clk		= "l4_div_ck",
2152 2153
	.addr		= omap44xx_gpio6_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2154 2155
};

2156 2157 2158
/* gpio6 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
	&omap44xx_l4_per__gpio6,
2159 2160
};

2161
static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2162
	{ .role = "dbclk", .clk = "gpio6_dbclk" },
2163 2164
};

2165 2166 2167
static struct omap_hwmod omap44xx_gpio6_hwmod = {
	.name		= "gpio6",
	.class		= &omap44xx_gpio_hwmod_class,
2168
	.clkdm_name	= "l4_per_clkdm",
2169
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2170 2171 2172 2173
	.mpu_irqs	= omap44xx_gpio6_irqs,
	.main_clk	= "gpio6_ick",
	.prcm = {
		.omap4 = {
2174
			.clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2175
			.context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2176
			.modulemode   = MODULEMODE_HWCTRL,
2177
		},
2178
	},
2179 2180 2181 2182 2183 2184
	.opt_clks	= gpio6_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio6_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio6_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio6_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2185 2186
};

2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201
/*
 * 'hsi' class
 * mipi high-speed synchronous serial interface (multichannel and full-duplex
 * serial if)
 */

static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
			   SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2202
			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
	.name	= "hsi",
	.sysc	= &omap44xx_hsi_sysc,
};

/* hsi */
static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
	{ .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
	{ .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
	{ .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2216
	{ .irq = -1 }
2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229
};

/* hsi master ports */
static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
	&omap44xx_hsi__l3_main_2,
};

static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
	{
		.pa_start	= 0x4a058000,
		.pa_end		= 0x4a05bfff,
		.flags		= ADDR_TYPE_RT
	},
2230
	{ }
2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249
};

/* l4_cfg -> hsi */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_hsi_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_hsi_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* hsi slave ports */
static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
	&omap44xx_l4_cfg__hsi,
};

static struct omap_hwmod omap44xx_hsi_hwmod = {
	.name		= "hsi",
	.class		= &omap44xx_hsi_hwmod_class,
2250
	.clkdm_name	= "l3_init_clkdm",
2251 2252
	.mpu_irqs	= omap44xx_hsi_irqs,
	.main_clk	= "hsi_fck",
2253
	.prcm = {
2254
		.omap4 = {
2255
			.clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2256
			.context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2257
			.modulemode   = MODULEMODE_HWCTRL,
2258 2259 2260 2261 2262 2263 2264 2265 2266
		},
	},
	.slaves		= omap44xx_hsi_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_hsi_slaves),
	.masters	= omap44xx_hsi_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_hsi_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

2267 2268 2269 2270
/*
 * 'i2c' class
 * multimaster high-speed i2c controller
 */
2271

2272 2273 2274 2275 2276
static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0090,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2277
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2278 2279
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
2280
	.sysc_fields	= &omap_hwmod_sysc_type1,
2281 2282
};

2283
static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2284 2285
	.name	= "i2c",
	.sysc	= &omap44xx_i2c_sysc,
2286
	.rev	= OMAP_I2C_IP_VERSION_2,
2287
	.reset	= &omap_i2c_reset,
2288 2289
};

2290 2291 2292 2293
static struct omap_i2c_dev_attr i2c_dev_attr = {
	.flags	= OMAP_I2C_FLAG_BUS_SHIFT_NONE,
};

2294 2295 2296 2297
/* i2c1 */
static struct omap_hwmod omap44xx_i2c1_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
	{ .irq = 56 + OMAP44XX_IRQ_GIC_START },
2298
	{ .irq = -1 }
2299 2300
};

2301 2302 2303
static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2304
	{ .dma_req = -1 }
2305 2306
};

2307
static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2308
	{
2309 2310
		.pa_start	= 0x48070000,
		.pa_end		= 0x480700ff,
2311 2312
		.flags		= ADDR_TYPE_RT
	},
2313
	{ }
2314 2315
};

2316 2317 2318 2319 2320 2321
/* l4_per -> i2c1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_i2c1_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_i2c1_addrs,
2322 2323 2324
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

2325 2326 2327
/* i2c1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
	&omap44xx_l4_per__i2c1,
2328 2329
};

2330 2331 2332
static struct omap_hwmod omap44xx_i2c1_hwmod = {
	.name		= "i2c1",
	.class		= &omap44xx_i2c_hwmod_class,
2333
	.clkdm_name	= "l4_per_clkdm",
2334
	.flags		= HWMOD_16BIT_REG,
2335 2336 2337
	.mpu_irqs	= omap44xx_i2c1_irqs,
	.sdma_reqs	= omap44xx_i2c1_sdma_reqs,
	.main_clk	= "i2c1_fck",
2338 2339
	.prcm = {
		.omap4 = {
2340
			.clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2341
			.context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2342
			.modulemode   = MODULEMODE_SWCTRL,
2343 2344
		},
	},
2345 2346
	.slaves		= omap44xx_i2c1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c1_slaves),
2347
	.dev_attr	= &i2c_dev_attr,
2348 2349 2350
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

2351 2352 2353 2354
/* i2c2 */
static struct omap_hwmod omap44xx_i2c2_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
	{ .irq = 57 + OMAP44XX_IRQ_GIC_START },
2355
	{ .irq = -1 }
2356 2357
};

2358 2359 2360
static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2361
	{ .dma_req = -1 }
2362 2363 2364
};

static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2365
	{
2366 2367
		.pa_start	= 0x48072000,
		.pa_end		= 0x480720ff,
2368 2369
		.flags		= ADDR_TYPE_RT
	},
2370
	{ }
2371 2372
};

2373 2374
/* l4_per -> i2c2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2375
	.master		= &omap44xx_l4_per_hwmod,
2376
	.slave		= &omap44xx_i2c2_hwmod,
2377
	.clk		= "l4_div_ck",
2378
	.addr		= omap44xx_i2c2_addrs,
2379 2380 2381
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

2382 2383 2384
/* i2c2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
	&omap44xx_l4_per__i2c2,
2385 2386
};

2387 2388 2389
static struct omap_hwmod omap44xx_i2c2_hwmod = {
	.name		= "i2c2",
	.class		= &omap44xx_i2c_hwmod_class,
2390
	.clkdm_name	= "l4_per_clkdm",
2391
	.flags		= HWMOD_16BIT_REG,
2392 2393 2394
	.mpu_irqs	= omap44xx_i2c2_irqs,
	.sdma_reqs	= omap44xx_i2c2_sdma_reqs,
	.main_clk	= "i2c2_fck",
2395 2396
	.prcm = {
		.omap4 = {
2397
			.clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2398
			.context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2399
			.modulemode   = MODULEMODE_SWCTRL,
2400 2401
		},
	},
2402 2403
	.slaves		= omap44xx_i2c2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c2_slaves),
2404
	.dev_attr	= &i2c_dev_attr,
2405 2406 2407
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

2408 2409 2410 2411
/* i2c3 */
static struct omap_hwmod omap44xx_i2c3_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
	{ .irq = 61 + OMAP44XX_IRQ_GIC_START },
2412
	{ .irq = -1 }
2413 2414
};

2415 2416 2417
static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2418
	{ .dma_req = -1 }
2419 2420
};

2421
static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2422
	{
2423 2424
		.pa_start	= 0x48060000,
		.pa_end		= 0x480600ff,
2425 2426
		.flags		= ADDR_TYPE_RT
	},
2427
	{ }
2428 2429
};

2430 2431
/* l4_per -> i2c3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2432
	.master		= &omap44xx_l4_per_hwmod,
2433
	.slave		= &omap44xx_i2c3_hwmod,
2434
	.clk		= "l4_div_ck",
2435
	.addr		= omap44xx_i2c3_addrs,
2436 2437 2438
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

2439 2440 2441
/* i2c3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
	&omap44xx_l4_per__i2c3,
2442 2443
};

2444 2445 2446
static struct omap_hwmod omap44xx_i2c3_hwmod = {
	.name		= "i2c3",
	.class		= &omap44xx_i2c_hwmod_class,
2447
	.clkdm_name	= "l4_per_clkdm",
2448
	.flags		= HWMOD_16BIT_REG,
2449 2450 2451
	.mpu_irqs	= omap44xx_i2c3_irqs,
	.sdma_reqs	= omap44xx_i2c3_sdma_reqs,
	.main_clk	= "i2c3_fck",
2452 2453
	.prcm = {
		.omap4 = {
2454
			.clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2455
			.context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2456
			.modulemode   = MODULEMODE_SWCTRL,
2457 2458
		},
	},
2459 2460
	.slaves		= omap44xx_i2c3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c3_slaves),
2461
	.dev_attr	= &i2c_dev_attr,
2462 2463 2464
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

2465 2466 2467 2468
/* i2c4 */
static struct omap_hwmod omap44xx_i2c4_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
	{ .irq = 62 + OMAP44XX_IRQ_GIC_START },
2469
	{ .irq = -1 }
2470 2471
};

2472 2473 2474
static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2475
	{ .dma_req = -1 }
2476 2477
};

2478
static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2479
	{
2480 2481
		.pa_start	= 0x48350000,
		.pa_end		= 0x483500ff,
2482 2483
		.flags		= ADDR_TYPE_RT
	},
2484
	{ }
2485 2486
};

2487 2488 2489 2490 2491 2492 2493
/* l4_per -> i2c4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_i2c4_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_i2c4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2494 2495
};

2496 2497 2498
/* i2c4 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
	&omap44xx_l4_per__i2c4,
2499 2500
};

2501 2502 2503
static struct omap_hwmod omap44xx_i2c4_hwmod = {
	.name		= "i2c4",
	.class		= &omap44xx_i2c_hwmod_class,
2504
	.clkdm_name	= "l4_per_clkdm",
2505
	.flags		= HWMOD_16BIT_REG,
2506 2507 2508
	.mpu_irqs	= omap44xx_i2c4_irqs,
	.sdma_reqs	= omap44xx_i2c4_sdma_reqs,
	.main_clk	= "i2c4_fck",
2509 2510
	.prcm = {
		.omap4 = {
2511
			.clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2512
			.context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2513
			.modulemode   = MODULEMODE_SWCTRL,
2514 2515
		},
	},
2516 2517
	.slaves		= omap44xx_i2c4_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c4_slaves),
2518
	.dev_attr	= &i2c_dev_attr,
2519 2520 2521
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533
/*
 * 'ipu' class
 * imaging processor unit
 */

static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
	.name	= "ipu",
};

/* ipu */
static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
	{ .irq = 100 + OMAP44XX_IRQ_GIC_START },
2534
	{ .irq = -1 }
2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570
};

static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
	{ .name = "cpu0", .rst_shift = 0 },
};

static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
	{ .name = "cpu1", .rst_shift = 1 },
};

static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
	{ .name = "mmu_cache", .rst_shift = 2 },
};

/* ipu master ports */
static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
	&omap44xx_ipu__l3_main_2,
};

/* l3_main_2 -> ipu */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_ipu_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* ipu slave ports */
static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
	&omap44xx_l3_main_2__ipu,
};

/* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
	.name		= "ipu_c0",
	.class		= &omap44xx_ipu_hwmod_class,
2571
	.clkdm_name	= "ducati_clkdm",
2572 2573 2574
	.flags		= HWMOD_INIT_NO_RESET,
	.rst_lines	= omap44xx_ipu_c0_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_ipu_c0_resets),
2575
	.prcm = {
2576
		.omap4 = {
2577
			.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2578 2579 2580 2581 2582 2583 2584 2585 2586
		},
	},
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
	.name		= "ipu_c1",
	.class		= &omap44xx_ipu_hwmod_class,
2587
	.clkdm_name	= "ducati_clkdm",
2588 2589 2590
	.flags		= HWMOD_INIT_NO_RESET,
	.rst_lines	= omap44xx_ipu_c1_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_ipu_c1_resets),
2591
	.prcm = {
2592
		.omap4 = {
2593
			.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2594 2595 2596 2597 2598 2599 2600 2601
		},
	},
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

static struct omap_hwmod omap44xx_ipu_hwmod = {
	.name		= "ipu",
	.class		= &omap44xx_ipu_hwmod_class,
2602
	.clkdm_name	= "ducati_clkdm",
2603 2604 2605 2606
	.mpu_irqs	= omap44xx_ipu_irqs,
	.rst_lines	= omap44xx_ipu_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_ipu_resets),
	.main_clk	= "ipu_fck",
2607
	.prcm = {
2608
		.omap4 = {
2609
			.clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2610
			.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2611
			.context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2612
			.modulemode   = MODULEMODE_HWCTRL,
2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633
		},
	},
	.slaves		= omap44xx_ipu_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_ipu_slaves),
	.masters	= omap44xx_ipu_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_ipu_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'iss' class
 * external images sensor pixel data processor
 */

static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2634
			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
	.name	= "iss",
	.sysc	= &omap44xx_iss_sysc,
};

/* iss */
static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
	{ .irq = 24 + OMAP44XX_IRQ_GIC_START },
2646
	{ .irq = -1 }
2647 2648 2649 2650 2651 2652 2653
};

static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
	{ .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
	{ .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
	{ .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
	{ .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2654
	{ .dma_req = -1 }
2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667
};

/* iss master ports */
static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
	&omap44xx_iss__l3_main_2,
};

static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
	{
		.pa_start	= 0x52000000,
		.pa_end		= 0x520000ff,
		.flags		= ADDR_TYPE_RT
	},
2668
	{ }
2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691
};

/* l3_main_2 -> iss */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_iss_hwmod,
	.clk		= "l3_div_ck",
	.addr		= omap44xx_iss_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* iss slave ports */
static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
	&omap44xx_l3_main_2__iss,
};

static struct omap_hwmod_opt_clk iss_opt_clks[] = {
	{ .role = "ctrlclk", .clk = "iss_ctrlclk" },
};

static struct omap_hwmod omap44xx_iss_hwmod = {
	.name		= "iss",
	.class		= &omap44xx_iss_hwmod_class,
2692
	.clkdm_name	= "iss_clkdm",
2693 2694 2695
	.mpu_irqs	= omap44xx_iss_irqs,
	.sdma_reqs	= omap44xx_iss_sdma_reqs,
	.main_clk	= "iss_fck",
2696
	.prcm = {
2697
		.omap4 = {
2698
			.clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2699
			.context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2700
			.modulemode   = MODULEMODE_SWCTRL,
2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711
		},
	},
	.opt_clks	= iss_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(iss_opt_clks),
	.slaves		= omap44xx_iss_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_iss_slaves),
	.masters	= omap44xx_iss_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_iss_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

2712 2713 2714 2715 2716 2717
/*
 * 'iva' class
 * multi-standard video encoder/decoder hardware accelerator
 */

static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2718
	.name	= "iva",
2719 2720 2721 2722 2723 2724 2725
};

/* iva */
static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
	{ .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
	{ .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
	{ .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2726
	{ .irq = -1 }
2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752
};

static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
	{ .name = "logic", .rst_shift = 2 },
};

static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
	{ .name = "seq0", .rst_shift = 0 },
};

static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
	{ .name = "seq1", .rst_shift = 1 },
};

/* iva master ports */
static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
	&omap44xx_iva__l3_main_2,
	&omap44xx_iva__l3_instr,
};

static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
	{
		.pa_start	= 0x5a000000,
		.pa_end		= 0x5a07ffff,
		.flags		= ADDR_TYPE_RT
	},
2753
	{ }
2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774
};

/* l3_main_2 -> iva */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_iva_hwmod,
	.clk		= "l3_div_ck",
	.addr		= omap44xx_iva_addrs,
	.user		= OCP_USER_MPU,
};

/* iva slave ports */
static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
	&omap44xx_dsp__iva,
	&omap44xx_l3_main_2__iva,
};

/* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
	.name		= "iva_seq0",
	.class		= &omap44xx_iva_hwmod_class,
2775
	.clkdm_name	= "ivahd_clkdm",
2776 2777 2778 2779 2780
	.flags		= HWMOD_INIT_NO_RESET,
	.rst_lines	= omap44xx_iva_seq0_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_iva_seq0_resets),
	.prcm = {
		.omap4 = {
2781
			.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2782 2783 2784 2785 2786 2787 2788 2789 2790
		},
	},
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
	.name		= "iva_seq1",
	.class		= &omap44xx_iva_hwmod_class,
2791
	.clkdm_name	= "ivahd_clkdm",
2792 2793 2794 2795 2796
	.flags		= HWMOD_INIT_NO_RESET,
	.rst_lines	= omap44xx_iva_seq1_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_iva_seq1_resets),
	.prcm = {
		.omap4 = {
2797
			.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2798 2799 2800 2801 2802 2803 2804 2805
		},
	},
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

static struct omap_hwmod omap44xx_iva_hwmod = {
	.name		= "iva",
	.class		= &omap44xx_iva_hwmod_class,
2806
	.clkdm_name	= "ivahd_clkdm",
2807 2808 2809 2810 2811 2812
	.mpu_irqs	= omap44xx_iva_irqs,
	.rst_lines	= omap44xx_iva_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_iva_resets),
	.main_clk	= "iva_fck",
	.prcm = {
		.omap4 = {
2813
			.clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2814
			.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2815
			.context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2816
			.modulemode   = MODULEMODE_HWCTRL,
2817 2818 2819 2820 2821 2822 2823 2824 2825
		},
	},
	.slaves		= omap44xx_iva_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_iva_slaves),
	.masters	= omap44xx_iva_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_iva_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'kbd' class
 * keyboard controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
	.name	= "kbd",
	.sysc	= &omap44xx_kbd_sysc,
};

/* kbd */
static struct omap_hwmod omap44xx_kbd_hwmod;
static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
	{ .irq = 120 + OMAP44XX_IRQ_GIC_START },
2852
	{ .irq = -1 }
2853 2854 2855 2856 2857 2858 2859 2860
};

static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
	{
		.pa_start	= 0x4a31c000,
		.pa_end		= 0x4a31c07f,
		.flags		= ADDR_TYPE_RT
	},
2861
	{ }
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};

/* l4_wkup -> kbd */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
	.master		= &omap44xx_l4_wkup_hwmod,
	.slave		= &omap44xx_kbd_hwmod,
	.clk		= "l4_wkup_clk_mux_ck",
	.addr		= omap44xx_kbd_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* kbd slave ports */
static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
	&omap44xx_l4_wkup__kbd,
};

static struct omap_hwmod omap44xx_kbd_hwmod = {
	.name		= "kbd",
	.class		= &omap44xx_kbd_hwmod_class,
2881
	.clkdm_name	= "l4_wkup_clkdm",
2882 2883
	.mpu_irqs	= omap44xx_kbd_irqs,
	.main_clk	= "kbd_fck",
2884
	.prcm = {
2885
		.omap4 = {
2886
			.clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2887
			.context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2888
			.modulemode   = MODULEMODE_SWCTRL,
2889 2890 2891 2892 2893 2894 2895
		},
	},
	.slaves		= omap44xx_kbd_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_kbd_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'mailbox' class
 * mailbox module allowing communication between the on-chip processors using a
 * queued mailbox-interrupt mechanism.
 */

static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
	.name	= "mailbox",
	.sysc	= &omap44xx_mailbox_sysc,
};

/* mailbox */
static struct omap_hwmod omap44xx_mailbox_hwmod;
static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
	{ .irq = 26 + OMAP44XX_IRQ_GIC_START },
2920
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
	{
		.pa_start	= 0x4a0f4000,
		.pa_end		= 0x4a0f41ff,
		.flags		= ADDR_TYPE_RT
	},
2929
	{ }
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};

/* l4_cfg -> mailbox */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_mailbox_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mailbox_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mailbox slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
	&omap44xx_l4_cfg__mailbox,
};

static struct omap_hwmod omap44xx_mailbox_hwmod = {
	.name		= "mailbox",
	.class		= &omap44xx_mailbox_hwmod_class,
2949
	.clkdm_name	= "l4_cfg_clkdm",
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	.mpu_irqs	= omap44xx_mailbox_irqs,
2951
	.prcm = {
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		.omap4 = {
2953
			.clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2954
			.context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
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		},
	},
	.slaves		= omap44xx_mailbox_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mailbox_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'mcbsp' class
 * multi channel buffered serial port controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
	.sysc_offs	= 0x008c,
	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
	.name	= "mcbsp",
	.sysc	= &omap44xx_mcbsp_sysc,
2978
	.rev	= MCBSP_CONFIG_TYPE4,
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};

/* mcbsp1 */
static struct omap_hwmod omap44xx_mcbsp1_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
	{ .irq = 17 + OMAP44XX_IRQ_GIC_START },
2985
	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2991
	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
	{
2996
		.name		= "mpu",
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		.pa_start	= 0x40122000,
		.pa_end		= 0x401220ff,
		.flags		= ADDR_TYPE_RT
	},
3001
	{ }
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};

/* l4_abe -> mcbsp1 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_mcbsp1_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_mcbsp1_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
	{
3015
		.name		= "dma",
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		.pa_start	= 0x49022000,
		.pa_end		= 0x490220ff,
		.flags		= ADDR_TYPE_RT
	},
3020
	{ }
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};

/* l4_abe -> mcbsp1 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_mcbsp1_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_mcbsp1_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* mcbsp1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
	&omap44xx_l4_abe__mcbsp1,
	&omap44xx_l4_abe__mcbsp1_dma,
};

static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
	.name		= "mcbsp1",
	.class		= &omap44xx_mcbsp_hwmod_class,
3041
	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_mcbsp1_irqs,
	.sdma_reqs	= omap44xx_mcbsp1_sdma_reqs,
	.main_clk	= "mcbsp1_fck",
	.prcm = {
		.omap4 = {
3047
			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
3048
			.context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
3049
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
	.slaves		= omap44xx_mcbsp1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcbsp1_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mcbsp2 */
static struct omap_hwmod omap44xx_mcbsp2_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
	{ .irq = 22 + OMAP44XX_IRQ_GIC_START },
3061
	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
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	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
	{
3072
		.name		= "mpu",
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		.pa_start	= 0x40124000,
		.pa_end		= 0x401240ff,
		.flags		= ADDR_TYPE_RT
	},
3077
	{ }
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};

/* l4_abe -> mcbsp2 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_mcbsp2_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_mcbsp2_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
	{
3091
		.name		= "dma",
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		.pa_start	= 0x49024000,
		.pa_end		= 0x490240ff,
		.flags		= ADDR_TYPE_RT
	},
3096
	{ }
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};

/* l4_abe -> mcbsp2 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_mcbsp2_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_mcbsp2_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* mcbsp2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
	&omap44xx_l4_abe__mcbsp2,
	&omap44xx_l4_abe__mcbsp2_dma,
};

static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
	.name		= "mcbsp2",
	.class		= &omap44xx_mcbsp_hwmod_class,
3117
	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_mcbsp2_irqs,
	.sdma_reqs	= omap44xx_mcbsp2_sdma_reqs,
	.main_clk	= "mcbsp2_fck",
	.prcm = {
		.omap4 = {
3123
			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3124
			.context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
3125
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
	.slaves		= omap44xx_mcbsp2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcbsp2_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mcbsp3 */
static struct omap_hwmod omap44xx_mcbsp3_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
	{ .irq = 23 + OMAP44XX_IRQ_GIC_START },
3137
	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
3143
	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
	{
3148
		.name		= "mpu",
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		.pa_start	= 0x40126000,
		.pa_end		= 0x401260ff,
		.flags		= ADDR_TYPE_RT
	},
3153
	{ }
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};

/* l4_abe -> mcbsp3 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_mcbsp3_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_mcbsp3_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
	{
3167
		.name		= "dma",
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		.pa_start	= 0x49026000,
		.pa_end		= 0x490260ff,
		.flags		= ADDR_TYPE_RT
	},
3172
	{ }
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};

/* l4_abe -> mcbsp3 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_mcbsp3_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_mcbsp3_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* mcbsp3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
	&omap44xx_l4_abe__mcbsp3,
	&omap44xx_l4_abe__mcbsp3_dma,
};

static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
	.name		= "mcbsp3",
	.class		= &omap44xx_mcbsp_hwmod_class,
3193
	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_mcbsp3_irqs,
	.sdma_reqs	= omap44xx_mcbsp3_sdma_reqs,
	.main_clk	= "mcbsp3_fck",
	.prcm = {
		.omap4 = {
3199
			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
3200
			.context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
3201
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
	.slaves		= omap44xx_mcbsp3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcbsp3_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mcbsp4 */
static struct omap_hwmod omap44xx_mcbsp4_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
	{ .irq = 16 + OMAP44XX_IRQ_GIC_START },
3213
	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3219
	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
	{
		.pa_start	= 0x48096000,
		.pa_end		= 0x480960ff,
		.flags		= ADDR_TYPE_RT
	},
3228
	{ }
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};

/* l4_per -> mcbsp4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mcbsp4_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mcbsp4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mcbsp4 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
	&omap44xx_l4_per__mcbsp4,
};

static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
	.name		= "mcbsp4",
	.class		= &omap44xx_mcbsp_hwmod_class,
3248
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_mcbsp4_irqs,
	.sdma_reqs	= omap44xx_mcbsp4_sdma_reqs,
	.main_clk	= "mcbsp4_fck",
	.prcm = {
		.omap4 = {
3254
			.clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
3255
			.context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
3256
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
	.slaves		= omap44xx_mcbsp4_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcbsp4_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288
/*
 * 'mcpdm' class
 * multi channel pdm controller (proprietary interface with phoenix power
 * ic)
 */

static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
	.name	= "mcpdm",
	.sysc	= &omap44xx_mcpdm_sysc,
};

/* mcpdm */
static struct omap_hwmod omap44xx_mcpdm_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
	{ .irq = 112 + OMAP44XX_IRQ_GIC_START },
3289
	{ .irq = -1 }
3290 3291 3292 3293 3294
};

static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
	{ .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
	{ .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3295
	{ .dma_req = -1 }
3296 3297 3298 3299 3300 3301 3302 3303
};

static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
	{
		.pa_start	= 0x40132000,
		.pa_end		= 0x4013207f,
		.flags		= ADDR_TYPE_RT
	},
3304
	{ }
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};

/* l4_abe -> mcpdm */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_mcpdm_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_mcpdm_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
	{
		.pa_start	= 0x49032000,
		.pa_end		= 0x4903207f,
		.flags		= ADDR_TYPE_RT
	},
3322
	{ }
3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342
};

/* l4_abe -> mcpdm (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_mcpdm_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_mcpdm_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* mcpdm slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
	&omap44xx_l4_abe__mcpdm,
	&omap44xx_l4_abe__mcpdm_dma,
};

static struct omap_hwmod omap44xx_mcpdm_hwmod = {
	.name		= "mcpdm",
	.class		= &omap44xx_mcpdm_hwmod_class,
3343
	.clkdm_name	= "abe_clkdm",
3344 3345 3346
	.mpu_irqs	= omap44xx_mcpdm_irqs,
	.sdma_reqs	= omap44xx_mcpdm_sdma_reqs,
	.main_clk	= "mcpdm_fck",
3347
	.prcm = {
3348
		.omap4 = {
3349
			.clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3350
			.context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
3351
			.modulemode   = MODULEMODE_SWCTRL,
3352 3353 3354 3355 3356 3357 3358
		},
	},
	.slaves		= omap44xx_mcpdm_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcpdm_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'mcspi' class
 * multichannel serial port interface (mcspi) / master/slave synchronous serial
 * bus
 */

static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
	.name	= "mcspi",
	.sysc	= &omap44xx_mcspi_sysc,
3378
	.rev	= OMAP4_MCSPI_REV,
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};

/* mcspi1 */
static struct omap_hwmod omap44xx_mcspi1_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
	{ .irq = 65 + OMAP44XX_IRQ_GIC_START },
3385
	{ .irq = -1 }
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3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396
};

static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
	{ .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
	{ .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
	{ .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
	{ .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3397
	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
	{
		.pa_start	= 0x48098000,
		.pa_end		= 0x480981ff,
		.flags		= ADDR_TYPE_RT
	},
3406
	{ }
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3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422
};

/* l4_per -> mcspi1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mcspi1_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mcspi1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mcspi1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
	&omap44xx_l4_per__mcspi1,
};

3423 3424 3425 3426 3427
/* mcspi1 dev_attr */
static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
	.num_chipselect	= 4,
};

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static struct omap_hwmod omap44xx_mcspi1_hwmod = {
	.name		= "mcspi1",
	.class		= &omap44xx_mcspi_hwmod_class,
3431
	.clkdm_name	= "l4_per_clkdm",
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3432 3433 3434 3435 3436
	.mpu_irqs	= omap44xx_mcspi1_irqs,
	.sdma_reqs	= omap44xx_mcspi1_sdma_reqs,
	.main_clk	= "mcspi1_fck",
	.prcm = {
		.omap4 = {
3437
			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
3438
			.context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
3439
			.modulemode   = MODULEMODE_SWCTRL,
B
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3440 3441
		},
	},
3442
	.dev_attr	= &mcspi1_dev_attr,
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3443 3444 3445 3446 3447 3448 3449 3450 3451
	.slaves		= omap44xx_mcspi1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi1_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mcspi2 */
static struct omap_hwmod omap44xx_mcspi2_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
	{ .irq = 66 + OMAP44XX_IRQ_GIC_START },
3452
	{ .irq = -1 }
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3453 3454 3455 3456 3457 3458 3459
};

static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
	{ .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
	{ .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3460
	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
	{
		.pa_start	= 0x4809a000,
		.pa_end		= 0x4809a1ff,
		.flags		= ADDR_TYPE_RT
	},
3469
	{ }
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3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485
};

/* l4_per -> mcspi2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mcspi2_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mcspi2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mcspi2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
	&omap44xx_l4_per__mcspi2,
};

3486 3487 3488 3489 3490
/* mcspi2 dev_attr */
static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
	.num_chipselect	= 2,
};

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static struct omap_hwmod omap44xx_mcspi2_hwmod = {
	.name		= "mcspi2",
	.class		= &omap44xx_mcspi_hwmod_class,
3494
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_mcspi2_irqs,
	.sdma_reqs	= omap44xx_mcspi2_sdma_reqs,
	.main_clk	= "mcspi2_fck",
	.prcm = {
		.omap4 = {
3500
			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
3501
			.context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
3502
			.modulemode   = MODULEMODE_SWCTRL,
B
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3503 3504
		},
	},
3505
	.dev_attr	= &mcspi2_dev_attr,
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	.slaves		= omap44xx_mcspi2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi2_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mcspi3 */
static struct omap_hwmod omap44xx_mcspi3_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
	{ .irq = 91 + OMAP44XX_IRQ_GIC_START },
3515
	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
	{ .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
	{ .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3523
	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
	{
		.pa_start	= 0x480b8000,
		.pa_end		= 0x480b81ff,
		.flags		= ADDR_TYPE_RT
	},
3532
	{ }
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};

/* l4_per -> mcspi3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mcspi3_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mcspi3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mcspi3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
	&omap44xx_l4_per__mcspi3,
};

3549 3550 3551 3552 3553
/* mcspi3 dev_attr */
static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
	.num_chipselect	= 2,
};

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static struct omap_hwmod omap44xx_mcspi3_hwmod = {
	.name		= "mcspi3",
	.class		= &omap44xx_mcspi_hwmod_class,
3557
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_mcspi3_irqs,
	.sdma_reqs	= omap44xx_mcspi3_sdma_reqs,
	.main_clk	= "mcspi3_fck",
	.prcm = {
		.omap4 = {
3563
			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
3564
			.context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
3565
			.modulemode   = MODULEMODE_SWCTRL,
B
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3566 3567
		},
	},
3568
	.dev_attr	= &mcspi3_dev_attr,
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3569 3570 3571 3572 3573 3574 3575 3576 3577
	.slaves		= omap44xx_mcspi3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi3_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mcspi4 */
static struct omap_hwmod omap44xx_mcspi4_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
	{ .irq = 48 + OMAP44XX_IRQ_GIC_START },
3578
	{ .irq = -1 }
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3579 3580 3581 3582 3583
};

static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
	{ .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3584
	{ .dma_req = -1 }
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3585 3586 3587 3588 3589 3590 3591 3592
};

static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
	{
		.pa_start	= 0x480ba000,
		.pa_end		= 0x480ba1ff,
		.flags		= ADDR_TYPE_RT
	},
3593
	{ }
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};

/* l4_per -> mcspi4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mcspi4_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mcspi4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mcspi4 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
	&omap44xx_l4_per__mcspi4,
};

3610 3611 3612 3613 3614
/* mcspi4 dev_attr */
static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
	.num_chipselect	= 1,
};

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static struct omap_hwmod omap44xx_mcspi4_hwmod = {
	.name		= "mcspi4",
	.class		= &omap44xx_mcspi_hwmod_class,
3618
	.clkdm_name	= "l4_per_clkdm",
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3619 3620 3621 3622 3623
	.mpu_irqs	= omap44xx_mcspi4_irqs,
	.sdma_reqs	= omap44xx_mcspi4_sdma_reqs,
	.main_clk	= "mcspi4_fck",
	.prcm = {
		.omap4 = {
3624
			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
3625
			.context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
3626
			.modulemode   = MODULEMODE_SWCTRL,
B
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3627 3628
		},
	},
3629
	.dev_attr	= &mcspi4_dev_attr,
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3630 3631 3632 3633 3634
	.slaves		= omap44xx_mcspi4_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi4_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647
/*
 * 'mmc' class
 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
			   SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3648
			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
	.name	= "mmc",
	.sysc	= &omap44xx_mmc_sysc,
};

/* mmc1 */
static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
	{ .irq = 83 + OMAP44XX_IRQ_GIC_START },
3660
	{ .irq = -1 }
3661 3662 3663 3664 3665
};

static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3666
	{ .dma_req = -1 }
3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679
};

/* mmc1 master ports */
static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
	&omap44xx_mmc1__l3_main_1,
};

static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
	{
		.pa_start	= 0x4809c000,
		.pa_end		= 0x4809c3ff,
		.flags		= ADDR_TYPE_RT
	},
3680
	{ }
3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696
};

/* l4_per -> mmc1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mmc1_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mmc1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mmc1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
	&omap44xx_l4_per__mmc1,
};

3697 3698 3699 3700 3701
/* mmc1 dev_attr */
static struct omap_mmc_dev_attr mmc1_dev_attr = {
	.flags	= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
};

3702 3703 3704
static struct omap_hwmod omap44xx_mmc1_hwmod = {
	.name		= "mmc1",
	.class		= &omap44xx_mmc_hwmod_class,
3705
	.clkdm_name	= "l3_init_clkdm",
3706 3707 3708
	.mpu_irqs	= omap44xx_mmc1_irqs,
	.sdma_reqs	= omap44xx_mmc1_sdma_reqs,
	.main_clk	= "mmc1_fck",
3709
	.prcm = {
3710
		.omap4 = {
3711
			.clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3712
			.context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
3713
			.modulemode   = MODULEMODE_SWCTRL,
3714 3715
		},
	},
3716
	.dev_attr	= &mmc1_dev_attr,
3717 3718 3719 3720 3721 3722 3723 3724 3725 3726
	.slaves		= omap44xx_mmc1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mmc1_slaves),
	.masters	= omap44xx_mmc1_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_mmc1_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mmc2 */
static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
	{ .irq = 86 + OMAP44XX_IRQ_GIC_START },
3727
	{ .irq = -1 }
3728 3729 3730 3731 3732
};

static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3733
	{ .dma_req = -1 }
3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746
};

/* mmc2 master ports */
static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
	&omap44xx_mmc2__l3_main_1,
};

static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
	{
		.pa_start	= 0x480b4000,
		.pa_end		= 0x480b43ff,
		.flags		= ADDR_TYPE_RT
	},
3747
	{ }
3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766
};

/* l4_per -> mmc2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mmc2_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mmc2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mmc2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
	&omap44xx_l4_per__mmc2,
};

static struct omap_hwmod omap44xx_mmc2_hwmod = {
	.name		= "mmc2",
	.class		= &omap44xx_mmc_hwmod_class,
3767
	.clkdm_name	= "l3_init_clkdm",
3768 3769 3770
	.mpu_irqs	= omap44xx_mmc2_irqs,
	.sdma_reqs	= omap44xx_mmc2_sdma_reqs,
	.main_clk	= "mmc2_fck",
3771
	.prcm = {
3772
		.omap4 = {
3773
			.clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3774
			.context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
3775
			.modulemode   = MODULEMODE_SWCTRL,
3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788
		},
	},
	.slaves		= omap44xx_mmc2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mmc2_slaves),
	.masters	= omap44xx_mmc2_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_mmc2_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mmc3 */
static struct omap_hwmod omap44xx_mmc3_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
	{ .irq = 94 + OMAP44XX_IRQ_GIC_START },
3789
	{ .irq = -1 }
3790 3791 3792 3793 3794
};

static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3795
	{ .dma_req = -1 }
3796 3797 3798 3799 3800 3801 3802 3803
};

static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
	{
		.pa_start	= 0x480ad000,
		.pa_end		= 0x480ad3ff,
		.flags		= ADDR_TYPE_RT
	},
3804
	{ }
3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823
};

/* l4_per -> mmc3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mmc3_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mmc3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mmc3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
	&omap44xx_l4_per__mmc3,
};

static struct omap_hwmod omap44xx_mmc3_hwmod = {
	.name		= "mmc3",
	.class		= &omap44xx_mmc_hwmod_class,
3824
	.clkdm_name	= "l4_per_clkdm",
3825 3826 3827
	.mpu_irqs	= omap44xx_mmc3_irqs,
	.sdma_reqs	= omap44xx_mmc3_sdma_reqs,
	.main_clk	= "mmc3_fck",
3828
	.prcm = {
3829
		.omap4 = {
3830
			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3831
			.context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
3832
			.modulemode   = MODULEMODE_SWCTRL,
3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843
		},
	},
	.slaves		= omap44xx_mmc3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mmc3_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mmc4 */
static struct omap_hwmod omap44xx_mmc4_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
	{ .irq = 96 + OMAP44XX_IRQ_GIC_START },
3844
	{ .irq = -1 }
3845 3846 3847 3848 3849
};

static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3850
	{ .dma_req = -1 }
3851 3852 3853 3854 3855 3856 3857 3858
};

static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
	{
		.pa_start	= 0x480d1000,
		.pa_end		= 0x480d13ff,
		.flags		= ADDR_TYPE_RT
	},
3859
	{ }
3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878
};

/* l4_per -> mmc4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mmc4_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mmc4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mmc4 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
	&omap44xx_l4_per__mmc4,
};

static struct omap_hwmod omap44xx_mmc4_hwmod = {
	.name		= "mmc4",
	.class		= &omap44xx_mmc_hwmod_class,
3879
	.clkdm_name	= "l4_per_clkdm",
3880
	.mpu_irqs	= omap44xx_mmc4_irqs,
3881

3882 3883
	.sdma_reqs	= omap44xx_mmc4_sdma_reqs,
	.main_clk	= "mmc4_fck",
3884
	.prcm = {
3885
		.omap4 = {
3886
			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3887
			.context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
3888
			.modulemode   = MODULEMODE_SWCTRL,
3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899
		},
	},
	.slaves		= omap44xx_mmc4_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mmc4_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mmc5 */
static struct omap_hwmod omap44xx_mmc5_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
	{ .irq = 59 + OMAP44XX_IRQ_GIC_START },
3900
	{ .irq = -1 }
3901 3902 3903 3904 3905
};

static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3906
	{ .dma_req = -1 }
3907 3908 3909 3910 3911 3912 3913 3914
};

static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
	{
		.pa_start	= 0x480d5000,
		.pa_end		= 0x480d53ff,
		.flags		= ADDR_TYPE_RT
	},
3915
	{ }
3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934
};

/* l4_per -> mmc5 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mmc5_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mmc5_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mmc5 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
	&omap44xx_l4_per__mmc5,
};

static struct omap_hwmod omap44xx_mmc5_hwmod = {
	.name		= "mmc5",
	.class		= &omap44xx_mmc_hwmod_class,
3935
	.clkdm_name	= "l4_per_clkdm",
3936 3937 3938
	.mpu_irqs	= omap44xx_mmc5_irqs,
	.sdma_reqs	= omap44xx_mmc5_sdma_reqs,
	.main_clk	= "mmc5_fck",
3939
	.prcm = {
3940
		.omap4 = {
3941
			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3942
			.context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
3943
			.modulemode   = MODULEMODE_SWCTRL,
3944 3945 3946 3947 3948 3949 3950
		},
	},
	.slaves		= omap44xx_mmc5_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mmc5_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

3951 3952 3953 3954 3955 3956
/*
 * 'mpu' class
 * mpu sub-system
 */

static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3957
	.name	= "mpu",
3958 3959
};

3960 3961 3962 3963 3964
/* mpu */
static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
	{ .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
	{ .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
	{ .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3965
	{ .irq = -1 }
3966 3967
};

3968 3969 3970 3971 3972 3973 3974 3975 3976 3977
/* mpu master ports */
static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
	&omap44xx_mpu__l3_main_1,
	&omap44xx_mpu__l4_abe,
	&omap44xx_mpu__dmm,
};

static struct omap_hwmod omap44xx_mpu_hwmod = {
	.name		= "mpu",
	.class		= &omap44xx_mpu_hwmod_class,
3978
	.clkdm_name	= "mpuss_clkdm",
3979
	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3980 3981
	.mpu_irqs	= omap44xx_mpu_irqs,
	.main_clk	= "dpll_mpu_m2_ck",
3982 3983
	.prcm = {
		.omap4 = {
3984
			.clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
3985
			.context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3986 3987
		},
	},
3988 3989
	.masters	= omap44xx_mpu_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_mpu_masters),
3990 3991 3992
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013
/*
 * 'smartreflex' class
 * smartreflex module (monitor silicon performance and outputs a measure of
 * performance error)
 */

/* The IP is not compliant to type1 / type2 scheme */
static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
	.sidle_shift	= 24,
	.enwkup_shift	= 26,
};

static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
	.sysc_offs	= 0x0038,
	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type_smartreflex,
};

static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
4014 4015 4016
	.name	= "smartreflex",
	.sysc	= &omap44xx_smartreflex_sysc,
	.rev	= 2,
4017 4018 4019 4020 4021 4022
};

/* smartreflex_core */
static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
	{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
4023
	{ .irq = -1 }
4024 4025 4026 4027 4028 4029 4030 4031
};

static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
	{
		.pa_start	= 0x4a0dd000,
		.pa_end		= 0x4a0dd03f,
		.flags		= ADDR_TYPE_RT
	},
4032
	{ }
4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051
};

/* l4_cfg -> smartreflex_core */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_smartreflex_core_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_smartreflex_core_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* smartreflex_core slave ports */
static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
	&omap44xx_l4_cfg__smartreflex_core,
};

static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
	.name		= "smartreflex_core",
	.class		= &omap44xx_smartreflex_hwmod_class,
4052
	.clkdm_name	= "l4_ao_clkdm",
4053
	.mpu_irqs	= omap44xx_smartreflex_core_irqs,
4054

4055 4056 4057 4058
	.main_clk	= "smartreflex_core_fck",
	.vdd_name	= "core",
	.prcm = {
		.omap4 = {
4059
			.clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
4060
			.context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
4061
			.modulemode   = MODULEMODE_SWCTRL,
4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072
		},
	},
	.slaves		= omap44xx_smartreflex_core_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* smartreflex_iva */
static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
	{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
4073
	{ .irq = -1 }
4074 4075 4076 4077 4078 4079 4080 4081
};

static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
	{
		.pa_start	= 0x4a0db000,
		.pa_end		= 0x4a0db03f,
		.flags		= ADDR_TYPE_RT
	},
4082
	{ }
4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101
};

/* l4_cfg -> smartreflex_iva */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_smartreflex_iva_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_smartreflex_iva_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* smartreflex_iva slave ports */
static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
	&omap44xx_l4_cfg__smartreflex_iva,
};

static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
	.name		= "smartreflex_iva",
	.class		= &omap44xx_smartreflex_hwmod_class,
4102
	.clkdm_name	= "l4_ao_clkdm",
4103 4104 4105 4106 4107
	.mpu_irqs	= omap44xx_smartreflex_iva_irqs,
	.main_clk	= "smartreflex_iva_fck",
	.vdd_name	= "iva",
	.prcm = {
		.omap4 = {
4108
			.clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
4109
			.context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
4110
			.modulemode   = MODULEMODE_SWCTRL,
4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121
		},
	},
	.slaves		= omap44xx_smartreflex_iva_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* smartreflex_mpu */
static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
	{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
4122
	{ .irq = -1 }
4123 4124 4125 4126 4127 4128 4129 4130
};

static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
	{
		.pa_start	= 0x4a0d9000,
		.pa_end		= 0x4a0d903f,
		.flags		= ADDR_TYPE_RT
	},
4131
	{ }
4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 4150
};

/* l4_cfg -> smartreflex_mpu */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_smartreflex_mpu_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_smartreflex_mpu_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* smartreflex_mpu slave ports */
static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
	&omap44xx_l4_cfg__smartreflex_mpu,
};

static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
	.name		= "smartreflex_mpu",
	.class		= &omap44xx_smartreflex_hwmod_class,
4151
	.clkdm_name	= "l4_ao_clkdm",
4152 4153 4154 4155 4156
	.mpu_irqs	= omap44xx_smartreflex_mpu_irqs,
	.main_clk	= "smartreflex_mpu_fck",
	.vdd_name	= "mpu",
	.prcm = {
		.omap4 = {
4157
			.clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
4158
			.context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
4159
			.modulemode   = MODULEMODE_SWCTRL,
4160 4161 4162 4163 4164 4165 4166
		},
	},
	.slaves		= omap44xx_smartreflex_mpu_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197
/*
 * 'spinlock' class
 * spinlock provides hardware assistance for synchronizing the processes
 * running on multiple processors
 */

static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
	.name	= "spinlock",
	.sysc	= &omap44xx_spinlock_sysc,
};

/* spinlock */
static struct omap_hwmod omap44xx_spinlock_hwmod;
static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
	{
		.pa_start	= 0x4a0f6000,
		.pa_end		= 0x4a0f6fff,
		.flags		= ADDR_TYPE_RT
	},
4198
	{ }
4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217
};

/* l4_cfg -> spinlock */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_spinlock_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_spinlock_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* spinlock slave ports */
static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
	&omap44xx_l4_cfg__spinlock,
};

static struct omap_hwmod omap44xx_spinlock_hwmod = {
	.name		= "spinlock",
	.class		= &omap44xx_spinlock_hwmod_class,
4218
	.clkdm_name	= "l4_cfg_clkdm",
4219 4220
	.prcm = {
		.omap4 = {
4221
			.clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
4222
			.context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4223 4224 4225 4226 4227 4228 4229
		},
	},
	.slaves		= omap44xx_spinlock_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_spinlock_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271
/*
 * 'timer' class
 * general purpose timer module with accurate 1ms tick
 * This class contains several variants: ['timer_1ms', 'timer']
 */

static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
	.name	= "timer",
	.sysc	= &omap44xx_timer_1ms_sysc,
};

static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
	.name	= "timer",
	.sysc	= &omap44xx_timer_sysc,
};

/* timer1 */
static struct omap_hwmod omap44xx_timer1_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
	{ .irq = 37 + OMAP44XX_IRQ_GIC_START },
4272
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
	{
		.pa_start	= 0x4a318000,
		.pa_end		= 0x4a31807f,
		.flags		= ADDR_TYPE_RT
	},
4281
	{ }
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};

/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
	.master		= &omap44xx_l4_wkup_hwmod,
	.slave		= &omap44xx_timer1_hwmod,
	.clk		= "l4_wkup_clk_mux_ck",
	.addr		= omap44xx_timer1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* timer1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
	&omap44xx_l4_wkup__timer1,
};

static struct omap_hwmod omap44xx_timer1_hwmod = {
	.name		= "timer1",
	.class		= &omap44xx_timer_1ms_hwmod_class,
4301
	.clkdm_name	= "l4_wkup_clkdm",
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	.mpu_irqs	= omap44xx_timer1_irqs,
	.main_clk	= "timer1_fck",
	.prcm = {
		.omap4 = {
4306
			.clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
4307
			.context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
4308
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
	.slaves		= omap44xx_timer1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer1_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer2 */
static struct omap_hwmod omap44xx_timer2_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
	{ .irq = 38 + OMAP44XX_IRQ_GIC_START },
4320
	{ .irq = -1 }
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4321 4322 4323 4324 4325 4326 4327 4328
};

static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
	{
		.pa_start	= 0x48032000,
		.pa_end		= 0x4803207f,
		.flags		= ADDR_TYPE_RT
	},
4329
	{ }
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};

/* l4_per -> timer2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_timer2_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_timer2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* timer2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
	&omap44xx_l4_per__timer2,
};

static struct omap_hwmod omap44xx_timer2_hwmod = {
	.name		= "timer2",
	.class		= &omap44xx_timer_1ms_hwmod_class,
4349
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_timer2_irqs,
	.main_clk	= "timer2_fck",
	.prcm = {
		.omap4 = {
4354
			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
4355
			.context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
4356
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
	.slaves		= omap44xx_timer2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer2_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer3 */
static struct omap_hwmod omap44xx_timer3_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
	{ .irq = 39 + OMAP44XX_IRQ_GIC_START },
4368
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
	{
		.pa_start	= 0x48034000,
		.pa_end		= 0x4803407f,
		.flags		= ADDR_TYPE_RT
	},
4377
	{ }
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};

/* l4_per -> timer3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_timer3_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_timer3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* timer3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
	&omap44xx_l4_per__timer3,
};

static struct omap_hwmod omap44xx_timer3_hwmod = {
	.name		= "timer3",
	.class		= &omap44xx_timer_hwmod_class,
4397
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_timer3_irqs,
	.main_clk	= "timer3_fck",
	.prcm = {
		.omap4 = {
4402
			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
4403
			.context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
4404
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
	.slaves		= omap44xx_timer3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer3_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer4 */
static struct omap_hwmod omap44xx_timer4_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
	{ .irq = 40 + OMAP44XX_IRQ_GIC_START },
4416
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
	{
		.pa_start	= 0x48036000,
		.pa_end		= 0x4803607f,
		.flags		= ADDR_TYPE_RT
	},
4425
	{ }
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};

/* l4_per -> timer4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_timer4_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_timer4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* timer4 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
	&omap44xx_l4_per__timer4,
};

static struct omap_hwmod omap44xx_timer4_hwmod = {
	.name		= "timer4",
	.class		= &omap44xx_timer_hwmod_class,
4445
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_timer4_irqs,
	.main_clk	= "timer4_fck",
	.prcm = {
		.omap4 = {
4450
			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
4451
			.context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
4452
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
	.slaves		= omap44xx_timer4_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer4_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer5 */
static struct omap_hwmod omap44xx_timer5_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
	{ .irq = 41 + OMAP44XX_IRQ_GIC_START },
4464
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
	{
		.pa_start	= 0x40138000,
		.pa_end		= 0x4013807f,
		.flags		= ADDR_TYPE_RT
	},
4473
	{ }
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};

/* l4_abe -> timer5 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_timer5_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_timer5_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
	{
		.pa_start	= 0x49038000,
		.pa_end		= 0x4903807f,
		.flags		= ADDR_TYPE_RT
	},
4491
	{ }
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};

/* l4_abe -> timer5 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_timer5_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_timer5_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* timer5 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
	&omap44xx_l4_abe__timer5,
	&omap44xx_l4_abe__timer5_dma,
};

static struct omap_hwmod omap44xx_timer5_hwmod = {
	.name		= "timer5",
	.class		= &omap44xx_timer_hwmod_class,
4512
	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_timer5_irqs,
	.main_clk	= "timer5_fck",
	.prcm = {
		.omap4 = {
4517
			.clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
4518
			.context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
4519
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
	.slaves		= omap44xx_timer5_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer5_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer6 */
static struct omap_hwmod omap44xx_timer6_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
	{ .irq = 42 + OMAP44XX_IRQ_GIC_START },
4531
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
	{
		.pa_start	= 0x4013a000,
		.pa_end		= 0x4013a07f,
		.flags		= ADDR_TYPE_RT
	},
4540
	{ }
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};

/* l4_abe -> timer6 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_timer6_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_timer6_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
	{
		.pa_start	= 0x4903a000,
		.pa_end		= 0x4903a07f,
		.flags		= ADDR_TYPE_RT
	},
4558
	{ }
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};

/* l4_abe -> timer6 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_timer6_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_timer6_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* timer6 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
	&omap44xx_l4_abe__timer6,
	&omap44xx_l4_abe__timer6_dma,
};

static struct omap_hwmod omap44xx_timer6_hwmod = {
	.name		= "timer6",
	.class		= &omap44xx_timer_hwmod_class,
4579
	.clkdm_name	= "abe_clkdm",
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4580
	.mpu_irqs	= omap44xx_timer6_irqs,
4581

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	.main_clk	= "timer6_fck",
	.prcm = {
		.omap4 = {
4585
			.clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
4586
			.context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
4587
			.modulemode   = MODULEMODE_SWCTRL,
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4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598
		},
	},
	.slaves		= omap44xx_timer6_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer6_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer7 */
static struct omap_hwmod omap44xx_timer7_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
	{ .irq = 43 + OMAP44XX_IRQ_GIC_START },
4599
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
	{
		.pa_start	= 0x4013c000,
		.pa_end		= 0x4013c07f,
		.flags		= ADDR_TYPE_RT
	},
4608
	{ }
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};

/* l4_abe -> timer7 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_timer7_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_timer7_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
	{
		.pa_start	= 0x4903c000,
		.pa_end		= 0x4903c07f,
		.flags		= ADDR_TYPE_RT
	},
4626
	{ }
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4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646
};

/* l4_abe -> timer7 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_timer7_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_timer7_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* timer7 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
	&omap44xx_l4_abe__timer7,
	&omap44xx_l4_abe__timer7_dma,
};

static struct omap_hwmod omap44xx_timer7_hwmod = {
	.name		= "timer7",
	.class		= &omap44xx_timer_hwmod_class,
4647
	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_timer7_irqs,
	.main_clk	= "timer7_fck",
	.prcm = {
		.omap4 = {
4652
			.clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
4653
			.context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
4654
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
	.slaves		= omap44xx_timer7_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer7_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer8 */
static struct omap_hwmod omap44xx_timer8_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
	{ .irq = 44 + OMAP44XX_IRQ_GIC_START },
4666
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
	{
		.pa_start	= 0x4013e000,
		.pa_end		= 0x4013e07f,
		.flags		= ADDR_TYPE_RT
	},
4675
	{ }
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};

/* l4_abe -> timer8 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_timer8_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_timer8_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
	{
		.pa_start	= 0x4903e000,
		.pa_end		= 0x4903e07f,
		.flags		= ADDR_TYPE_RT
	},
4693
	{ }
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};

/* l4_abe -> timer8 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_timer8_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_timer8_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* timer8 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
	&omap44xx_l4_abe__timer8,
	&omap44xx_l4_abe__timer8_dma,
};

static struct omap_hwmod omap44xx_timer8_hwmod = {
	.name		= "timer8",
	.class		= &omap44xx_timer_hwmod_class,
4714
	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_timer8_irqs,
	.main_clk	= "timer8_fck",
	.prcm = {
		.omap4 = {
4719
			.clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
4720
			.context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
4721
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
	.slaves		= omap44xx_timer8_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer8_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer9 */
static struct omap_hwmod omap44xx_timer9_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
	{ .irq = 45 + OMAP44XX_IRQ_GIC_START },
4733
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
	{
		.pa_start	= 0x4803e000,
		.pa_end		= 0x4803e07f,
		.flags		= ADDR_TYPE_RT
	},
4742
	{ }
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};

/* l4_per -> timer9 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_timer9_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_timer9_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* timer9 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
	&omap44xx_l4_per__timer9,
};

static struct omap_hwmod omap44xx_timer9_hwmod = {
	.name		= "timer9",
	.class		= &omap44xx_timer_hwmod_class,
4762
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_timer9_irqs,
	.main_clk	= "timer9_fck",
	.prcm = {
		.omap4 = {
4767
			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
4768
			.context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
4769
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
	.slaves		= omap44xx_timer9_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer9_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer10 */
static struct omap_hwmod omap44xx_timer10_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
	{ .irq = 46 + OMAP44XX_IRQ_GIC_START },
4781
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
	{
		.pa_start	= 0x48086000,
		.pa_end		= 0x4808607f,
		.flags		= ADDR_TYPE_RT
	},
4790
	{ }
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};

/* l4_per -> timer10 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_timer10_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_timer10_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* timer10 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
	&omap44xx_l4_per__timer10,
};

static struct omap_hwmod omap44xx_timer10_hwmod = {
	.name		= "timer10",
	.class		= &omap44xx_timer_1ms_hwmod_class,
4810
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_timer10_irqs,
	.main_clk	= "timer10_fck",
	.prcm = {
		.omap4 = {
4815
			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
4816
			.context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
4817
			.modulemode   = MODULEMODE_SWCTRL,
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4818 4819 4820 4821 4822 4823 4824 4825 4826 4827 4828
		},
	},
	.slaves		= omap44xx_timer10_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer10_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer11 */
static struct omap_hwmod omap44xx_timer11_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
	{ .irq = 47 + OMAP44XX_IRQ_GIC_START },
4829
	{ .irq = -1 }
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4830 4831 4832 4833 4834 4835 4836 4837
};

static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
	{
		.pa_start	= 0x48088000,
		.pa_end		= 0x4808807f,
		.flags		= ADDR_TYPE_RT
	},
4838
	{ }
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};

/* l4_per -> timer11 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_timer11_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_timer11_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* timer11 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
	&omap44xx_l4_per__timer11,
};

static struct omap_hwmod omap44xx_timer11_hwmod = {
	.name		= "timer11",
	.class		= &omap44xx_timer_hwmod_class,
4858
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_timer11_irqs,
	.main_clk	= "timer11_fck",
	.prcm = {
		.omap4 = {
4863
			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
4864
			.context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
4865
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
	.slaves		= omap44xx_timer11_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer11_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
4874 4875
 * 'uart' class
 * universal asynchronous receiver/transmitter (uart)
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 */

4878 4879 4880 4881 4882
static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
	.rev_offs	= 0x0050,
	.sysc_offs	= 0x0054,
	.syss_offs	= 0x0058,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4883 4884
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
4885 4886
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
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	.sysc_fields	= &omap_hwmod_sysc_type1,
};

4890
static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4891 4892
	.name	= "uart",
	.sysc	= &omap44xx_uart_sysc,
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};

4895 4896 4897 4898
/* uart1 */
static struct omap_hwmod omap44xx_uart1_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
	{ .irq = 72 + OMAP44XX_IRQ_GIC_START },
4899
	{ .irq = -1 }
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};

4902 4903 4904
static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4905
	{ .dma_req = -1 }
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};

4908
static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
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	{
4910 4911
		.pa_start	= 0x4806a000,
		.pa_end		= 0x4806a0ff,
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		.flags		= ADDR_TYPE_RT
	},
4914
	{ }
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};

4917 4918 4919 4920 4921 4922
/* l4_per -> uart1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_uart1_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_uart1_addrs,
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	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

4926 4927 4928
/* uart1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
	&omap44xx_l4_per__uart1,
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};

4931 4932 4933
static struct omap_hwmod omap44xx_uart1_hwmod = {
	.name		= "uart1",
	.class		= &omap44xx_uart_hwmod_class,
4934
	.clkdm_name	= "l4_per_clkdm",
4935 4936 4937
	.mpu_irqs	= omap44xx_uart1_irqs,
	.sdma_reqs	= omap44xx_uart1_sdma_reqs,
	.main_clk	= "uart1_fck",
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	.prcm = {
		.omap4 = {
4940
			.clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
4941
			.context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
4942
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
4945 4946
	.slaves		= omap44xx_uart1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_uart1_slaves),
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	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

4950 4951 4952 4953
/* uart2 */
static struct omap_hwmod omap44xx_uart2_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
	{ .irq = 73 + OMAP44XX_IRQ_GIC_START },
4954
	{ .irq = -1 }
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};

4957 4958 4959
static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4960
	{ .dma_req = -1 }
4961 4962 4963
};

static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
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	{
4965 4966
		.pa_start	= 0x4806c000,
		.pa_end		= 0x4806c0ff,
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		.flags		= ADDR_TYPE_RT
	},
4969
	{ }
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};

4972 4973
/* l4_per -> uart2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
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	.master		= &omap44xx_l4_per_hwmod,
4975 4976 4977
	.slave		= &omap44xx_uart2_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_uart2_addrs,
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	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

4981 4982 4983
/* uart2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
	&omap44xx_l4_per__uart2,
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};

4986 4987 4988
static struct omap_hwmod omap44xx_uart2_hwmod = {
	.name		= "uart2",
	.class		= &omap44xx_uart_hwmod_class,
4989
	.clkdm_name	= "l4_per_clkdm",
4990 4991 4992
	.mpu_irqs	= omap44xx_uart2_irqs,
	.sdma_reqs	= omap44xx_uart2_sdma_reqs,
	.main_clk	= "uart2_fck",
B
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	.prcm = {
		.omap4 = {
4995
			.clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
4996
			.context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
4997
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
5000 5001
	.slaves		= omap44xx_uart2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_uart2_slaves),
B
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	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

5005 5006 5007 5008
/* uart3 */
static struct omap_hwmod omap44xx_uart3_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
	{ .irq = 74 + OMAP44XX_IRQ_GIC_START },
5009
	{ .irq = -1 }
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5010 5011
};

5012 5013 5014
static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
5015
	{ .dma_req = -1 }
5016 5017 5018
};

static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
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	{
5020 5021
		.pa_start	= 0x48020000,
		.pa_end		= 0x480200ff,
B
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5022 5023
		.flags		= ADDR_TYPE_RT
	},
5024
	{ }
B
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};

5027 5028
/* l4_per -> uart3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
B
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5029
	.master		= &omap44xx_l4_per_hwmod,
5030 5031 5032
	.slave		= &omap44xx_uart3_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_uart3_addrs,
B
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5033 5034 5035
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

5036 5037 5038 5039 5040 5041 5042 5043
/* uart3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
	&omap44xx_l4_per__uart3,
};

static struct omap_hwmod omap44xx_uart3_hwmod = {
	.name		= "uart3",
	.class		= &omap44xx_uart_hwmod_class,
5044
	.clkdm_name	= "l4_per_clkdm",
5045
	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
5046 5047 5048
	.mpu_irqs	= omap44xx_uart3_irqs,
	.sdma_reqs	= omap44xx_uart3_sdma_reqs,
	.main_clk	= "uart3_fck",
B
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	.prcm = {
		.omap4 = {
5051
			.clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
5052
			.context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
5053
			.modulemode   = MODULEMODE_SWCTRL,
B
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5054 5055
		},
	},
5056 5057
	.slaves		= omap44xx_uart3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_uart3_slaves),
B
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5058 5059 5060
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

5061 5062 5063 5064
/* uart4 */
static struct omap_hwmod omap44xx_uart4_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
	{ .irq = 70 + OMAP44XX_IRQ_GIC_START },
5065
	{ .irq = -1 }
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5066 5067
};

5068 5069 5070
static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
5071
	{ .dma_req = -1 }
5072 5073 5074
};

static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
B
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5075
	{
5076 5077
		.pa_start	= 0x4806e000,
		.pa_end		= 0x4806e0ff,
B
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5078 5079
		.flags		= ADDR_TYPE_RT
	},
5080
	{ }
B
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5081 5082
};

5083 5084
/* l4_per -> uart4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
B
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5085
	.master		= &omap44xx_l4_per_hwmod,
5086 5087 5088
	.slave		= &omap44xx_uart4_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_uart4_addrs,
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5089 5090 5091
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

5092 5093 5094
/* uart4 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
	&omap44xx_l4_per__uart4,
B
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5095 5096
};

5097 5098 5099
static struct omap_hwmod omap44xx_uart4_hwmod = {
	.name		= "uart4",
	.class		= &omap44xx_uart_hwmod_class,
5100
	.clkdm_name	= "l4_per_clkdm",
5101 5102 5103
	.mpu_irqs	= omap44xx_uart4_irqs,
	.sdma_reqs	= omap44xx_uart4_sdma_reqs,
	.main_clk	= "uart4_fck",
B
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5104 5105
	.prcm = {
		.omap4 = {
5106
			.clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
5107
			.context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
5108
			.modulemode   = MODULEMODE_SWCTRL,
B
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5109 5110
		},
	},
5111 5112
	.slaves		= omap44xx_uart4_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_uart4_slaves),
B
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5113 5114 5115
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

B
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5116 5117 5118 5119 5120 5121 5122 5123 5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134
/*
 * 'usb_otg_hs' class
 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
	.rev_offs	= 0x0400,
	.sysc_offs	= 0x0404,
	.syss_offs	= 0x0408,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
			   SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
			   MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
5135 5136
	.name	= "usb_otg_hs",
	.sysc	= &omap44xx_usb_otg_hs_sysc,
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5137 5138 5139 5140 5141 5142
};

/* usb_otg_hs */
static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
	{ .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
	{ .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
5143
	{ .irq = -1 }
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5144 5145 5146 5147 5148 5149 5150 5151 5152 5153 5154 5155 5156
};

/* usb_otg_hs master ports */
static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
	&omap44xx_usb_otg_hs__l3_main_2,
};

static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
	{
		.pa_start	= 0x4a0ab000,
		.pa_end		= 0x4a0ab003,
		.flags		= ADDR_TYPE_RT
	},
5157
	{ }
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5158 5159 5160 5161 5162 5163 5164 5165 5166 5167 5168 5169 5170 5171 5172 5173 5174 5175 5176 5177 5178 5179 5180
};

/* l4_cfg -> usb_otg_hs */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_usb_otg_hs_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_usb_otg_hs_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* usb_otg_hs slave ports */
static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
	&omap44xx_l4_cfg__usb_otg_hs,
};

static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
	{ .role = "xclk", .clk = "usb_otg_hs_xclk" },
};

static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
	.name		= "usb_otg_hs",
	.class		= &omap44xx_usb_otg_hs_hwmod_class,
5181
	.clkdm_name	= "l3_init_clkdm",
B
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5182 5183 5184 5185 5186
	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
	.mpu_irqs	= omap44xx_usb_otg_hs_irqs,
	.main_clk	= "usb_otg_hs_ick",
	.prcm = {
		.omap4 = {
5187
			.clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
5188
			.context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
5189
			.modulemode   = MODULEMODE_HWCTRL,
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5190 5191 5192
		},
	},
	.opt_clks	= usb_otg_hs_opt_clks,
5193
	.opt_clks_cnt	= ARRAY_SIZE(usb_otg_hs_opt_clks),
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5194 5195 5196 5197 5198 5199 5200
	.slaves		= omap44xx_usb_otg_hs_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
	.masters	= omap44xx_usb_otg_hs_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211
/*
 * 'wd_timer' class
 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 * overflow condition
 */

static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
5212
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5213 5214
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
5215
	.sysc_fields	= &omap_hwmod_sysc_type1,
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};

5218 5219 5220
static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
	.name		= "wd_timer",
	.sysc		= &omap44xx_wd_timer_sysc,
5221
	.pre_shutdown	= &omap2_wd_timer_disable,
5222 5223 5224 5225 5226 5227
};

/* wd_timer2 */
static struct omap_hwmod omap44xx_wd_timer2_hwmod;
static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
	{ .irq = 80 + OMAP44XX_IRQ_GIC_START },
5228
	{ .irq = -1 }
5229 5230 5231
};

static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
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	{
5233 5234
		.pa_start	= 0x4a314000,
		.pa_end		= 0x4a31407f,
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		.flags		= ADDR_TYPE_RT
	},
5237
	{ }
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};

5240 5241 5242 5243 5244 5245
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
	.master		= &omap44xx_l4_wkup_hwmod,
	.slave		= &omap44xx_wd_timer2_hwmod,
	.clk		= "l4_wkup_clk_mux_ck",
	.addr		= omap44xx_wd_timer2_addrs,
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	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

5249 5250 5251
/* wd_timer2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
	&omap44xx_l4_wkup__wd_timer2,
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};

5254 5255 5256
static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
	.name		= "wd_timer2",
	.class		= &omap44xx_wd_timer_hwmod_class,
5257
	.clkdm_name	= "l4_wkup_clkdm",
5258 5259
	.mpu_irqs	= omap44xx_wd_timer2_irqs,
	.main_clk	= "wd_timer2_fck",
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	.prcm = {
		.omap4 = {
5262
			.clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
5263
			.context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
5264
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
5267 5268
	.slaves		= omap44xx_wd_timer2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_wd_timer2_slaves),
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	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

5272 5273 5274 5275
/* wd_timer3 */
static struct omap_hwmod omap44xx_wd_timer3_hwmod;
static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
	{ .irq = 36 + OMAP44XX_IRQ_GIC_START },
5276
	{ .irq = -1 }
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};

5279
static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
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	{
5281 5282
		.pa_start	= 0x40130000,
		.pa_end		= 0x4013007f,
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		.flags		= ADDR_TYPE_RT
	},
5285
	{ }
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};

5288 5289 5290 5291 5292 5293 5294
/* l4_abe -> wd_timer3 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_wd_timer3_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_wd_timer3_addrs,
	.user		= OCP_USER_MPU,
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};

5297 5298 5299 5300 5301 5302
static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
	{
		.pa_start	= 0x49030000,
		.pa_end		= 0x4903007f,
		.flags		= ADDR_TYPE_RT
	},
5303
	{ }
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};

5306 5307 5308 5309 5310 5311 5312
/* l4_abe -> wd_timer3 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_wd_timer3_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_wd_timer3_dma_addrs,
	.user		= OCP_USER_SDMA,
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};

5315 5316 5317 5318 5319 5320 5321 5322 5323
/* wd_timer3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
	&omap44xx_l4_abe__wd_timer3,
	&omap44xx_l4_abe__wd_timer3_dma,
};

static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
	.name		= "wd_timer3",
	.class		= &omap44xx_wd_timer_hwmod_class,
5324
	.clkdm_name	= "abe_clkdm",
5325 5326
	.mpu_irqs	= omap44xx_wd_timer3_irqs,
	.main_clk	= "wd_timer3_fck",
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	.prcm = {
		.omap4 = {
5329
			.clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
5330
			.context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
5331
			.modulemode   = MODULEMODE_SWCTRL,
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		},
	},
5334 5335
	.slaves		= omap44xx_wd_timer3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_wd_timer3_slaves),
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	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
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5339
static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5340

5341 5342
	/* dmm class */
	&omap44xx_dmm_hwmod,
5343

5344 5345
	/* emif_fw class */
	&omap44xx_emif_fw_hwmod,
5346

5347 5348 5349 5350 5351
	/* l3 class */
	&omap44xx_l3_instr_hwmod,
	&omap44xx_l3_main_1_hwmod,
	&omap44xx_l3_main_2_hwmod,
	&omap44xx_l3_main_3_hwmod,
5352

5353 5354 5355 5356 5357
	/* l4 class */
	&omap44xx_l4_abe_hwmod,
	&omap44xx_l4_cfg_hwmod,
	&omap44xx_l4_per_hwmod,
	&omap44xx_l4_wkup_hwmod,
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5358

5359 5360 5361
	/* mpu_bus class */
	&omap44xx_mpu_private_hwmod,

5362 5363 5364 5365 5366 5367 5368 5369 5370
	/* aess class */
/*	&omap44xx_aess_hwmod, */

	/* bandgap class */
	&omap44xx_bandgap_hwmod,

	/* counter class */
/*	&omap44xx_counter_32k_hwmod, */

5371 5372 5373
	/* dma class */
	&omap44xx_dma_system_hwmod,

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	/* dmic class */
	&omap44xx_dmic_hwmod,

5377 5378 5379 5380
	/* dsp class */
	&omap44xx_dsp_hwmod,
	&omap44xx_dsp_c0_hwmod,

5381 5382 5383 5384 5385 5386 5387 5388 5389
	/* dss class */
	&omap44xx_dss_hwmod,
	&omap44xx_dss_dispc_hwmod,
	&omap44xx_dss_dsi1_hwmod,
	&omap44xx_dss_dsi2_hwmod,
	&omap44xx_dss_hdmi_hwmod,
	&omap44xx_dss_rfbi_hwmod,
	&omap44xx_dss_venc_hwmod,

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	/* gpio class */
	&omap44xx_gpio1_hwmod,
	&omap44xx_gpio2_hwmod,
	&omap44xx_gpio3_hwmod,
	&omap44xx_gpio4_hwmod,
	&omap44xx_gpio5_hwmod,
	&omap44xx_gpio6_hwmod,

5398 5399 5400
	/* hsi class */
/*	&omap44xx_hsi_hwmod, */

5401 5402 5403 5404 5405 5406
	/* i2c class */
	&omap44xx_i2c1_hwmod,
	&omap44xx_i2c2_hwmod,
	&omap44xx_i2c3_hwmod,
	&omap44xx_i2c4_hwmod,

5407 5408 5409 5410 5411 5412 5413 5414
	/* ipu class */
	&omap44xx_ipu_hwmod,
	&omap44xx_ipu_c0_hwmod,
	&omap44xx_ipu_c1_hwmod,

	/* iss class */
/*	&omap44xx_iss_hwmod, */

5415 5416 5417 5418 5419
	/* iva class */
	&omap44xx_iva_hwmod,
	&omap44xx_iva_seq0_hwmod,
	&omap44xx_iva_seq1_hwmod,

5420
	/* kbd class */
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5421
	&omap44xx_kbd_hwmod,
5422

B
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5423 5424 5425
	/* mailbox class */
	&omap44xx_mailbox_hwmod,

B
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	/* mcbsp class */
	&omap44xx_mcbsp1_hwmod,
	&omap44xx_mcbsp2_hwmod,
	&omap44xx_mcbsp3_hwmod,
	&omap44xx_mcbsp4_hwmod,

5432 5433 5434
	/* mcpdm class */
/*	&omap44xx_mcpdm_hwmod, */

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5435 5436 5437 5438 5439 5440
	/* mcspi class */
	&omap44xx_mcspi1_hwmod,
	&omap44xx_mcspi2_hwmod,
	&omap44xx_mcspi3_hwmod,
	&omap44xx_mcspi4_hwmod,

5441
	/* mmc class */
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5442 5443 5444 5445 5446
	&omap44xx_mmc1_hwmod,
	&omap44xx_mmc2_hwmod,
	&omap44xx_mmc3_hwmod,
	&omap44xx_mmc4_hwmod,
	&omap44xx_mmc5_hwmod,
5447

5448 5449
	/* mpu class */
	&omap44xx_mpu_hwmod,
5450

5451 5452 5453 5454 5455
	/* smartreflex class */
	&omap44xx_smartreflex_core_hwmod,
	&omap44xx_smartreflex_iva_hwmod,
	&omap44xx_smartreflex_mpu_hwmod,

5456 5457 5458
	/* spinlock class */
	&omap44xx_spinlock_hwmod,

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5459 5460 5461 5462 5463 5464 5465 5466 5467 5468 5469 5470 5471
	/* timer class */
	&omap44xx_timer1_hwmod,
	&omap44xx_timer2_hwmod,
	&omap44xx_timer3_hwmod,
	&omap44xx_timer4_hwmod,
	&omap44xx_timer5_hwmod,
	&omap44xx_timer6_hwmod,
	&omap44xx_timer7_hwmod,
	&omap44xx_timer8_hwmod,
	&omap44xx_timer9_hwmod,
	&omap44xx_timer10_hwmod,
	&omap44xx_timer11_hwmod,

5472 5473 5474 5475 5476
	/* uart class */
	&omap44xx_uart1_hwmod,
	&omap44xx_uart2_hwmod,
	&omap44xx_uart3_hwmod,
	&omap44xx_uart4_hwmod,
5477

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5478 5479 5480
	/* usb_otg_hs class */
	&omap44xx_usb_otg_hs_hwmod,

5481 5482 5483 5484
	/* wd_timer class */
	&omap44xx_wd_timer2_hwmod,
	&omap44xx_wd_timer3_hwmod,

5485 5486 5487 5488 5489
	NULL,
};

int __init omap44xx_hwmod_init(void)
{
5490
	return omap_hwmod_register(omap44xx_hwmods);
5491 5492
}