omap_hwmod_44xx_data.c 134.2 KB
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/*
 * Hardware modules present on the OMAP44xx chips
 *
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 * Copyright (C) 2009-2011 Texas Instruments, Inc.
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 * Copyright (C) 2009-2010 Nokia Corporation
 *
 * Paul Walmsley
 * Benoit Cousson
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/io.h>

#include <plat/omap_hwmod.h>
#include <plat/cpu.h>
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#include <plat/i2c.h>
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#include <plat/gpio.h>
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#include <plat/dma.h>
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#include <plat/mcspi.h>
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#include <plat/mcbsp.h>
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#include <plat/mmc.h>
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#include <plat/i2c.h>
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#include "omap_hwmod_common_data.h"

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#include "cm1_44xx.h"
#include "cm2_44xx.h"
#include "prm44xx.h"
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#include "prm-regbits-44xx.h"
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#include "wd_timer.h"
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/* Base offset for all OMAP4 interrupts external to MPUSS */
#define OMAP44XX_IRQ_GIC_START	32

/* Base offset for all OMAP4 dma requests */
#define OMAP44XX_DMA_REQ_START  1

/* Backward references (IPs with Bus Master capability) */
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static struct omap_hwmod omap44xx_aess_hwmod;
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static struct omap_hwmod omap44xx_dma_system_hwmod;
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static struct omap_hwmod omap44xx_dmm_hwmod;
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static struct omap_hwmod omap44xx_dsp_hwmod;
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static struct omap_hwmod omap44xx_dss_hwmod;
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static struct omap_hwmod omap44xx_emif_fw_hwmod;
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static struct omap_hwmod omap44xx_hsi_hwmod;
static struct omap_hwmod omap44xx_ipu_hwmod;
static struct omap_hwmod omap44xx_iss_hwmod;
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static struct omap_hwmod omap44xx_iva_hwmod;
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static struct omap_hwmod omap44xx_l3_instr_hwmod;
static struct omap_hwmod omap44xx_l3_main_1_hwmod;
static struct omap_hwmod omap44xx_l3_main_2_hwmod;
static struct omap_hwmod omap44xx_l3_main_3_hwmod;
static struct omap_hwmod omap44xx_l4_abe_hwmod;
static struct omap_hwmod omap44xx_l4_cfg_hwmod;
static struct omap_hwmod omap44xx_l4_per_hwmod;
static struct omap_hwmod omap44xx_l4_wkup_hwmod;
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static struct omap_hwmod omap44xx_mmc1_hwmod;
static struct omap_hwmod omap44xx_mmc2_hwmod;
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static struct omap_hwmod omap44xx_mpu_hwmod;
static struct omap_hwmod omap44xx_mpu_private_hwmod;
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static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
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/*
 * Interconnects omap_hwmod structures
 * hwmods that compose the global OMAP interconnect
 */

/*
 * 'dmm' class
 * instance(s): dmm
 */
static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
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	.name	= "dmm",
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};

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/* dmm */
static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
	{ .irq = 113 + OMAP44XX_IRQ_GIC_START },
	{ .irq = -1 }
};

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/* l3_main_1 -> dmm */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
	.master		= &omap44xx_l3_main_1_hwmod,
	.slave		= &omap44xx_dmm_hwmod,
	.clk		= "l3_div_ck",
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	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
	{
		.pa_start	= 0x4e000000,
		.pa_end		= 0x4e0007ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* mpu -> dmm */
static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
	.master		= &omap44xx_mpu_hwmod,
	.slave		= &omap44xx_dmm_hwmod,
	.clk		= "l3_div_ck",
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	.addr		= omap44xx_dmm_addrs,
	.user		= OCP_USER_MPU,
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};

/* dmm slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
	&omap44xx_l3_main_1__dmm,
	&omap44xx_mpu__dmm,
};

static struct omap_hwmod omap44xx_dmm_hwmod = {
	.name		= "dmm",
	.class		= &omap44xx_dmm_hwmod_class,
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	.clkdm_name	= "l3_emif_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
		},
	},
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	.slaves		= omap44xx_dmm_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dmm_slaves),
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	.mpu_irqs	= omap44xx_dmm_irqs,
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	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'emif_fw' class
 * instance(s): emif_fw
 */
static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
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	.name	= "emif_fw",
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};

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/* emif_fw */
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/* dmm -> emif_fw */
static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
	.master		= &omap44xx_dmm_hwmod,
	.slave		= &omap44xx_emif_fw_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
	{
		.pa_start	= 0x4a20c000,
		.pa_end		= 0x4a20c0ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

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/* l4_cfg -> emif_fw */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_emif_fw_hwmod,
	.clk		= "l4_div_ck",
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	.addr		= omap44xx_emif_fw_addrs,
	.user		= OCP_USER_MPU,
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};

/* emif_fw slave ports */
static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
	&omap44xx_dmm__emif_fw,
	&omap44xx_l4_cfg__emif_fw,
};

static struct omap_hwmod omap44xx_emif_fw_hwmod = {
	.name		= "emif_fw",
	.class		= &omap44xx_emif_fw_hwmod_class,
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	.clkdm_name	= "l3_emif_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
		},
	},
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	.slaves		= omap44xx_emif_fw_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_emif_fw_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'l3' class
 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 */
static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
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	.name	= "l3",
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};

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/* l3_instr */
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/* iva -> l3_instr */
static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
	.master		= &omap44xx_iva_hwmod,
	.slave		= &omap44xx_l3_instr_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* l3_main_3 -> l3_instr */
static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
	.master		= &omap44xx_l3_main_3_hwmod,
	.slave		= &omap44xx_l3_instr_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_instr slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
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	&omap44xx_iva__l3_instr,
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	&omap44xx_l3_main_3__l3_instr,
};

static struct omap_hwmod omap44xx_l3_instr_hwmod = {
	.name		= "l3_instr",
	.class		= &omap44xx_l3_hwmod_class,
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	.clkdm_name	= "l3_instr_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
		},
	},
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	.slaves		= omap44xx_l3_instr_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l3_instr_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/* l3_main_1 */
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static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
	{ .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
	{ .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
	{ .irq = -1 }
};

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/* dsp -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
	.master		= &omap44xx_dsp_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* dss -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
	.master		= &omap44xx_dss_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* l3_main_2 -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_cfg -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l4_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* mmc1 -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
	.master		= &omap44xx_mmc1_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mmc2 -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
	.master		= &omap44xx_mmc2_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
	{
		.pa_start	= 0x44000000,
		.pa_end		= 0x44000fff,
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		.flags		= ADDR_TYPE_RT
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	},
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	{ }
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};

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/* mpu -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
	.master		= &omap44xx_mpu_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l3_div_ck",
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	.addr		= omap44xx_l3_main_1_addrs,
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	.user		= OCP_USER_MPU,
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};

/* l3_main_1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
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	&omap44xx_dsp__l3_main_1,
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	&omap44xx_dss__l3_main_1,
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	&omap44xx_l3_main_2__l3_main_1,
	&omap44xx_l4_cfg__l3_main_1,
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	&omap44xx_mmc1__l3_main_1,
	&omap44xx_mmc2__l3_main_1,
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	&omap44xx_mpu__l3_main_1,
};

static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
	.name		= "l3_main_1",
	.class		= &omap44xx_l3_hwmod_class,
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	.clkdm_name	= "l3_1_clkdm",
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	.mpu_irqs	= omap44xx_l3_main_1_irqs,
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
		},
	},
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	.slaves		= omap44xx_l3_main_1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l3_main_1_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/* l3_main_2 */
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/* dma_system -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
	.master		= &omap44xx_dma_system_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* hsi -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
	.master		= &omap44xx_hsi_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* ipu -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
	.master		= &omap44xx_ipu_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* iss -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
	.master		= &omap44xx_iss_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* iva -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
	.master		= &omap44xx_iva_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
	{
		.pa_start	= 0x44800000,
		.pa_end		= 0x44801fff,
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		.flags		= ADDR_TYPE_RT
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	},
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	{ }
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};

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/* l3_main_1 -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
	.master		= &omap44xx_l3_main_1_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
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	.addr		= omap44xx_l3_main_2_addrs,
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	.user		= OCP_USER_MPU,
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};

/* l4_cfg -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l4_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* usb_otg_hs -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
	.master		= &omap44xx_usb_otg_hs_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* l3_main_2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
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	&omap44xx_dma_system__l3_main_2,
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	&omap44xx_hsi__l3_main_2,
	&omap44xx_ipu__l3_main_2,
	&omap44xx_iss__l3_main_2,
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	&omap44xx_iva__l3_main_2,
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	&omap44xx_l3_main_1__l3_main_2,
	&omap44xx_l4_cfg__l3_main_2,
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	&omap44xx_usb_otg_hs__l3_main_2,
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};

static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
	.name		= "l3_main_2",
	.class		= &omap44xx_l3_hwmod_class,
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	.clkdm_name	= "l3_2_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
		},
	},
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	.slaves		= omap44xx_l3_main_2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l3_main_2_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/* l3_main_3 */
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static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
	{
		.pa_start	= 0x45000000,
		.pa_end		= 0x45000fff,
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		.flags		= ADDR_TYPE_RT
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	},
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	{ }
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};

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/* l3_main_1 -> l3_main_3 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
	.master		= &omap44xx_l3_main_1_hwmod,
	.slave		= &omap44xx_l3_main_3_hwmod,
	.clk		= "l3_div_ck",
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	.addr		= omap44xx_l3_main_3_addrs,
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	.user		= OCP_USER_MPU,
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};

/* l3_main_2 -> l3_main_3 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_l3_main_3_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_cfg -> l3_main_3 */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_l3_main_3_hwmod,
	.clk		= "l4_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
	&omap44xx_l3_main_1__l3_main_3,
	&omap44xx_l3_main_2__l3_main_3,
	&omap44xx_l4_cfg__l3_main_3,
};

static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
	.name		= "l3_main_3",
	.class		= &omap44xx_l3_hwmod_class,
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	.clkdm_name	= "l3_instr_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
		},
	},
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	.slaves		= omap44xx_l3_main_3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l3_main_3_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'l4' class
 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 */
static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
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	.name	= "l4",
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};

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/* l4_abe */
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/* aess -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
	.master		= &omap44xx_aess_hwmod,
	.slave		= &omap44xx_l4_abe_hwmod,
	.clk		= "ocp_abe_iclk",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* dsp -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
	.master		= &omap44xx_dsp_hwmod,
	.slave		= &omap44xx_l4_abe_hwmod,
	.clk		= "ocp_abe_iclk",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* l3_main_1 -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
	.master		= &omap44xx_l3_main_1_hwmod,
	.slave		= &omap44xx_l4_abe_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mpu -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
	.master		= &omap44xx_mpu_hwmod,
	.slave		= &omap44xx_l4_abe_hwmod,
	.clk		= "ocp_abe_iclk",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_abe slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
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	&omap44xx_aess__l4_abe,
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	&omap44xx_dsp__l4_abe,
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	&omap44xx_l3_main_1__l4_abe,
	&omap44xx_mpu__l4_abe,
};

static struct omap_hwmod omap44xx_l4_abe_hwmod = {
	.name		= "l4_abe",
	.class		= &omap44xx_l4_hwmod_class,
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	.clkdm_name	= "abe_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
		},
	},
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	.slaves		= omap44xx_l4_abe_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l4_abe_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/* l4_cfg */
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/* l3_main_1 -> l4_cfg */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
	.master		= &omap44xx_l3_main_1_hwmod,
	.slave		= &omap44xx_l4_cfg_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_cfg slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
	&omap44xx_l3_main_1__l4_cfg,
};

static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
	.name		= "l4_cfg",
	.class		= &omap44xx_l4_hwmod_class,
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	.clkdm_name	= "l4_cfg_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
		},
	},
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	.slaves		= omap44xx_l4_cfg_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l4_cfg_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/* l4_per */
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/* l3_main_2 -> l4_per */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_l4_per_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
	&omap44xx_l3_main_2__l4_per,
};

static struct omap_hwmod omap44xx_l4_per_hwmod = {
	.name		= "l4_per",
	.class		= &omap44xx_l4_hwmod_class,
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	.clkdm_name	= "l4_per_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
		},
	},
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	.slaves		= omap44xx_l4_per_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l4_per_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/* l4_wkup */
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/* l4_cfg -> l4_wkup */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_l4_wkup_hwmod,
	.clk		= "l4_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
	&omap44xx_l4_cfg__l4_wkup,
};

static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
	.name		= "l4_wkup",
	.class		= &omap44xx_l4_hwmod_class,
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	.clkdm_name	= "l4_wkup_clkdm",
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	.prcm = {
		.omap4 = {
			.clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
		},
	},
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	.slaves		= omap44xx_l4_wkup_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l4_wkup_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
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 * 'mpu_bus' class
 * instance(s): mpu_private
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 */
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static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
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	.name	= "mpu_bus",
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};
648

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/* mpu_private */
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/* mpu -> mpu_private */
static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
	.master		= &omap44xx_mpu_hwmod,
	.slave		= &omap44xx_mpu_private_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mpu_private slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
	&omap44xx_mpu__mpu_private,
};

static struct omap_hwmod omap44xx_mpu_private_hwmod = {
	.name		= "mpu_private",
	.class		= &omap44xx_mpu_bus_hwmod_class,
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	.clkdm_name	= "mpuss_clkdm",
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	.slaves		= omap44xx_mpu_private_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mpu_private_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * Modules omap_hwmod structures
 *
 * The following IPs are excluded for the moment because:
 * - They do not need an explicit SW control using omap_hwmod API.
 * - They still need to be validated with the driver
 *   properly adapted to omap_hwmod / omap_device
 *
 *  c2c
 *  c2c_target_fw
 *  cm_core
 *  cm_core_aon
 *  ctrl_module_core
 *  ctrl_module_pad_core
 *  ctrl_module_pad_wkup
 *  ctrl_module_wkup
 *  debugss
 *  efuse_ctrl_cust
 *  efuse_ctrl_std
 *  elm
 *  emif1
 *  emif2
 *  fdif
 *  gpmc
 *  gpu
 *  hdq1w
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 *  mcasp
 *  mpu_c0
 *  mpu_c1
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 *  ocmc_ram
 *  ocp2scp_usb_phy
 *  ocp_wp_noc
 *  prcm_mpu
 *  prm
 *  scrm
 *  sl2if
 *  slimbus1
 *  slimbus2
 *  usb_host_fs
 *  usb_host_hs
 *  usb_phy_cm
 *  usb_tll_hs
 *  usim
 */

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/*
 * 'aess' class
 * audio engine sub system
 */

static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
			   MSTANDBY_SMART_WKUP),
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	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
	.name	= "aess",
	.sysc	= &omap44xx_aess_sysc,
};

/* aess */
static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
	{ .irq = 99 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
	{ .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
	{ .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
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	{ .dma_req = -1 }
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};

/* aess master ports */
static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
	&omap44xx_aess__l4_abe,
};

static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
	{
		.pa_start	= 0x401f1000,
		.pa_end		= 0x401f13ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_abe -> aess */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_aess_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_aess_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
	{
		.pa_start	= 0x490f1000,
		.pa_end		= 0x490f13ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_abe -> aess (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_aess_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_aess_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* aess slave ports */
static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
	&omap44xx_l4_abe__aess,
	&omap44xx_l4_abe__aess_dma,
};

static struct omap_hwmod omap44xx_aess_hwmod = {
	.name		= "aess",
	.class		= &omap44xx_aess_hwmod_class,
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	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_aess_irqs,
	.sdma_reqs	= omap44xx_aess_sdma_reqs,
	.main_clk	= "aess_fck",
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	.prcm = {
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		.omap4 = {
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			.clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_aess_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_aess_slaves),
	.masters	= omap44xx_aess_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_aess_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'bandgap' class
 * bangap reference for ldo regulators
 */

static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
	.name	= "bandgap",
};

/* bandgap */
static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
	{ .role = "fclk", .clk = "bandgap_fclk" },
};

static struct omap_hwmod omap44xx_bandgap_hwmod = {
	.name		= "bandgap",
	.class		= &omap44xx_bandgap_hwmod_class,
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	.clkdm_name	= "l4_wkup_clkdm",
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	.prcm = {
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		.omap4 = {
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			.clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
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		},
	},
	.opt_clks	= bandgap_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(bandgap_opt_clks),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'counter' class
 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 */

static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0004,
	.sysc_flags	= SYSC_HAS_SIDLEMODE,
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
	.name	= "counter",
	.sysc	= &omap44xx_counter_sysc,
};

/* counter_32k */
static struct omap_hwmod omap44xx_counter_32k_hwmod;
static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
	{
		.pa_start	= 0x4a304000,
		.pa_end		= 0x4a30401f,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_wkup -> counter_32k */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
	.master		= &omap44xx_l4_wkup_hwmod,
	.slave		= &omap44xx_counter_32k_hwmod,
	.clk		= "l4_wkup_clk_mux_ck",
	.addr		= omap44xx_counter_32k_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* counter_32k slave ports */
static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
	&omap44xx_l4_wkup__counter_32k,
};

static struct omap_hwmod omap44xx_counter_32k_hwmod = {
	.name		= "counter_32k",
	.class		= &omap44xx_counter_hwmod_class,
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	.clkdm_name	= "l4_wkup_clkdm",
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	.flags		= HWMOD_SWSUP_SIDLE,
	.main_clk	= "sys_32k_ck",
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	.prcm = {
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		.omap4 = {
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			.clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_counter_32k_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_counter_32k_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'dma' class
 * dma controller for data exchange between memory to memory (i.e. internal or
 * external memory) and gp peripherals to memory or memory to gp peripherals
 */

static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x002c,
	.syss_offs	= 0x0028,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
	.name	= "dma",
	.sysc	= &omap44xx_dma_sysc,
};

/* dma dev_attr */
static struct omap_dma_dev_attr dma_dev_attr = {
	.dev_caps	= RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
			  IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
	.lch_count	= 32,
};

/* dma_system */
static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
	{ .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
	{ .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
	{ .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
	{ .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

/* dma_system master ports */
static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
	&omap44xx_dma_system__l3_main_2,
};

static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
	{
		.pa_start	= 0x4a056000,
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		.pa_end		= 0x4a056fff,
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		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_cfg -> dma_system */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_dma_system_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dma_system_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* dma_system slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
	&omap44xx_l4_cfg__dma_system,
};

static struct omap_hwmod omap44xx_dma_system_hwmod = {
	.name		= "dma_system",
	.class		= &omap44xx_dma_hwmod_class,
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	.clkdm_name	= "l3_dma_clkdm",
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	.mpu_irqs	= omap44xx_dma_system_irqs,
	.main_clk	= "l3_div_ck",
	.prcm = {
		.omap4 = {
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			.clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
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		},
	},
	.dev_attr	= &dma_dev_attr,
	.slaves		= omap44xx_dma_system_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dma_system_slaves),
	.masters	= omap44xx_dma_system_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_dma_system_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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Benoit Cousson 已提交
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/*
 * 'dmic' class
 * digital microphone controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
	.name	= "dmic",
	.sysc	= &omap44xx_dmic_sysc,
};

/* dmic */
static struct omap_hwmod omap44xx_dmic_hwmod;
static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
	{ .irq = 114 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
	{ .dma_req = 66 + OMAP44XX_DMA_REQ_START },
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	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
	{
		.pa_start	= 0x4012e000,
		.pa_end		= 0x4012e07f,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_abe -> dmic */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_dmic_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_dmic_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
	{
		.pa_start	= 0x4902e000,
		.pa_end		= 0x4902e07f,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_abe -> dmic (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_dmic_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_dmic_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* dmic slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
	&omap44xx_l4_abe__dmic,
	&omap44xx_l4_abe__dmic_dma,
};

static struct omap_hwmod omap44xx_dmic_hwmod = {
	.name		= "dmic",
	.class		= &omap44xx_dmic_hwmod_class,
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	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_dmic_irqs,
	.sdma_reqs	= omap44xx_dmic_sdma_reqs,
	.main_clk	= "dmic_fck",
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	.prcm = {
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		.omap4 = {
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			.clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_dmic_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dmic_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'dsp' class
 * dsp sub-system
 */

static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
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	.name	= "dsp",
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};

/* dsp */
static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
	{ .irq = 28 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
	{ .name = "mmu_cache", .rst_shift = 1 },
};

static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
	{ .name = "dsp", .rst_shift = 0 },
};

/* dsp -> iva */
static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
	.master		= &omap44xx_dsp_hwmod,
	.slave		= &omap44xx_iva_hwmod,
	.clk		= "dpll_iva_m5x2_ck",
};

/* dsp master ports */
static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
	&omap44xx_dsp__l3_main_1,
	&omap44xx_dsp__l4_abe,
	&omap44xx_dsp__iva,
};

/* l4_cfg -> dsp */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_dsp_hwmod,
	.clk		= "l4_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* dsp slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
	&omap44xx_l4_cfg__dsp,
};

/* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
	.name		= "dsp_c0",
	.class		= &omap44xx_dsp_hwmod_class,
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	.clkdm_name	= "tesla_clkdm",
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	.flags		= HWMOD_INIT_NO_RESET,
	.rst_lines	= omap44xx_dsp_c0_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_dsp_c0_resets),
	.prcm = {
		.omap4 = {
			.rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
		},
	},
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

static struct omap_hwmod omap44xx_dsp_hwmod = {
	.name		= "dsp",
	.class		= &omap44xx_dsp_hwmod_class,
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	.clkdm_name	= "tesla_clkdm",
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	.mpu_irqs	= omap44xx_dsp_irqs,
	.rst_lines	= omap44xx_dsp_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_dsp_resets),
	.main_clk	= "dsp_fck",
	.prcm = {
		.omap4 = {
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			.clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
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			.rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
		},
	},
	.slaves		= omap44xx_dsp_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dsp_slaves),
	.masters	= omap44xx_dsp_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_dsp_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'dss' class
 * display sub-system
 */

static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
	.rev_offs	= 0x0000,
	.syss_offs	= 0x0014,
	.sysc_flags	= SYSS_HAS_RESET_STATUS,
};

static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
	.name	= "dss",
	.sysc	= &omap44xx_dss_sysc,
};

/* dss */
/* dss master ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
	&omap44xx_dss__l3_main_1,
};

static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
	{
		.pa_start	= 0x58000000,
		.pa_end		= 0x5800007f,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l3_main_2 -> dss */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_hwmod,
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	.clk		= "dss_fck",
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	.addr		= omap44xx_dss_dma_addrs,
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
	{
		.pa_start	= 0x48040000,
		.pa_end		= 0x4804007f,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_per -> dss */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_addrs,
	.user		= OCP_USER_MPU,
};

/* dss slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
	&omap44xx_l3_main_2__dss,
	&omap44xx_l4_per__dss,
};

static struct omap_hwmod_opt_clk dss_opt_clks[] = {
	{ .role = "sys_clk", .clk = "dss_sys_clk" },
	{ .role = "tv_clk", .clk = "dss_tv_clk" },
	{ .role = "dss_clk", .clk = "dss_dss_clk" },
	{ .role = "video_clk", .clk = "dss_48mhz_clk" },
};

static struct omap_hwmod omap44xx_dss_hwmod = {
	.name		= "dss_core",
	.class		= &omap44xx_dss_hwmod_class,
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	.clkdm_name	= "l3_dss_clkdm",
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	.main_clk	= "dss_dss_clk",
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	.prcm = {
		.omap4 = {
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			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
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		},
	},
	.opt_clks	= dss_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_opt_clks),
	.slaves		= omap44xx_dss_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_slaves),
	.masters	= omap44xx_dss_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_dss_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'dispc' class
 * display controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
	.name	= "dispc",
	.sysc	= &omap44xx_dispc_sysc,
};

/* dss_dispc */
static struct omap_hwmod omap44xx_dss_dispc_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
	{ .irq = 25 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
	{ .dma_req = 5 + OMAP44XX_DMA_REQ_START },
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	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
	{
		.pa_start	= 0x58001000,
		.pa_end		= 0x58001fff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l3_main_2 -> dss_dispc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_dispc_hwmod,
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	.clk		= "dss_fck",
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	.addr		= omap44xx_dss_dispc_dma_addrs,
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
	{
		.pa_start	= 0x48041000,
		.pa_end		= 0x48041fff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_per -> dss_dispc */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_dispc_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_dispc_addrs,
	.user		= OCP_USER_MPU,
};

/* dss_dispc slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
	&omap44xx_l3_main_2__dss_dispc,
	&omap44xx_l4_per__dss_dispc,
};

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static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
	{ .role = "sys_clk", .clk = "dss_sys_clk" },
	{ .role = "tv_clk", .clk = "dss_tv_clk" },
	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
};

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static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
	.name		= "dss_dispc",
	.class		= &omap44xx_dispc_hwmod_class,
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	.clkdm_name	= "l3_dss_clkdm",
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	.mpu_irqs	= omap44xx_dss_dispc_irqs,
	.sdma_reqs	= omap44xx_dss_dispc_sdma_reqs,
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	.main_clk	= "dss_dss_clk",
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	.prcm = {
		.omap4 = {
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			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
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		},
	},
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	.opt_clks	= dss_dispc_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_dispc_opt_clks),
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	.slaves		= omap44xx_dss_dispc_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'dsi' class
 * display serial interface controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
	.name	= "dsi",
	.sysc	= &omap44xx_dsi_sysc,
};

/* dss_dsi1 */
static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
	{ .irq = 53 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
	{ .dma_req = 74 + OMAP44XX_DMA_REQ_START },
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	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
	{
		.pa_start	= 0x58004000,
		.pa_end		= 0x580041ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l3_main_2 -> dss_dsi1 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_dsi1_hwmod,
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	.clk		= "dss_fck",
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	.addr		= omap44xx_dss_dsi1_dma_addrs,
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
	{
		.pa_start	= 0x48044000,
		.pa_end		= 0x480441ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_per -> dss_dsi1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_dsi1_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_dsi1_addrs,
	.user		= OCP_USER_MPU,
};

/* dss_dsi1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
	&omap44xx_l3_main_2__dss_dsi1,
	&omap44xx_l4_per__dss_dsi1,
};

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static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
	{ .role = "sys_clk", .clk = "dss_sys_clk" },
};

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static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
	.name		= "dss_dsi1",
	.class		= &omap44xx_dsi_hwmod_class,
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	.clkdm_name	= "l3_dss_clkdm",
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	.mpu_irqs	= omap44xx_dss_dsi1_irqs,
	.sdma_reqs	= omap44xx_dss_dsi1_sdma_reqs,
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	.main_clk	= "dss_dss_clk",
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	.prcm = {
		.omap4 = {
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			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
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		},
	},
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	.opt_clks	= dss_dsi1_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi1_opt_clks),
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	.slaves		= omap44xx_dss_dsi1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* dss_dsi2 */
static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
	{ .irq = 84 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
	{ .dma_req = 83 + OMAP44XX_DMA_REQ_START },
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	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
	{
		.pa_start	= 0x58005000,
		.pa_end		= 0x580051ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l3_main_2 -> dss_dsi2 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_dsi2_hwmod,
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	.clk		= "dss_fck",
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	.addr		= omap44xx_dss_dsi2_dma_addrs,
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
	{
		.pa_start	= 0x48045000,
		.pa_end		= 0x480451ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_per -> dss_dsi2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_dsi2_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_dsi2_addrs,
	.user		= OCP_USER_MPU,
};

/* dss_dsi2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
	&omap44xx_l3_main_2__dss_dsi2,
	&omap44xx_l4_per__dss_dsi2,
};

1518 1519 1520 1521
static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
	{ .role = "sys_clk", .clk = "dss_sys_clk" },
};

1522 1523 1524
static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
	.name		= "dss_dsi2",
	.class		= &omap44xx_dsi_hwmod_class,
1525
	.clkdm_name	= "l3_dss_clkdm",
1526 1527
	.mpu_irqs	= omap44xx_dss_dsi2_irqs,
	.sdma_reqs	= omap44xx_dss_dsi2_sdma_reqs,
1528
	.main_clk	= "dss_dss_clk",
1529 1530
	.prcm = {
		.omap4 = {
1531
			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1532 1533
		},
	},
1534 1535
	.opt_clks	= dss_dsi2_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi2_opt_clks),
1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564
	.slaves		= omap44xx_dss_dsi2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'hdmi' class
 * hdmi controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
	.name	= "hdmi",
	.sysc	= &omap44xx_hdmi_sysc,
};

/* dss_hdmi */
static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
	{ .irq = 101 + OMAP44XX_IRQ_GIC_START },
1565
	{ .irq = -1 }
1566 1567 1568 1569
};

static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
	{ .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1570
	{ .dma_req = -1 }
1571 1572 1573 1574 1575 1576 1577 1578
};

static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
	{
		.pa_start	= 0x58006000,
		.pa_end		= 0x58006fff,
		.flags		= ADDR_TYPE_RT
	},
1579
	{ }
1580 1581 1582 1583 1584 1585
};

/* l3_main_2 -> dss_hdmi */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_hdmi_hwmod,
1586
	.clk		= "dss_fck",
1587 1588 1589 1590 1591 1592 1593 1594 1595 1596
	.addr		= omap44xx_dss_hdmi_dma_addrs,
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
	{
		.pa_start	= 0x48046000,
		.pa_end		= 0x48046fff,
		.flags		= ADDR_TYPE_RT
	},
1597
	{ }
1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614
};

/* l4_per -> dss_hdmi */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_hdmi_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_hdmi_addrs,
	.user		= OCP_USER_MPU,
};

/* dss_hdmi slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
	&omap44xx_l3_main_2__dss_hdmi,
	&omap44xx_l4_per__dss_hdmi,
};

1615 1616 1617 1618
static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
	{ .role = "sys_clk", .clk = "dss_sys_clk" },
};

1619 1620 1621
static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
	.name		= "dss_hdmi",
	.class		= &omap44xx_hdmi_hwmod_class,
1622
	.clkdm_name	= "l3_dss_clkdm",
1623 1624
	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
1625
	.main_clk	= "dss_dss_clk",
1626 1627
	.prcm = {
		.omap4 = {
1628
			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1629 1630
		},
	},
1631 1632
	.opt_clks	= dss_hdmi_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_hdmi_opt_clks),
1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661
	.slaves		= omap44xx_dss_hdmi_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'rfbi' class
 * remote frame buffer interface
 */

static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
	.name	= "rfbi",
	.sysc	= &omap44xx_rfbi_sysc,
};

/* dss_rfbi */
static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
	{ .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1662
	{ .dma_req = -1 }
1663 1664 1665 1666 1667 1668 1669 1670
};

static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
	{
		.pa_start	= 0x58002000,
		.pa_end		= 0x580020ff,
		.flags		= ADDR_TYPE_RT
	},
1671
	{ }
1672 1673 1674 1675 1676 1677
};

/* l3_main_2 -> dss_rfbi */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_rfbi_hwmod,
1678
	.clk		= "dss_fck",
1679 1680 1681 1682 1683 1684 1685 1686 1687 1688
	.addr		= omap44xx_dss_rfbi_dma_addrs,
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
	{
		.pa_start	= 0x48042000,
		.pa_end		= 0x480420ff,
		.flags		= ADDR_TYPE_RT
	},
1689
	{ }
1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706
};

/* l4_per -> dss_rfbi */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_rfbi_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_rfbi_addrs,
	.user		= OCP_USER_MPU,
};

/* dss_rfbi slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
	&omap44xx_l3_main_2__dss_rfbi,
	&omap44xx_l4_per__dss_rfbi,
};

1707 1708 1709 1710
static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
	{ .role = "ick", .clk = "dss_fck" },
};

1711 1712 1713
static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
	.name		= "dss_rfbi",
	.class		= &omap44xx_rfbi_hwmod_class,
1714
	.clkdm_name	= "l3_dss_clkdm",
1715
	.sdma_reqs	= omap44xx_dss_rfbi_sdma_reqs,
1716
	.main_clk	= "dss_dss_clk",
1717 1718
	.prcm = {
		.omap4 = {
1719
			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1720 1721
		},
	},
1722 1723
	.opt_clks	= dss_rfbi_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745
	.slaves		= omap44xx_dss_rfbi_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'venc' class
 * video encoder
 */

static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
	.name	= "venc",
};

/* dss_venc */
static struct omap_hwmod omap44xx_dss_venc_hwmod;
static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
	{
		.pa_start	= 0x58003000,
		.pa_end		= 0x580030ff,
		.flags		= ADDR_TYPE_RT
	},
1746
	{ }
1747 1748 1749 1750 1751 1752
};

/* l3_main_2 -> dss_venc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_venc_hwmod,
1753
	.clk		= "dss_fck",
1754 1755 1756 1757 1758 1759 1760 1761 1762 1763
	.addr		= omap44xx_dss_venc_dma_addrs,
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
	{
		.pa_start	= 0x48043000,
		.pa_end		= 0x480430ff,
		.flags		= ADDR_TYPE_RT
	},
1764
	{ }
1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784
};

/* l4_per -> dss_venc */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_venc_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_venc_addrs,
	.user		= OCP_USER_MPU,
};

/* dss_venc slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
	&omap44xx_l3_main_2__dss_venc,
	&omap44xx_l4_per__dss_venc,
};

static struct omap_hwmod omap44xx_dss_venc_hwmod = {
	.name		= "dss_venc",
	.class		= &omap44xx_venc_hwmod_class,
1785
	.clkdm_name	= "l3_dss_clkdm",
1786
	.main_clk	= "dss_dss_clk",
1787 1788
	.prcm = {
		.omap4 = {
1789
			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1790 1791 1792 1793 1794 1795 1796
		},
	},
	.slaves		= omap44xx_dss_venc_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_venc_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

1797 1798 1799 1800 1801 1802 1803
/*
 * 'gpio' class
 * general purpose io module
 */

static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
	.rev_offs	= 0x0000,
1804
	.sysc_offs	= 0x0010,
1805
	.syss_offs	= 0x0114,
1806 1807 1808
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
1809 1810
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
1811 1812 1813
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

1814
static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1815 1816 1817
	.name	= "gpio",
	.sysc	= &omap44xx_gpio_sysc,
	.rev	= 2,
1818 1819
};

1820 1821
/* gpio dev_attr */
static struct omap_gpio_dev_attr gpio_dev_attr = {
1822 1823
	.bank_width	= 32,
	.dbck_flag	= true,
1824 1825
};

1826 1827 1828 1829
/* gpio1 */
static struct omap_hwmod omap44xx_gpio1_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
	{ .irq = 29 + OMAP44XX_IRQ_GIC_START },
1830
	{ .irq = -1 }
1831 1832
};

1833
static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1834
	{
1835 1836
		.pa_start	= 0x4a310000,
		.pa_end		= 0x4a3101ff,
1837 1838
		.flags		= ADDR_TYPE_RT
	},
1839
	{ }
1840 1841
};

1842 1843 1844 1845
/* l4_wkup -> gpio1 */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
	.master		= &omap44xx_l4_wkup_hwmod,
	.slave		= &omap44xx_gpio1_hwmod,
1846
	.clk		= "l4_wkup_clk_mux_ck",
1847
	.addr		= omap44xx_gpio1_addrs,
1848 1849 1850
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

1851 1852 1853
/* gpio1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
	&omap44xx_l4_wkup__gpio1,
1854 1855
};

1856
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1857
	{ .role = "dbclk", .clk = "gpio1_dbclk" },
1858 1859 1860 1861 1862
};

static struct omap_hwmod omap44xx_gpio1_hwmod = {
	.name		= "gpio1",
	.class		= &omap44xx_gpio_hwmod_class,
1863
	.clkdm_name	= "l4_wkup_clkdm",
1864 1865
	.mpu_irqs	= omap44xx_gpio1_irqs,
	.main_clk	= "gpio1_ick",
1866 1867
	.prcm = {
		.omap4 = {
1868
			.clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1869 1870
		},
	},
1871 1872 1873 1874 1875
	.opt_clks	= gpio1_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio1_slaves),
1876 1877 1878
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

1879 1880 1881 1882
/* gpio2 */
static struct omap_hwmod omap44xx_gpio2_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
	{ .irq = 30 + OMAP44XX_IRQ_GIC_START },
1883
	{ .irq = -1 }
1884 1885
};

1886
static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1887
	{
1888 1889
		.pa_start	= 0x48055000,
		.pa_end		= 0x480551ff,
1890 1891
		.flags		= ADDR_TYPE_RT
	},
1892
	{ }
1893 1894
};

1895 1896
/* l4_per -> gpio2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1897
	.master		= &omap44xx_l4_per_hwmod,
1898
	.slave		= &omap44xx_gpio2_hwmod,
1899
	.clk		= "l4_div_ck",
1900
	.addr		= omap44xx_gpio2_addrs,
1901 1902 1903
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

1904 1905 1906
/* gpio2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
	&omap44xx_l4_per__gpio2,
1907 1908
};

1909
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1910
	{ .role = "dbclk", .clk = "gpio2_dbclk" },
1911 1912 1913 1914 1915
};

static struct omap_hwmod omap44xx_gpio2_hwmod = {
	.name		= "gpio2",
	.class		= &omap44xx_gpio_hwmod_class,
1916
	.clkdm_name	= "l4_per_clkdm",
1917
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1918 1919
	.mpu_irqs	= omap44xx_gpio2_irqs,
	.main_clk	= "gpio2_ick",
1920 1921
	.prcm = {
		.omap4 = {
1922
			.clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1923 1924
		},
	},
1925 1926 1927 1928 1929
	.opt_clks	= gpio2_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio2_slaves),
1930 1931 1932
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

1933 1934 1935 1936
/* gpio3 */
static struct omap_hwmod omap44xx_gpio3_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
	{ .irq = 31 + OMAP44XX_IRQ_GIC_START },
1937
	{ .irq = -1 }
1938 1939
};

1940
static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1941
	{
1942 1943
		.pa_start	= 0x48057000,
		.pa_end		= 0x480571ff,
1944 1945
		.flags		= ADDR_TYPE_RT
	},
1946
	{ }
1947 1948
};

1949 1950
/* l4_per -> gpio3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1951
	.master		= &omap44xx_l4_per_hwmod,
1952
	.slave		= &omap44xx_gpio3_hwmod,
1953
	.clk		= "l4_div_ck",
1954
	.addr		= omap44xx_gpio3_addrs,
1955 1956 1957
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

1958 1959 1960
/* gpio3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
	&omap44xx_l4_per__gpio3,
1961 1962
};

1963
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1964
	{ .role = "dbclk", .clk = "gpio3_dbclk" },
1965 1966 1967 1968 1969
};

static struct omap_hwmod omap44xx_gpio3_hwmod = {
	.name		= "gpio3",
	.class		= &omap44xx_gpio_hwmod_class,
1970
	.clkdm_name	= "l4_per_clkdm",
1971
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1972 1973
	.mpu_irqs	= omap44xx_gpio3_irqs,
	.main_clk	= "gpio3_ick",
1974 1975
	.prcm = {
		.omap4 = {
1976
			.clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1977 1978
		},
	},
1979 1980 1981 1982 1983
	.opt_clks	= gpio3_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio3_slaves),
1984 1985 1986
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

1987 1988 1989 1990
/* gpio4 */
static struct omap_hwmod omap44xx_gpio4_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
	{ .irq = 32 + OMAP44XX_IRQ_GIC_START },
1991
	{ .irq = -1 }
1992 1993
};

1994
static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1995
	{
1996 1997
		.pa_start	= 0x48059000,
		.pa_end		= 0x480591ff,
1998 1999
		.flags		= ADDR_TYPE_RT
	},
2000
	{ }
2001 2002
};

2003 2004
/* l4_per -> gpio4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2005
	.master		= &omap44xx_l4_per_hwmod,
2006
	.slave		= &omap44xx_gpio4_hwmod,
2007
	.clk		= "l4_div_ck",
2008
	.addr		= omap44xx_gpio4_addrs,
2009 2010 2011
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

2012 2013 2014
/* gpio4 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
	&omap44xx_l4_per__gpio4,
2015 2016
};

2017
static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2018
	{ .role = "dbclk", .clk = "gpio4_dbclk" },
2019 2020 2021 2022 2023
};

static struct omap_hwmod omap44xx_gpio4_hwmod = {
	.name		= "gpio4",
	.class		= &omap44xx_gpio_hwmod_class,
2024
	.clkdm_name	= "l4_per_clkdm",
2025
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2026 2027
	.mpu_irqs	= omap44xx_gpio4_irqs,
	.main_clk	= "gpio4_ick",
2028 2029
	.prcm = {
		.omap4 = {
2030
			.clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2031 2032
		},
	},
2033 2034 2035 2036 2037
	.opt_clks	= gpio4_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio4_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio4_slaves),
2038 2039 2040
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

2041 2042 2043 2044
/* gpio5 */
static struct omap_hwmod omap44xx_gpio5_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
	{ .irq = 33 + OMAP44XX_IRQ_GIC_START },
2045
	{ .irq = -1 }
2046 2047
};

2048 2049 2050 2051 2052 2053
static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
	{
		.pa_start	= 0x4805b000,
		.pa_end		= 0x4805b1ff,
		.flags		= ADDR_TYPE_RT
	},
2054
	{ }
2055 2056
};

2057 2058 2059 2060
/* l4_per -> gpio5 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_gpio5_hwmod,
2061
	.clk		= "l4_div_ck",
2062 2063
	.addr		= omap44xx_gpio5_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2064 2065
};

2066 2067 2068
/* gpio5 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
	&omap44xx_l4_per__gpio5,
2069 2070
};

2071
static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2072
	{ .role = "dbclk", .clk = "gpio5_dbclk" },
2073 2074
};

2075 2076 2077
static struct omap_hwmod omap44xx_gpio5_hwmod = {
	.name		= "gpio5",
	.class		= &omap44xx_gpio_hwmod_class,
2078
	.clkdm_name	= "l4_per_clkdm",
2079
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2080 2081
	.mpu_irqs	= omap44xx_gpio5_irqs,
	.main_clk	= "gpio5_ick",
2082 2083
	.prcm = {
		.omap4 = {
2084
			.clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2085 2086
		},
	},
2087 2088 2089 2090 2091
	.opt_clks	= gpio5_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio5_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio5_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio5_slaves),
2092 2093 2094
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

2095 2096 2097 2098
/* gpio6 */
static struct omap_hwmod omap44xx_gpio6_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
	{ .irq = 34 + OMAP44XX_IRQ_GIC_START },
2099
	{ .irq = -1 }
2100 2101
};

2102
static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2103
	{
2104 2105
		.pa_start	= 0x4805d000,
		.pa_end		= 0x4805d1ff,
2106 2107
		.flags		= ADDR_TYPE_RT
	},
2108
	{ }
2109 2110
};

2111 2112 2113 2114
/* l4_per -> gpio6 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_gpio6_hwmod,
2115
	.clk		= "l4_div_ck",
2116 2117
	.addr		= omap44xx_gpio6_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2118 2119
};

2120 2121 2122
/* gpio6 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
	&omap44xx_l4_per__gpio6,
2123 2124
};

2125
static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2126
	{ .role = "dbclk", .clk = "gpio6_dbclk" },
2127 2128
};

2129 2130 2131
static struct omap_hwmod omap44xx_gpio6_hwmod = {
	.name		= "gpio6",
	.class		= &omap44xx_gpio_hwmod_class,
2132
	.clkdm_name	= "l4_per_clkdm",
2133
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2134 2135 2136 2137
	.mpu_irqs	= omap44xx_gpio6_irqs,
	.main_clk	= "gpio6_ick",
	.prcm = {
		.omap4 = {
2138
			.clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2139
		},
2140
	},
2141 2142 2143 2144 2145 2146
	.opt_clks	= gpio6_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio6_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio6_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio6_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2147 2148
};

2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163
/*
 * 'hsi' class
 * mipi high-speed synchronous serial interface (multichannel and full-duplex
 * serial if)
 */

static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
			   SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2164
			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
	.name	= "hsi",
	.sysc	= &omap44xx_hsi_sysc,
};

/* hsi */
static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
	{ .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
	{ .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
	{ .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2178
	{ .irq = -1 }
2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191
};

/* hsi master ports */
static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
	&omap44xx_hsi__l3_main_2,
};

static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
	{
		.pa_start	= 0x4a058000,
		.pa_end		= 0x4a05bfff,
		.flags		= ADDR_TYPE_RT
	},
2192
	{ }
2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211
};

/* l4_cfg -> hsi */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_hsi_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_hsi_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* hsi slave ports */
static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
	&omap44xx_l4_cfg__hsi,
};

static struct omap_hwmod omap44xx_hsi_hwmod = {
	.name		= "hsi",
	.class		= &omap44xx_hsi_hwmod_class,
2212
	.clkdm_name	= "l3_init_clkdm",
2213 2214
	.mpu_irqs	= omap44xx_hsi_irqs,
	.main_clk	= "hsi_fck",
2215
	.prcm = {
2216
		.omap4 = {
2217
			.clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2218 2219 2220 2221 2222 2223 2224 2225 2226
		},
	},
	.slaves		= omap44xx_hsi_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_hsi_slaves),
	.masters	= omap44xx_hsi_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_hsi_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

2227 2228 2229 2230
/*
 * 'i2c' class
 * multimaster high-speed i2c controller
 */
2231

2232 2233 2234 2235 2236
static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0090,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2237
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2238 2239
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
2240
	.sysc_fields	= &omap_hwmod_sysc_type1,
2241 2242
};

2243
static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2244 2245
	.name	= "i2c",
	.sysc	= &omap44xx_i2c_sysc,
2246
	.rev	= OMAP_I2C_IP_VERSION_2,
2247
	.reset	= &omap_i2c_reset,
2248 2249
};

2250 2251 2252 2253
static struct omap_i2c_dev_attr i2c_dev_attr = {
	.flags	= OMAP_I2C_FLAG_BUS_SHIFT_NONE,
};

2254 2255 2256 2257
/* i2c1 */
static struct omap_hwmod omap44xx_i2c1_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
	{ .irq = 56 + OMAP44XX_IRQ_GIC_START },
2258
	{ .irq = -1 }
2259 2260
};

2261 2262 2263
static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2264
	{ .dma_req = -1 }
2265 2266
};

2267
static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2268
	{
2269 2270
		.pa_start	= 0x48070000,
		.pa_end		= 0x480700ff,
2271 2272
		.flags		= ADDR_TYPE_RT
	},
2273
	{ }
2274 2275
};

2276 2277 2278 2279 2280 2281
/* l4_per -> i2c1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_i2c1_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_i2c1_addrs,
2282 2283 2284
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

2285 2286 2287
/* i2c1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
	&omap44xx_l4_per__i2c1,
2288 2289
};

2290 2291 2292
static struct omap_hwmod omap44xx_i2c1_hwmod = {
	.name		= "i2c1",
	.class		= &omap44xx_i2c_hwmod_class,
2293
	.clkdm_name	= "l4_per_clkdm",
2294
	.flags		= HWMOD_16BIT_REG,
2295 2296 2297
	.mpu_irqs	= omap44xx_i2c1_irqs,
	.sdma_reqs	= omap44xx_i2c1_sdma_reqs,
	.main_clk	= "i2c1_fck",
2298 2299
	.prcm = {
		.omap4 = {
2300
			.clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2301 2302
		},
	},
2303 2304
	.slaves		= omap44xx_i2c1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c1_slaves),
2305
	.dev_attr	= &i2c_dev_attr,
2306 2307 2308
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

2309 2310 2311 2312
/* i2c2 */
static struct omap_hwmod omap44xx_i2c2_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
	{ .irq = 57 + OMAP44XX_IRQ_GIC_START },
2313
	{ .irq = -1 }
2314 2315
};

2316 2317 2318
static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2319
	{ .dma_req = -1 }
2320 2321 2322
};

static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2323
	{
2324 2325
		.pa_start	= 0x48072000,
		.pa_end		= 0x480720ff,
2326 2327
		.flags		= ADDR_TYPE_RT
	},
2328
	{ }
2329 2330
};

2331 2332
/* l4_per -> i2c2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2333
	.master		= &omap44xx_l4_per_hwmod,
2334
	.slave		= &omap44xx_i2c2_hwmod,
2335
	.clk		= "l4_div_ck",
2336
	.addr		= omap44xx_i2c2_addrs,
2337 2338 2339
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

2340 2341 2342
/* i2c2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
	&omap44xx_l4_per__i2c2,
2343 2344
};

2345 2346 2347
static struct omap_hwmod omap44xx_i2c2_hwmod = {
	.name		= "i2c2",
	.class		= &omap44xx_i2c_hwmod_class,
2348
	.clkdm_name	= "l4_per_clkdm",
2349
	.flags		= HWMOD_16BIT_REG,
2350 2351 2352
	.mpu_irqs	= omap44xx_i2c2_irqs,
	.sdma_reqs	= omap44xx_i2c2_sdma_reqs,
	.main_clk	= "i2c2_fck",
2353 2354
	.prcm = {
		.omap4 = {
2355
			.clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2356 2357
		},
	},
2358 2359
	.slaves		= omap44xx_i2c2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c2_slaves),
2360
	.dev_attr	= &i2c_dev_attr,
2361 2362 2363
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

2364 2365 2366 2367
/* i2c3 */
static struct omap_hwmod omap44xx_i2c3_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
	{ .irq = 61 + OMAP44XX_IRQ_GIC_START },
2368
	{ .irq = -1 }
2369 2370
};

2371 2372 2373
static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2374
	{ .dma_req = -1 }
2375 2376
};

2377
static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2378
	{
2379 2380
		.pa_start	= 0x48060000,
		.pa_end		= 0x480600ff,
2381 2382
		.flags		= ADDR_TYPE_RT
	},
2383
	{ }
2384 2385
};

2386 2387
/* l4_per -> i2c3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2388
	.master		= &omap44xx_l4_per_hwmod,
2389
	.slave		= &omap44xx_i2c3_hwmod,
2390
	.clk		= "l4_div_ck",
2391
	.addr		= omap44xx_i2c3_addrs,
2392 2393 2394
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

2395 2396 2397
/* i2c3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
	&omap44xx_l4_per__i2c3,
2398 2399
};

2400 2401 2402
static struct omap_hwmod omap44xx_i2c3_hwmod = {
	.name		= "i2c3",
	.class		= &omap44xx_i2c_hwmod_class,
2403
	.clkdm_name	= "l4_per_clkdm",
2404
	.flags		= HWMOD_16BIT_REG,
2405 2406 2407
	.mpu_irqs	= omap44xx_i2c3_irqs,
	.sdma_reqs	= omap44xx_i2c3_sdma_reqs,
	.main_clk	= "i2c3_fck",
2408 2409
	.prcm = {
		.omap4 = {
2410
			.clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2411 2412
		},
	},
2413 2414
	.slaves		= omap44xx_i2c3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c3_slaves),
2415
	.dev_attr	= &i2c_dev_attr,
2416 2417 2418
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

2419 2420 2421 2422
/* i2c4 */
static struct omap_hwmod omap44xx_i2c4_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
	{ .irq = 62 + OMAP44XX_IRQ_GIC_START },
2423
	{ .irq = -1 }
2424 2425
};

2426 2427 2428
static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2429
	{ .dma_req = -1 }
2430 2431
};

2432
static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2433
	{
2434 2435
		.pa_start	= 0x48350000,
		.pa_end		= 0x483500ff,
2436 2437
		.flags		= ADDR_TYPE_RT
	},
2438
	{ }
2439 2440
};

2441 2442 2443 2444 2445 2446 2447
/* l4_per -> i2c4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_i2c4_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_i2c4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2448 2449
};

2450 2451 2452
/* i2c4 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
	&omap44xx_l4_per__i2c4,
2453 2454
};

2455 2456 2457
static struct omap_hwmod omap44xx_i2c4_hwmod = {
	.name		= "i2c4",
	.class		= &omap44xx_i2c_hwmod_class,
2458
	.clkdm_name	= "l4_per_clkdm",
2459
	.flags		= HWMOD_16BIT_REG,
2460 2461 2462
	.mpu_irqs	= omap44xx_i2c4_irqs,
	.sdma_reqs	= omap44xx_i2c4_sdma_reqs,
	.main_clk	= "i2c4_fck",
2463 2464
	.prcm = {
		.omap4 = {
2465
			.clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2466 2467
		},
	},
2468 2469
	.slaves		= omap44xx_i2c4_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c4_slaves),
2470
	.dev_attr	= &i2c_dev_attr,
2471 2472 2473
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485
/*
 * 'ipu' class
 * imaging processor unit
 */

static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
	.name	= "ipu",
};

/* ipu */
static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
	{ .irq = 100 + OMAP44XX_IRQ_GIC_START },
2486
	{ .irq = -1 }
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};

static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
	{ .name = "cpu0", .rst_shift = 0 },
};

static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
	{ .name = "cpu1", .rst_shift = 1 },
};

static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
	{ .name = "mmu_cache", .rst_shift = 2 },
};

/* ipu master ports */
static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
	&omap44xx_ipu__l3_main_2,
};

/* l3_main_2 -> ipu */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_ipu_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* ipu slave ports */
static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
	&omap44xx_l3_main_2__ipu,
};

/* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
	.name		= "ipu_c0",
	.class		= &omap44xx_ipu_hwmod_class,
2523
	.clkdm_name	= "ducati_clkdm",
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	.flags		= HWMOD_INIT_NO_RESET,
	.rst_lines	= omap44xx_ipu_c0_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_ipu_c0_resets),
2527
	.prcm = {
2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538
		.omap4 = {
			.rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
		},
	},
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
	.name		= "ipu_c1",
	.class		= &omap44xx_ipu_hwmod_class,
2539
	.clkdm_name	= "ducati_clkdm",
2540 2541 2542
	.flags		= HWMOD_INIT_NO_RESET,
	.rst_lines	= omap44xx_ipu_c1_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_ipu_c1_resets),
2543
	.prcm = {
2544 2545 2546 2547 2548 2549 2550 2551 2552 2553
		.omap4 = {
			.rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
		},
	},
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

static struct omap_hwmod omap44xx_ipu_hwmod = {
	.name		= "ipu",
	.class		= &omap44xx_ipu_hwmod_class,
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	.clkdm_name	= "ducati_clkdm",
2555 2556 2557 2558
	.mpu_irqs	= omap44xx_ipu_irqs,
	.rst_lines	= omap44xx_ipu_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_ipu_resets),
	.main_clk	= "ipu_fck",
2559
	.prcm = {
2560
		.omap4 = {
2561
			.clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583
			.rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
		},
	},
	.slaves		= omap44xx_ipu_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_ipu_slaves),
	.masters	= omap44xx_ipu_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_ipu_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'iss' class
 * external images sensor pixel data processor
 */

static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
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			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
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	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
	.name	= "iss",
	.sysc	= &omap44xx_iss_sysc,
};

/* iss */
static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
	{ .irq = 24 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
	{ .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
	{ .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
	{ .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
	{ .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
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	{ .dma_req = -1 }
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};

/* iss master ports */
static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
	&omap44xx_iss__l3_main_2,
};

static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
	{
		.pa_start	= 0x52000000,
		.pa_end		= 0x520000ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l3_main_2 -> iss */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_iss_hwmod,
	.clk		= "l3_div_ck",
	.addr		= omap44xx_iss_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* iss slave ports */
static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
	&omap44xx_l3_main_2__iss,
};

static struct omap_hwmod_opt_clk iss_opt_clks[] = {
	{ .role = "ctrlclk", .clk = "iss_ctrlclk" },
};

static struct omap_hwmod omap44xx_iss_hwmod = {
	.name		= "iss",
	.class		= &omap44xx_iss_hwmod_class,
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	.clkdm_name	= "iss_clkdm",
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	.mpu_irqs	= omap44xx_iss_irqs,
	.sdma_reqs	= omap44xx_iss_sdma_reqs,
	.main_clk	= "iss_fck",
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	.prcm = {
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		.omap4 = {
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			.clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
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		},
	},
	.opt_clks	= iss_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(iss_opt_clks),
	.slaves		= omap44xx_iss_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_iss_slaves),
	.masters	= omap44xx_iss_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_iss_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'iva' class
 * multi-standard video encoder/decoder hardware accelerator
 */

static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
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	.name	= "iva",
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};

/* iva */
static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
	{ .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
	{ .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
	{ .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
	{ .name = "logic", .rst_shift = 2 },
};

static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
	{ .name = "seq0", .rst_shift = 0 },
};

static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
	{ .name = "seq1", .rst_shift = 1 },
};

/* iva master ports */
static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
	&omap44xx_iva__l3_main_2,
	&omap44xx_iva__l3_instr,
};

static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
	{
		.pa_start	= 0x5a000000,
		.pa_end		= 0x5a07ffff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l3_main_2 -> iva */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_iva_hwmod,
	.clk		= "l3_div_ck",
	.addr		= omap44xx_iva_addrs,
	.user		= OCP_USER_MPU,
};

/* iva slave ports */
static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
	&omap44xx_dsp__iva,
	&omap44xx_l3_main_2__iva,
};

/* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
	.name		= "iva_seq0",
	.class		= &omap44xx_iva_hwmod_class,
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	.clkdm_name	= "ivahd_clkdm",
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	.flags		= HWMOD_INIT_NO_RESET,
	.rst_lines	= omap44xx_iva_seq0_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_iva_seq0_resets),
	.prcm = {
		.omap4 = {
			.rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
		},
	},
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
	.name		= "iva_seq1",
	.class		= &omap44xx_iva_hwmod_class,
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	.clkdm_name	= "ivahd_clkdm",
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	.flags		= HWMOD_INIT_NO_RESET,
	.rst_lines	= omap44xx_iva_seq1_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_iva_seq1_resets),
	.prcm = {
		.omap4 = {
			.rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
		},
	},
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

static struct omap_hwmod omap44xx_iva_hwmod = {
	.name		= "iva",
	.class		= &omap44xx_iva_hwmod_class,
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	.clkdm_name	= "ivahd_clkdm",
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	.mpu_irqs	= omap44xx_iva_irqs,
	.rst_lines	= omap44xx_iva_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_iva_resets),
	.main_clk	= "iva_fck",
	.prcm = {
		.omap4 = {
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			.clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
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			.rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
		},
	},
	.slaves		= omap44xx_iva_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_iva_slaves),
	.masters	= omap44xx_iva_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_iva_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'kbd' class
 * keyboard controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
	.name	= "kbd",
	.sysc	= &omap44xx_kbd_sysc,
};

/* kbd */
static struct omap_hwmod omap44xx_kbd_hwmod;
static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
	{ .irq = 120 + OMAP44XX_IRQ_GIC_START },
2798
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
	{
		.pa_start	= 0x4a31c000,
		.pa_end		= 0x4a31c07f,
		.flags		= ADDR_TYPE_RT
	},
2807
	{ }
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};

/* l4_wkup -> kbd */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
	.master		= &omap44xx_l4_wkup_hwmod,
	.slave		= &omap44xx_kbd_hwmod,
	.clk		= "l4_wkup_clk_mux_ck",
	.addr		= omap44xx_kbd_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* kbd slave ports */
static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
	&omap44xx_l4_wkup__kbd,
};

static struct omap_hwmod omap44xx_kbd_hwmod = {
	.name		= "kbd",
	.class		= &omap44xx_kbd_hwmod_class,
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	.clkdm_name	= "l4_wkup_clkdm",
2828 2829
	.mpu_irqs	= omap44xx_kbd_irqs,
	.main_clk	= "kbd_fck",
2830
	.prcm = {
2831
		.omap4 = {
2832
			.clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_kbd_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_kbd_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'mailbox' class
 * mailbox module allowing communication between the on-chip processors using a
 * queued mailbox-interrupt mechanism.
 */

static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
	.name	= "mailbox",
	.sysc	= &omap44xx_mailbox_sysc,
};

/* mailbox */
static struct omap_hwmod omap44xx_mailbox_hwmod;
static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
	{ .irq = 26 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
	{
		.pa_start	= 0x4a0f4000,
		.pa_end		= 0x4a0f41ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_cfg -> mailbox */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_mailbox_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mailbox_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mailbox slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
	&omap44xx_l4_cfg__mailbox,
};

static struct omap_hwmod omap44xx_mailbox_hwmod = {
	.name		= "mailbox",
	.class		= &omap44xx_mailbox_hwmod_class,
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	.clkdm_name	= "l4_cfg_clkdm",
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	.mpu_irqs	= omap44xx_mailbox_irqs,
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	.prcm = {
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		.omap4 = {
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			.clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_mailbox_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mailbox_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'mcbsp' class
 * multi channel buffered serial port controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
	.sysc_offs	= 0x008c,
	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
	.name	= "mcbsp",
	.sysc	= &omap44xx_mcbsp_sysc,
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	.rev	= MCBSP_CONFIG_TYPE4,
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};

/* mcbsp1 */
static struct omap_hwmod omap44xx_mcbsp1_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
	{ .irq = 17 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
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	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
	{
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		.name		= "mpu",
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		.pa_start	= 0x40122000,
		.pa_end		= 0x401220ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_abe -> mcbsp1 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_mcbsp1_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_mcbsp1_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
	{
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		.name		= "dma",
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		.pa_start	= 0x49022000,
		.pa_end		= 0x490220ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_abe -> mcbsp1 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_mcbsp1_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_mcbsp1_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* mcbsp1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
	&omap44xx_l4_abe__mcbsp1,
	&omap44xx_l4_abe__mcbsp1_dma,
};

static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
	.name		= "mcbsp1",
	.class		= &omap44xx_mcbsp_hwmod_class,
2984
	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_mcbsp1_irqs,
	.sdma_reqs	= omap44xx_mcbsp1_sdma_reqs,
	.main_clk	= "mcbsp1_fck",
	.prcm = {
		.omap4 = {
2990
			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_mcbsp1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcbsp1_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mcbsp2 */
static struct omap_hwmod omap44xx_mcbsp2_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
	{ .irq = 22 + OMAP44XX_IRQ_GIC_START },
3002
	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
3008
	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
	{
3013
		.name		= "mpu",
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		.pa_start	= 0x40124000,
		.pa_end		= 0x401240ff,
		.flags		= ADDR_TYPE_RT
	},
3018
	{ }
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};

/* l4_abe -> mcbsp2 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_mcbsp2_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_mcbsp2_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
	{
3032
		.name		= "dma",
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		.pa_start	= 0x49024000,
		.pa_end		= 0x490240ff,
		.flags		= ADDR_TYPE_RT
	},
3037
	{ }
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};

/* l4_abe -> mcbsp2 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_mcbsp2_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_mcbsp2_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* mcbsp2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
	&omap44xx_l4_abe__mcbsp2,
	&omap44xx_l4_abe__mcbsp2_dma,
};

static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
	.name		= "mcbsp2",
	.class		= &omap44xx_mcbsp_hwmod_class,
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	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_mcbsp2_irqs,
	.sdma_reqs	= omap44xx_mcbsp2_sdma_reqs,
	.main_clk	= "mcbsp2_fck",
	.prcm = {
		.omap4 = {
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			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_mcbsp2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcbsp2_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mcbsp3 */
static struct omap_hwmod omap44xx_mcbsp3_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
	{ .irq = 23 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
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	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
	{
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		.name		= "mpu",
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		.pa_start	= 0x40126000,
		.pa_end		= 0x401260ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_abe -> mcbsp3 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_mcbsp3_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_mcbsp3_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
	{
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		.name		= "dma",
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		.pa_start	= 0x49026000,
		.pa_end		= 0x490260ff,
		.flags		= ADDR_TYPE_RT
	},
3111
	{ }
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};

/* l4_abe -> mcbsp3 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_mcbsp3_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_mcbsp3_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* mcbsp3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
	&omap44xx_l4_abe__mcbsp3,
	&omap44xx_l4_abe__mcbsp3_dma,
};

static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
	.name		= "mcbsp3",
	.class		= &omap44xx_mcbsp_hwmod_class,
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	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_mcbsp3_irqs,
	.sdma_reqs	= omap44xx_mcbsp3_sdma_reqs,
	.main_clk	= "mcbsp3_fck",
	.prcm = {
		.omap4 = {
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			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_mcbsp3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcbsp3_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mcbsp4 */
static struct omap_hwmod omap44xx_mcbsp4_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
	{ .irq = 16 + OMAP44XX_IRQ_GIC_START },
3150
	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3156
	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
	{
		.pa_start	= 0x48096000,
		.pa_end		= 0x480960ff,
		.flags		= ADDR_TYPE_RT
	},
3165
	{ }
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};

/* l4_per -> mcbsp4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mcbsp4_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mcbsp4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mcbsp4 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
	&omap44xx_l4_per__mcbsp4,
};

static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
	.name		= "mcbsp4",
	.class		= &omap44xx_mcbsp_hwmod_class,
3185
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_mcbsp4_irqs,
	.sdma_reqs	= omap44xx_mcbsp4_sdma_reqs,
	.main_clk	= "mcbsp4_fck",
	.prcm = {
		.omap4 = {
3191
			.clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_mcbsp4_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcbsp4_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223
/*
 * 'mcpdm' class
 * multi channel pdm controller (proprietary interface with phoenix power
 * ic)
 */

static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
	.name	= "mcpdm",
	.sysc	= &omap44xx_mcpdm_sysc,
};

/* mcpdm */
static struct omap_hwmod omap44xx_mcpdm_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
	{ .irq = 112 + OMAP44XX_IRQ_GIC_START },
3224
	{ .irq = -1 }
3225 3226 3227 3228 3229
};

static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
	{ .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
	{ .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3230
	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
	{
		.pa_start	= 0x40132000,
		.pa_end		= 0x4013207f,
		.flags		= ADDR_TYPE_RT
	},
3239
	{ }
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};

/* l4_abe -> mcpdm */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_mcpdm_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_mcpdm_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
	{
		.pa_start	= 0x49032000,
		.pa_end		= 0x4903207f,
		.flags		= ADDR_TYPE_RT
	},
3257
	{ }
3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277
};

/* l4_abe -> mcpdm (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_mcpdm_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_mcpdm_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* mcpdm slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
	&omap44xx_l4_abe__mcpdm,
	&omap44xx_l4_abe__mcpdm_dma,
};

static struct omap_hwmod omap44xx_mcpdm_hwmod = {
	.name		= "mcpdm",
	.class		= &omap44xx_mcpdm_hwmod_class,
3278
	.clkdm_name	= "abe_clkdm",
3279 3280 3281
	.mpu_irqs	= omap44xx_mcpdm_irqs,
	.sdma_reqs	= omap44xx_mcpdm_sdma_reqs,
	.main_clk	= "mcpdm_fck",
3282
	.prcm = {
3283
		.omap4 = {
3284
			.clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3285 3286 3287 3288 3289 3290 3291
		},
	},
	.slaves		= omap44xx_mcpdm_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcpdm_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'mcspi' class
 * multichannel serial port interface (mcspi) / master/slave synchronous serial
 * bus
 */

static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
	.name	= "mcspi",
	.sysc	= &omap44xx_mcspi_sysc,
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	.rev	= OMAP4_MCSPI_REV,
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};

/* mcspi1 */
static struct omap_hwmod omap44xx_mcspi1_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
	{ .irq = 65 + OMAP44XX_IRQ_GIC_START },
3318
	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
	{ .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
	{ .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
	{ .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
	{ .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
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	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
	{
		.pa_start	= 0x48098000,
		.pa_end		= 0x480981ff,
		.flags		= ADDR_TYPE_RT
	},
3339
	{ }
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};

/* l4_per -> mcspi1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mcspi1_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mcspi1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mcspi1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
	&omap44xx_l4_per__mcspi1,
};

3356 3357 3358 3359 3360
/* mcspi1 dev_attr */
static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
	.num_chipselect	= 4,
};

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static struct omap_hwmod omap44xx_mcspi1_hwmod = {
	.name		= "mcspi1",
	.class		= &omap44xx_mcspi_hwmod_class,
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	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_mcspi1_irqs,
	.sdma_reqs	= omap44xx_mcspi1_sdma_reqs,
	.main_clk	= "mcspi1_fck",
	.prcm = {
		.omap4 = {
3370
			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
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		},
	},
3373
	.dev_attr	= &mcspi1_dev_attr,
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	.slaves		= omap44xx_mcspi1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi1_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mcspi2 */
static struct omap_hwmod omap44xx_mcspi2_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
	{ .irq = 66 + OMAP44XX_IRQ_GIC_START },
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	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
	{ .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
	{ .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
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	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
	{
		.pa_start	= 0x4809a000,
		.pa_end		= 0x4809a1ff,
		.flags		= ADDR_TYPE_RT
	},
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	{ }
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};

/* l4_per -> mcspi2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mcspi2_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mcspi2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mcspi2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
	&omap44xx_l4_per__mcspi2,
};

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/* mcspi2 dev_attr */
static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
	.num_chipselect	= 2,
};

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static struct omap_hwmod omap44xx_mcspi2_hwmod = {
	.name		= "mcspi2",
	.class		= &omap44xx_mcspi_hwmod_class,
3425
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_mcspi2_irqs,
	.sdma_reqs	= omap44xx_mcspi2_sdma_reqs,
	.main_clk	= "mcspi2_fck",
	.prcm = {
		.omap4 = {
3431
			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
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		},
	},
3434
	.dev_attr	= &mcspi2_dev_attr,
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	.slaves		= omap44xx_mcspi2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi2_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mcspi3 */
static struct omap_hwmod omap44xx_mcspi3_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
	{ .irq = 91 + OMAP44XX_IRQ_GIC_START },
3444
	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
	{ .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
	{ .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3452
	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
	{
		.pa_start	= 0x480b8000,
		.pa_end		= 0x480b81ff,
		.flags		= ADDR_TYPE_RT
	},
3461
	{ }
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};

/* l4_per -> mcspi3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mcspi3_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mcspi3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mcspi3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
	&omap44xx_l4_per__mcspi3,
};

3478 3479 3480 3481 3482
/* mcspi3 dev_attr */
static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
	.num_chipselect	= 2,
};

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static struct omap_hwmod omap44xx_mcspi3_hwmod = {
	.name		= "mcspi3",
	.class		= &omap44xx_mcspi_hwmod_class,
3486
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_mcspi3_irqs,
	.sdma_reqs	= omap44xx_mcspi3_sdma_reqs,
	.main_clk	= "mcspi3_fck",
	.prcm = {
		.omap4 = {
3492
			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
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		},
	},
3495
	.dev_attr	= &mcspi3_dev_attr,
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	.slaves		= omap44xx_mcspi3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi3_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mcspi4 */
static struct omap_hwmod omap44xx_mcspi4_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
	{ .irq = 48 + OMAP44XX_IRQ_GIC_START },
3505
	{ .irq = -1 }
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};

static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
	{ .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3511
	{ .dma_req = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
	{
		.pa_start	= 0x480ba000,
		.pa_end		= 0x480ba1ff,
		.flags		= ADDR_TYPE_RT
	},
3520
	{ }
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};

/* l4_per -> mcspi4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mcspi4_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mcspi4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mcspi4 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
	&omap44xx_l4_per__mcspi4,
};

3537 3538 3539 3540 3541
/* mcspi4 dev_attr */
static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
	.num_chipselect	= 1,
};

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static struct omap_hwmod omap44xx_mcspi4_hwmod = {
	.name		= "mcspi4",
	.class		= &omap44xx_mcspi_hwmod_class,
3545
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_mcspi4_irqs,
	.sdma_reqs	= omap44xx_mcspi4_sdma_reqs,
	.main_clk	= "mcspi4_fck",
	.prcm = {
		.omap4 = {
3551
			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
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		},
	},
3554
	.dev_attr	= &mcspi4_dev_attr,
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	.slaves		= omap44xx_mcspi4_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi4_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572
/*
 * 'mmc' class
 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
			   SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3573
			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
	.name	= "mmc",
	.sysc	= &omap44xx_mmc_sysc,
};

/* mmc1 */
static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
	{ .irq = 83 + OMAP44XX_IRQ_GIC_START },
3585
	{ .irq = -1 }
3586 3587 3588 3589 3590
};

static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3591
	{ .dma_req = -1 }
3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604
};

/* mmc1 master ports */
static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
	&omap44xx_mmc1__l3_main_1,
};

static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
	{
		.pa_start	= 0x4809c000,
		.pa_end		= 0x4809c3ff,
		.flags		= ADDR_TYPE_RT
	},
3605
	{ }
3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621
};

/* l4_per -> mmc1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mmc1_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mmc1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mmc1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
	&omap44xx_l4_per__mmc1,
};

3622 3623 3624 3625 3626
/* mmc1 dev_attr */
static struct omap_mmc_dev_attr mmc1_dev_attr = {
	.flags	= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
};

3627 3628 3629
static struct omap_hwmod omap44xx_mmc1_hwmod = {
	.name		= "mmc1",
	.class		= &omap44xx_mmc_hwmod_class,
3630
	.clkdm_name	= "l3_init_clkdm",
3631 3632 3633
	.mpu_irqs	= omap44xx_mmc1_irqs,
	.sdma_reqs	= omap44xx_mmc1_sdma_reqs,
	.main_clk	= "mmc1_fck",
3634
	.prcm = {
3635
		.omap4 = {
3636
			.clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3637 3638
		},
	},
3639
	.dev_attr	= &mmc1_dev_attr,
3640 3641 3642 3643 3644 3645 3646 3647 3648 3649
	.slaves		= omap44xx_mmc1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mmc1_slaves),
	.masters	= omap44xx_mmc1_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_mmc1_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mmc2 */
static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
	{ .irq = 86 + OMAP44XX_IRQ_GIC_START },
3650
	{ .irq = -1 }
3651 3652 3653 3654 3655
};

static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3656
	{ .dma_req = -1 }
3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669
};

/* mmc2 master ports */
static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
	&omap44xx_mmc2__l3_main_1,
};

static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
	{
		.pa_start	= 0x480b4000,
		.pa_end		= 0x480b43ff,
		.flags		= ADDR_TYPE_RT
	},
3670
	{ }
3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689
};

/* l4_per -> mmc2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mmc2_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mmc2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mmc2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
	&omap44xx_l4_per__mmc2,
};

static struct omap_hwmod omap44xx_mmc2_hwmod = {
	.name		= "mmc2",
	.class		= &omap44xx_mmc_hwmod_class,
3690
	.clkdm_name	= "l3_init_clkdm",
3691 3692 3693
	.mpu_irqs	= omap44xx_mmc2_irqs,
	.sdma_reqs	= omap44xx_mmc2_sdma_reqs,
	.main_clk	= "mmc2_fck",
3694
	.prcm = {
3695
		.omap4 = {
3696
			.clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709
		},
	},
	.slaves		= omap44xx_mmc2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mmc2_slaves),
	.masters	= omap44xx_mmc2_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_mmc2_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mmc3 */
static struct omap_hwmod omap44xx_mmc3_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
	{ .irq = 94 + OMAP44XX_IRQ_GIC_START },
3710
	{ .irq = -1 }
3711 3712 3713 3714 3715
};

static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3716
	{ .dma_req = -1 }
3717 3718 3719 3720 3721 3722 3723 3724
};

static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
	{
		.pa_start	= 0x480ad000,
		.pa_end		= 0x480ad3ff,
		.flags		= ADDR_TYPE_RT
	},
3725
	{ }
3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744
};

/* l4_per -> mmc3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mmc3_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mmc3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mmc3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
	&omap44xx_l4_per__mmc3,
};

static struct omap_hwmod omap44xx_mmc3_hwmod = {
	.name		= "mmc3",
	.class		= &omap44xx_mmc_hwmod_class,
3745
	.clkdm_name	= "l4_per_clkdm",
3746 3747 3748
	.mpu_irqs	= omap44xx_mmc3_irqs,
	.sdma_reqs	= omap44xx_mmc3_sdma_reqs,
	.main_clk	= "mmc3_fck",
3749
	.prcm = {
3750
		.omap4 = {
3751
			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762
		},
	},
	.slaves		= omap44xx_mmc3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mmc3_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mmc4 */
static struct omap_hwmod omap44xx_mmc4_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
	{ .irq = 96 + OMAP44XX_IRQ_GIC_START },
3763
	{ .irq = -1 }
3764 3765 3766 3767 3768
};

static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3769
	{ .dma_req = -1 }
3770 3771 3772 3773 3774 3775 3776 3777
};

static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
	{
		.pa_start	= 0x480d1000,
		.pa_end		= 0x480d13ff,
		.flags		= ADDR_TYPE_RT
	},
3778
	{ }
3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797
};

/* l4_per -> mmc4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mmc4_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mmc4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mmc4 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
	&omap44xx_l4_per__mmc4,
};

static struct omap_hwmod omap44xx_mmc4_hwmod = {
	.name		= "mmc4",
	.class		= &omap44xx_mmc_hwmod_class,
3798
	.clkdm_name	= "l4_per_clkdm",
3799
	.mpu_irqs	= omap44xx_mmc4_irqs,
3800

3801 3802
	.sdma_reqs	= omap44xx_mmc4_sdma_reqs,
	.main_clk	= "mmc4_fck",
3803
	.prcm = {
3804
		.omap4 = {
3805
			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816
		},
	},
	.slaves		= omap44xx_mmc4_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mmc4_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* mmc5 */
static struct omap_hwmod omap44xx_mmc5_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
	{ .irq = 59 + OMAP44XX_IRQ_GIC_START },
3817
	{ .irq = -1 }
3818 3819 3820 3821 3822
};

static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3823
	{ .dma_req = -1 }
3824 3825 3826 3827 3828 3829 3830 3831
};

static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
	{
		.pa_start	= 0x480d5000,
		.pa_end		= 0x480d53ff,
		.flags		= ADDR_TYPE_RT
	},
3832
	{ }
3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851
};

/* l4_per -> mmc5 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_mmc5_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_mmc5_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mmc5 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
	&omap44xx_l4_per__mmc5,
};

static struct omap_hwmod omap44xx_mmc5_hwmod = {
	.name		= "mmc5",
	.class		= &omap44xx_mmc_hwmod_class,
3852
	.clkdm_name	= "l4_per_clkdm",
3853 3854 3855
	.mpu_irqs	= omap44xx_mmc5_irqs,
	.sdma_reqs	= omap44xx_mmc5_sdma_reqs,
	.main_clk	= "mmc5_fck",
3856
	.prcm = {
3857
		.omap4 = {
3858
			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3859 3860 3861 3862 3863 3864 3865
		},
	},
	.slaves		= omap44xx_mmc5_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mmc5_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

3866 3867 3868 3869 3870 3871
/*
 * 'mpu' class
 * mpu sub-system
 */

static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3872
	.name	= "mpu",
3873 3874
};

3875 3876 3877 3878 3879
/* mpu */
static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
	{ .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
	{ .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
	{ .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3880
	{ .irq = -1 }
3881 3882
};

3883 3884 3885 3886 3887 3888 3889 3890 3891 3892
/* mpu master ports */
static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
	&omap44xx_mpu__l3_main_1,
	&omap44xx_mpu__l4_abe,
	&omap44xx_mpu__dmm,
};

static struct omap_hwmod omap44xx_mpu_hwmod = {
	.name		= "mpu",
	.class		= &omap44xx_mpu_hwmod_class,
3893
	.clkdm_name	= "mpuss_clkdm",
3894
	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3895 3896
	.mpu_irqs	= omap44xx_mpu_irqs,
	.main_clk	= "dpll_mpu_m2_ck",
3897 3898
	.prcm = {
		.omap4 = {
3899
			.clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
3900 3901
		},
	},
3902 3903
	.masters	= omap44xx_mpu_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_mpu_masters),
3904 3905 3906
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927
/*
 * 'smartreflex' class
 * smartreflex module (monitor silicon performance and outputs a measure of
 * performance error)
 */

/* The IP is not compliant to type1 / type2 scheme */
static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
	.sidle_shift	= 24,
	.enwkup_shift	= 26,
};

static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
	.sysc_offs	= 0x0038,
	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type_smartreflex,
};

static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3928 3929 3930
	.name	= "smartreflex",
	.sysc	= &omap44xx_smartreflex_sysc,
	.rev	= 2,
3931 3932 3933 3934 3935 3936
};

/* smartreflex_core */
static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
	{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
3937
	{ .irq = -1 }
3938 3939 3940 3941 3942 3943 3944 3945
};

static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
	{
		.pa_start	= 0x4a0dd000,
		.pa_end		= 0x4a0dd03f,
		.flags		= ADDR_TYPE_RT
	},
3946
	{ }
3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965
};

/* l4_cfg -> smartreflex_core */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_smartreflex_core_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_smartreflex_core_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* smartreflex_core slave ports */
static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
	&omap44xx_l4_cfg__smartreflex_core,
};

static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
	.name		= "smartreflex_core",
	.class		= &omap44xx_smartreflex_hwmod_class,
3966
	.clkdm_name	= "l4_ao_clkdm",
3967
	.mpu_irqs	= omap44xx_smartreflex_core_irqs,
3968

3969 3970 3971 3972
	.main_clk	= "smartreflex_core_fck",
	.vdd_name	= "core",
	.prcm = {
		.omap4 = {
3973
			.clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984
		},
	},
	.slaves		= omap44xx_smartreflex_core_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* smartreflex_iva */
static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
	{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
3985
	{ .irq = -1 }
3986 3987 3988 3989 3990 3991 3992 3993
};

static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
	{
		.pa_start	= 0x4a0db000,
		.pa_end		= 0x4a0db03f,
		.flags		= ADDR_TYPE_RT
	},
3994
	{ }
3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013
};

/* l4_cfg -> smartreflex_iva */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_smartreflex_iva_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_smartreflex_iva_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* smartreflex_iva slave ports */
static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
	&omap44xx_l4_cfg__smartreflex_iva,
};

static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
	.name		= "smartreflex_iva",
	.class		= &omap44xx_smartreflex_hwmod_class,
4014
	.clkdm_name	= "l4_ao_clkdm",
4015 4016 4017 4018 4019
	.mpu_irqs	= omap44xx_smartreflex_iva_irqs,
	.main_clk	= "smartreflex_iva_fck",
	.vdd_name	= "iva",
	.prcm = {
		.omap4 = {
4020
			.clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031
		},
	},
	.slaves		= omap44xx_smartreflex_iva_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* smartreflex_mpu */
static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
	{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
4032
	{ .irq = -1 }
4033 4034 4035 4036 4037 4038 4039 4040
};

static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
	{
		.pa_start	= 0x4a0d9000,
		.pa_end		= 0x4a0d903f,
		.flags		= ADDR_TYPE_RT
	},
4041
	{ }
4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060
};

/* l4_cfg -> smartreflex_mpu */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_smartreflex_mpu_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_smartreflex_mpu_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* smartreflex_mpu slave ports */
static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
	&omap44xx_l4_cfg__smartreflex_mpu,
};

static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
	.name		= "smartreflex_mpu",
	.class		= &omap44xx_smartreflex_hwmod_class,
4061
	.clkdm_name	= "l4_ao_clkdm",
4062 4063 4064 4065 4066
	.mpu_irqs	= omap44xx_smartreflex_mpu_irqs,
	.main_clk	= "smartreflex_mpu_fck",
	.vdd_name	= "mpu",
	.prcm = {
		.omap4 = {
4067
			.clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
4068 4069 4070 4071 4072 4073 4074
		},
	},
	.slaves		= omap44xx_smartreflex_mpu_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105
/*
 * 'spinlock' class
 * spinlock provides hardware assistance for synchronizing the processes
 * running on multiple processors
 */

static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
	.name	= "spinlock",
	.sysc	= &omap44xx_spinlock_sysc,
};

/* spinlock */
static struct omap_hwmod omap44xx_spinlock_hwmod;
static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
	{
		.pa_start	= 0x4a0f6000,
		.pa_end		= 0x4a0f6fff,
		.flags		= ADDR_TYPE_RT
	},
4106
	{ }
4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125
};

/* l4_cfg -> spinlock */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_spinlock_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_spinlock_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* spinlock slave ports */
static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
	&omap44xx_l4_cfg__spinlock,
};

static struct omap_hwmod omap44xx_spinlock_hwmod = {
	.name		= "spinlock",
	.class		= &omap44xx_spinlock_hwmod_class,
4126
	.clkdm_name	= "l4_cfg_clkdm",
4127 4128
	.prcm = {
		.omap4 = {
4129
			.clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
4130 4131 4132 4133 4134 4135 4136
		},
	},
	.slaves		= omap44xx_spinlock_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_spinlock_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'timer' class
 * general purpose timer module with accurate 1ms tick
 * This class contains several variants: ['timer_1ms', 'timer']
 */

static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
	.name	= "timer",
	.sysc	= &omap44xx_timer_1ms_sysc,
};

static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
	.name	= "timer",
	.sysc	= &omap44xx_timer_sysc,
};

/* timer1 */
static struct omap_hwmod omap44xx_timer1_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
	{ .irq = 37 + OMAP44XX_IRQ_GIC_START },
4179
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
	{
		.pa_start	= 0x4a318000,
		.pa_end		= 0x4a31807f,
		.flags		= ADDR_TYPE_RT
	},
4188
	{ }
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};

/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
	.master		= &omap44xx_l4_wkup_hwmod,
	.slave		= &omap44xx_timer1_hwmod,
	.clk		= "l4_wkup_clk_mux_ck",
	.addr		= omap44xx_timer1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* timer1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
	&omap44xx_l4_wkup__timer1,
};

static struct omap_hwmod omap44xx_timer1_hwmod = {
	.name		= "timer1",
	.class		= &omap44xx_timer_1ms_hwmod_class,
4208
	.clkdm_name	= "l4_wkup_clkdm",
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	.mpu_irqs	= omap44xx_timer1_irqs,
	.main_clk	= "timer1_fck",
	.prcm = {
		.omap4 = {
4213
			.clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_timer1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer1_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer2 */
static struct omap_hwmod omap44xx_timer2_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
	{ .irq = 38 + OMAP44XX_IRQ_GIC_START },
4225
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
	{
		.pa_start	= 0x48032000,
		.pa_end		= 0x4803207f,
		.flags		= ADDR_TYPE_RT
	},
4234
	{ }
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};

/* l4_per -> timer2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_timer2_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_timer2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* timer2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
	&omap44xx_l4_per__timer2,
};

static struct omap_hwmod omap44xx_timer2_hwmod = {
	.name		= "timer2",
	.class		= &omap44xx_timer_1ms_hwmod_class,
4254
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_timer2_irqs,
	.main_clk	= "timer2_fck",
	.prcm = {
		.omap4 = {
4259
			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_timer2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer2_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer3 */
static struct omap_hwmod omap44xx_timer3_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
	{ .irq = 39 + OMAP44XX_IRQ_GIC_START },
4271
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
	{
		.pa_start	= 0x48034000,
		.pa_end		= 0x4803407f,
		.flags		= ADDR_TYPE_RT
	},
4280
	{ }
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};

/* l4_per -> timer3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_timer3_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_timer3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* timer3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
	&omap44xx_l4_per__timer3,
};

static struct omap_hwmod omap44xx_timer3_hwmod = {
	.name		= "timer3",
	.class		= &omap44xx_timer_hwmod_class,
4300
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_timer3_irqs,
	.main_clk	= "timer3_fck",
	.prcm = {
		.omap4 = {
4305
			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_timer3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer3_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer4 */
static struct omap_hwmod omap44xx_timer4_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
	{ .irq = 40 + OMAP44XX_IRQ_GIC_START },
4317
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
	{
		.pa_start	= 0x48036000,
		.pa_end		= 0x4803607f,
		.flags		= ADDR_TYPE_RT
	},
4326
	{ }
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};

/* l4_per -> timer4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_timer4_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_timer4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* timer4 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
	&omap44xx_l4_per__timer4,
};

static struct omap_hwmod omap44xx_timer4_hwmod = {
	.name		= "timer4",
	.class		= &omap44xx_timer_hwmod_class,
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	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_timer4_irqs,
	.main_clk	= "timer4_fck",
	.prcm = {
		.omap4 = {
4351
			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_timer4_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer4_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer5 */
static struct omap_hwmod omap44xx_timer5_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
	{ .irq = 41 + OMAP44XX_IRQ_GIC_START },
4363
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
	{
		.pa_start	= 0x40138000,
		.pa_end		= 0x4013807f,
		.flags		= ADDR_TYPE_RT
	},
4372
	{ }
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};

/* l4_abe -> timer5 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_timer5_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_timer5_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
	{
		.pa_start	= 0x49038000,
		.pa_end		= 0x4903807f,
		.flags		= ADDR_TYPE_RT
	},
4390
	{ }
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};

/* l4_abe -> timer5 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_timer5_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_timer5_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* timer5 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
	&omap44xx_l4_abe__timer5,
	&omap44xx_l4_abe__timer5_dma,
};

static struct omap_hwmod omap44xx_timer5_hwmod = {
	.name		= "timer5",
	.class		= &omap44xx_timer_hwmod_class,
4411
	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_timer5_irqs,
	.main_clk	= "timer5_fck",
	.prcm = {
		.omap4 = {
4416
			.clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
B
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4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427
		},
	},
	.slaves		= omap44xx_timer5_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer5_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer6 */
static struct omap_hwmod omap44xx_timer6_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
	{ .irq = 42 + OMAP44XX_IRQ_GIC_START },
4428
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
	{
		.pa_start	= 0x4013a000,
		.pa_end		= 0x4013a07f,
		.flags		= ADDR_TYPE_RT
	},
4437
	{ }
B
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4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454
};

/* l4_abe -> timer6 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_timer6_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_timer6_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
	{
		.pa_start	= 0x4903a000,
		.pa_end		= 0x4903a07f,
		.flags		= ADDR_TYPE_RT
	},
4455
	{ }
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};

/* l4_abe -> timer6 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_timer6_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_timer6_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* timer6 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
	&omap44xx_l4_abe__timer6,
	&omap44xx_l4_abe__timer6_dma,
};

static struct omap_hwmod omap44xx_timer6_hwmod = {
	.name		= "timer6",
	.class		= &omap44xx_timer_hwmod_class,
4476
	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_timer6_irqs,
4478

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	.main_clk	= "timer6_fck",
	.prcm = {
		.omap4 = {
4482
			.clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_timer6_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer6_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer7 */
static struct omap_hwmod omap44xx_timer7_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
	{ .irq = 43 + OMAP44XX_IRQ_GIC_START },
4494
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
	{
		.pa_start	= 0x4013c000,
		.pa_end		= 0x4013c07f,
		.flags		= ADDR_TYPE_RT
	},
4503
	{ }
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};

/* l4_abe -> timer7 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_timer7_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_timer7_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
	{
		.pa_start	= 0x4903c000,
		.pa_end		= 0x4903c07f,
		.flags		= ADDR_TYPE_RT
	},
4521
	{ }
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};

/* l4_abe -> timer7 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_timer7_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_timer7_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* timer7 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
	&omap44xx_l4_abe__timer7,
	&omap44xx_l4_abe__timer7_dma,
};

static struct omap_hwmod omap44xx_timer7_hwmod = {
	.name		= "timer7",
	.class		= &omap44xx_timer_hwmod_class,
4542
	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_timer7_irqs,
	.main_clk	= "timer7_fck",
	.prcm = {
		.omap4 = {
4547
			.clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_timer7_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer7_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer8 */
static struct omap_hwmod omap44xx_timer8_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
	{ .irq = 44 + OMAP44XX_IRQ_GIC_START },
4559
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
	{
		.pa_start	= 0x4013e000,
		.pa_end		= 0x4013e07f,
		.flags		= ADDR_TYPE_RT
	},
4568
	{ }
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};

/* l4_abe -> timer8 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_timer8_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_timer8_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
	{
		.pa_start	= 0x4903e000,
		.pa_end		= 0x4903e07f,
		.flags		= ADDR_TYPE_RT
	},
4586
	{ }
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};

/* l4_abe -> timer8 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_timer8_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_timer8_dma_addrs,
	.user		= OCP_USER_SDMA,
};

/* timer8 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
	&omap44xx_l4_abe__timer8,
	&omap44xx_l4_abe__timer8_dma,
};

static struct omap_hwmod omap44xx_timer8_hwmod = {
	.name		= "timer8",
	.class		= &omap44xx_timer_hwmod_class,
4607
	.clkdm_name	= "abe_clkdm",
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	.mpu_irqs	= omap44xx_timer8_irqs,
	.main_clk	= "timer8_fck",
	.prcm = {
		.omap4 = {
4612
			.clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_timer8_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer8_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer9 */
static struct omap_hwmod omap44xx_timer9_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
	{ .irq = 45 + OMAP44XX_IRQ_GIC_START },
4624
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
	{
		.pa_start	= 0x4803e000,
		.pa_end		= 0x4803e07f,
		.flags		= ADDR_TYPE_RT
	},
4633
	{ }
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};

/* l4_per -> timer9 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_timer9_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_timer9_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* timer9 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
	&omap44xx_l4_per__timer9,
};

static struct omap_hwmod omap44xx_timer9_hwmod = {
	.name		= "timer9",
	.class		= &omap44xx_timer_hwmod_class,
4653
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_timer9_irqs,
	.main_clk	= "timer9_fck",
	.prcm = {
		.omap4 = {
4658
			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_timer9_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer9_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer10 */
static struct omap_hwmod omap44xx_timer10_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
	{ .irq = 46 + OMAP44XX_IRQ_GIC_START },
4670
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
	{
		.pa_start	= 0x48086000,
		.pa_end		= 0x4808607f,
		.flags		= ADDR_TYPE_RT
	},
4679
	{ }
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};

/* l4_per -> timer10 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_timer10_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_timer10_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* timer10 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
	&omap44xx_l4_per__timer10,
};

static struct omap_hwmod omap44xx_timer10_hwmod = {
	.name		= "timer10",
	.class		= &omap44xx_timer_1ms_hwmod_class,
4699
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_timer10_irqs,
	.main_clk	= "timer10_fck",
	.prcm = {
		.omap4 = {
4704
			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_timer10_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer10_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* timer11 */
static struct omap_hwmod omap44xx_timer11_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
	{ .irq = 47 + OMAP44XX_IRQ_GIC_START },
4716
	{ .irq = -1 }
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};

static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
	{
		.pa_start	= 0x48088000,
		.pa_end		= 0x4808807f,
		.flags		= ADDR_TYPE_RT
	},
4725
	{ }
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};

/* l4_per -> timer11 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_timer11_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_timer11_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* timer11 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
	&omap44xx_l4_per__timer11,
};

static struct omap_hwmod omap44xx_timer11_hwmod = {
	.name		= "timer11",
	.class		= &omap44xx_timer_hwmod_class,
4745
	.clkdm_name	= "l4_per_clkdm",
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	.mpu_irqs	= omap44xx_timer11_irqs,
	.main_clk	= "timer11_fck",
	.prcm = {
		.omap4 = {
4750
			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
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		},
	},
	.slaves		= omap44xx_timer11_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_timer11_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
4759 4760
 * 'uart' class
 * universal asynchronous receiver/transmitter (uart)
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 */

4763 4764 4765 4766 4767
static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
	.rev_offs	= 0x0050,
	.sysc_offs	= 0x0054,
	.syss_offs	= 0x0058,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4768 4769
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
4770 4771
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
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	.sysc_fields	= &omap_hwmod_sysc_type1,
};

4775
static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4776 4777
	.name	= "uart",
	.sysc	= &omap44xx_uart_sysc,
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};

4780 4781 4782 4783
/* uart1 */
static struct omap_hwmod omap44xx_uart1_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
	{ .irq = 72 + OMAP44XX_IRQ_GIC_START },
4784
	{ .irq = -1 }
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};

4787 4788 4789
static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4790
	{ .dma_req = -1 }
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4791 4792
};

4793
static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
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4794
	{
4795 4796
		.pa_start	= 0x4806a000,
		.pa_end		= 0x4806a0ff,
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4797 4798
		.flags		= ADDR_TYPE_RT
	},
4799
	{ }
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};

4802 4803 4804 4805 4806 4807
/* l4_per -> uart1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_uart1_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_uart1_addrs,
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	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

4811 4812 4813
/* uart1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
	&omap44xx_l4_per__uart1,
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};

4816 4817 4818
static struct omap_hwmod omap44xx_uart1_hwmod = {
	.name		= "uart1",
	.class		= &omap44xx_uart_hwmod_class,
4819
	.clkdm_name	= "l4_per_clkdm",
4820 4821 4822
	.mpu_irqs	= omap44xx_uart1_irqs,
	.sdma_reqs	= omap44xx_uart1_sdma_reqs,
	.main_clk	= "uart1_fck",
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	.prcm = {
		.omap4 = {
4825
			.clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
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		},
	},
4828 4829
	.slaves		= omap44xx_uart1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_uart1_slaves),
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4830 4831 4832
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

4833 4834 4835 4836
/* uart2 */
static struct omap_hwmod omap44xx_uart2_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
	{ .irq = 73 + OMAP44XX_IRQ_GIC_START },
4837
	{ .irq = -1 }
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};

4840 4841 4842
static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4843
	{ .dma_req = -1 }
4844 4845 4846
};

static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
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	{
4848 4849
		.pa_start	= 0x4806c000,
		.pa_end		= 0x4806c0ff,
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		.flags		= ADDR_TYPE_RT
	},
4852
	{ }
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};

4855 4856
/* l4_per -> uart2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
B
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	.master		= &omap44xx_l4_per_hwmod,
4858 4859 4860
	.slave		= &omap44xx_uart2_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_uart2_addrs,
B
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4861 4862 4863
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

4864 4865 4866
/* uart2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
	&omap44xx_l4_per__uart2,
B
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4867 4868
};

4869 4870 4871
static struct omap_hwmod omap44xx_uart2_hwmod = {
	.name		= "uart2",
	.class		= &omap44xx_uart_hwmod_class,
4872
	.clkdm_name	= "l4_per_clkdm",
4873 4874 4875
	.mpu_irqs	= omap44xx_uart2_irqs,
	.sdma_reqs	= omap44xx_uart2_sdma_reqs,
	.main_clk	= "uart2_fck",
B
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4876 4877
	.prcm = {
		.omap4 = {
4878
			.clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
B
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4879 4880
		},
	},
4881 4882
	.slaves		= omap44xx_uart2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_uart2_slaves),
B
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4883 4884 4885
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

4886 4887 4888 4889
/* uart3 */
static struct omap_hwmod omap44xx_uart3_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
	{ .irq = 74 + OMAP44XX_IRQ_GIC_START },
4890
	{ .irq = -1 }
B
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4891 4892
};

4893 4894 4895
static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4896
	{ .dma_req = -1 }
4897 4898 4899
};

static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
B
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4900
	{
4901 4902
		.pa_start	= 0x48020000,
		.pa_end		= 0x480200ff,
B
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4903 4904
		.flags		= ADDR_TYPE_RT
	},
4905
	{ }
B
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4906 4907
};

4908 4909
/* l4_per -> uart3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
B
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4910
	.master		= &omap44xx_l4_per_hwmod,
4911 4912 4913
	.slave		= &omap44xx_uart3_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_uart3_addrs,
B
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4914 4915 4916
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

4917 4918 4919 4920 4921 4922 4923 4924
/* uart3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
	&omap44xx_l4_per__uart3,
};

static struct omap_hwmod omap44xx_uart3_hwmod = {
	.name		= "uart3",
	.class		= &omap44xx_uart_hwmod_class,
4925
	.clkdm_name	= "l4_per_clkdm",
4926
	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4927 4928 4929
	.mpu_irqs	= omap44xx_uart3_irqs,
	.sdma_reqs	= omap44xx_uart3_sdma_reqs,
	.main_clk	= "uart3_fck",
B
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	.prcm = {
		.omap4 = {
4932
			.clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
B
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		},
	},
4935 4936
	.slaves		= omap44xx_uart3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_uart3_slaves),
B
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4937 4938 4939
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

4940 4941 4942 4943
/* uart4 */
static struct omap_hwmod omap44xx_uart4_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
	{ .irq = 70 + OMAP44XX_IRQ_GIC_START },
4944
	{ .irq = -1 }
B
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};

4947 4948 4949
static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4950
	{ .dma_req = -1 }
4951 4952 4953
};

static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
B
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	{
4955 4956
		.pa_start	= 0x4806e000,
		.pa_end		= 0x4806e0ff,
B
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4957 4958
		.flags		= ADDR_TYPE_RT
	},
4959
	{ }
B
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4960 4961
};

4962 4963
/* l4_per -> uart4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
B
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	.master		= &omap44xx_l4_per_hwmod,
4965 4966 4967
	.slave		= &omap44xx_uart4_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_uart4_addrs,
B
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	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

4971 4972 4973
/* uart4 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
	&omap44xx_l4_per__uart4,
B
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};

4976 4977 4978
static struct omap_hwmod omap44xx_uart4_hwmod = {
	.name		= "uart4",
	.class		= &omap44xx_uart_hwmod_class,
4979
	.clkdm_name	= "l4_per_clkdm",
4980 4981 4982
	.mpu_irqs	= omap44xx_uart4_irqs,
	.sdma_reqs	= omap44xx_uart4_sdma_reqs,
	.main_clk	= "uart4_fck",
B
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4983 4984
	.prcm = {
		.omap4 = {
4985
			.clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
B
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4986 4987
		},
	},
4988 4989
	.slaves		= omap44xx_uart4_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_uart4_slaves),
B
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4990 4991 4992
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

B
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4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011
/*
 * 'usb_otg_hs' class
 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
	.rev_offs	= 0x0400,
	.sysc_offs	= 0x0404,
	.syss_offs	= 0x0408,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
			   SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
			   MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
5012 5013
	.name	= "usb_otg_hs",
	.sysc	= &omap44xx_usb_otg_hs_sysc,
B
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5014 5015 5016 5017 5018 5019
};

/* usb_otg_hs */
static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
	{ .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
	{ .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
5020
	{ .irq = -1 }
B
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5021 5022 5023 5024 5025 5026 5027 5028 5029 5030 5031 5032 5033
};

/* usb_otg_hs master ports */
static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
	&omap44xx_usb_otg_hs__l3_main_2,
};

static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
	{
		.pa_start	= 0x4a0ab000,
		.pa_end		= 0x4a0ab003,
		.flags		= ADDR_TYPE_RT
	},
5034
	{ }
B
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5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057
};

/* l4_cfg -> usb_otg_hs */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_usb_otg_hs_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_usb_otg_hs_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* usb_otg_hs slave ports */
static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
	&omap44xx_l4_cfg__usb_otg_hs,
};

static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
	{ .role = "xclk", .clk = "usb_otg_hs_xclk" },
};

static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
	.name		= "usb_otg_hs",
	.class		= &omap44xx_usb_otg_hs_hwmod_class,
5058
	.clkdm_name	= "l3_init_clkdm",
B
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5059 5060 5061 5062 5063
	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
	.mpu_irqs	= omap44xx_usb_otg_hs_irqs,
	.main_clk	= "usb_otg_hs_ick",
	.prcm = {
		.omap4 = {
5064
			.clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
B
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5065 5066 5067
		},
	},
	.opt_clks	= usb_otg_hs_opt_clks,
5068
	.opt_clks_cnt	= ARRAY_SIZE(usb_otg_hs_opt_clks),
B
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5069 5070 5071 5072 5073 5074 5075
	.slaves		= omap44xx_usb_otg_hs_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
	.masters	= omap44xx_usb_otg_hs_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086
/*
 * 'wd_timer' class
 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 * overflow condition
 */

static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
5087
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5088 5089
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
5090
	.sysc_fields	= &omap_hwmod_sysc_type1,
B
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5091 5092
};

5093 5094 5095
static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
	.name		= "wd_timer",
	.sysc		= &omap44xx_wd_timer_sysc,
5096
	.pre_shutdown	= &omap2_wd_timer_disable,
5097 5098 5099 5100 5101 5102
};

/* wd_timer2 */
static struct omap_hwmod omap44xx_wd_timer2_hwmod;
static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
	{ .irq = 80 + OMAP44XX_IRQ_GIC_START },
5103
	{ .irq = -1 }
5104 5105 5106
};

static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
B
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5107
	{
5108 5109
		.pa_start	= 0x4a314000,
		.pa_end		= 0x4a31407f,
B
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5110 5111
		.flags		= ADDR_TYPE_RT
	},
5112
	{ }
B
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5113 5114
};

5115 5116 5117 5118 5119 5120
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
	.master		= &omap44xx_l4_wkup_hwmod,
	.slave		= &omap44xx_wd_timer2_hwmod,
	.clk		= "l4_wkup_clk_mux_ck",
	.addr		= omap44xx_wd_timer2_addrs,
B
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5121 5122 5123
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

5124 5125 5126
/* wd_timer2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
	&omap44xx_l4_wkup__wd_timer2,
B
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5127 5128
};

5129 5130 5131
static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
	.name		= "wd_timer2",
	.class		= &omap44xx_wd_timer_hwmod_class,
5132
	.clkdm_name	= "l4_wkup_clkdm",
5133 5134
	.mpu_irqs	= omap44xx_wd_timer2_irqs,
	.main_clk	= "wd_timer2_fck",
B
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5135 5136
	.prcm = {
		.omap4 = {
5137
			.clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
B
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5138 5139
		},
	},
5140 5141
	.slaves		= omap44xx_wd_timer2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_wd_timer2_slaves),
B
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5142 5143 5144
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

5145 5146 5147 5148
/* wd_timer3 */
static struct omap_hwmod omap44xx_wd_timer3_hwmod;
static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
	{ .irq = 36 + OMAP44XX_IRQ_GIC_START },
5149
	{ .irq = -1 }
B
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5150 5151
};

5152
static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
B
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5153
	{
5154 5155
		.pa_start	= 0x40130000,
		.pa_end		= 0x4013007f,
B
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5156 5157
		.flags		= ADDR_TYPE_RT
	},
5158
	{ }
B
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5159 5160
};

5161 5162 5163 5164 5165 5166 5167
/* l4_abe -> wd_timer3 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_wd_timer3_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_wd_timer3_addrs,
	.user		= OCP_USER_MPU,
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5168 5169
};

5170 5171 5172 5173 5174 5175
static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
	{
		.pa_start	= 0x49030000,
		.pa_end		= 0x4903007f,
		.flags		= ADDR_TYPE_RT
	},
5176
	{ }
B
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5177 5178
};

5179 5180 5181 5182 5183 5184 5185
/* l4_abe -> wd_timer3 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
	.master		= &omap44xx_l4_abe_hwmod,
	.slave		= &omap44xx_wd_timer3_hwmod,
	.clk		= "ocp_abe_iclk",
	.addr		= omap44xx_wd_timer3_dma_addrs,
	.user		= OCP_USER_SDMA,
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5186 5187
};

5188 5189 5190 5191 5192 5193 5194 5195 5196
/* wd_timer3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
	&omap44xx_l4_abe__wd_timer3,
	&omap44xx_l4_abe__wd_timer3_dma,
};

static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
	.name		= "wd_timer3",
	.class		= &omap44xx_wd_timer_hwmod_class,
5197
	.clkdm_name	= "abe_clkdm",
5198 5199
	.mpu_irqs	= omap44xx_wd_timer3_irqs,
	.main_clk	= "wd_timer3_fck",
B
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5200 5201
	.prcm = {
		.omap4 = {
5202
			.clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
B
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5203 5204
		},
	},
5205 5206
	.slaves		= omap44xx_wd_timer3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_wd_timer3_slaves),
B
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5207 5208
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
B
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5209

5210
static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5211

5212 5213
	/* dmm class */
	&omap44xx_dmm_hwmod,
5214

5215 5216
	/* emif_fw class */
	&omap44xx_emif_fw_hwmod,
5217

5218 5219 5220 5221 5222
	/* l3 class */
	&omap44xx_l3_instr_hwmod,
	&omap44xx_l3_main_1_hwmod,
	&omap44xx_l3_main_2_hwmod,
	&omap44xx_l3_main_3_hwmod,
5223

5224 5225 5226 5227 5228
	/* l4 class */
	&omap44xx_l4_abe_hwmod,
	&omap44xx_l4_cfg_hwmod,
	&omap44xx_l4_per_hwmod,
	&omap44xx_l4_wkup_hwmod,
B
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5229

5230 5231 5232
	/* mpu_bus class */
	&omap44xx_mpu_private_hwmod,

5233 5234 5235 5236 5237 5238 5239 5240 5241
	/* aess class */
/*	&omap44xx_aess_hwmod, */

	/* bandgap class */
	&omap44xx_bandgap_hwmod,

	/* counter class */
/*	&omap44xx_counter_32k_hwmod, */

5242 5243 5244
	/* dma class */
	&omap44xx_dma_system_hwmod,

B
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5245 5246 5247
	/* dmic class */
	&omap44xx_dmic_hwmod,

5248 5249 5250 5251
	/* dsp class */
	&omap44xx_dsp_hwmod,
	&omap44xx_dsp_c0_hwmod,

5252 5253 5254 5255 5256 5257 5258 5259 5260
	/* dss class */
	&omap44xx_dss_hwmod,
	&omap44xx_dss_dispc_hwmod,
	&omap44xx_dss_dsi1_hwmod,
	&omap44xx_dss_dsi2_hwmod,
	&omap44xx_dss_hdmi_hwmod,
	&omap44xx_dss_rfbi_hwmod,
	&omap44xx_dss_venc_hwmod,

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5261 5262 5263 5264 5265 5266 5267 5268
	/* gpio class */
	&omap44xx_gpio1_hwmod,
	&omap44xx_gpio2_hwmod,
	&omap44xx_gpio3_hwmod,
	&omap44xx_gpio4_hwmod,
	&omap44xx_gpio5_hwmod,
	&omap44xx_gpio6_hwmod,

5269 5270 5271
	/* hsi class */
/*	&omap44xx_hsi_hwmod, */

5272 5273 5274 5275 5276 5277
	/* i2c class */
	&omap44xx_i2c1_hwmod,
	&omap44xx_i2c2_hwmod,
	&omap44xx_i2c3_hwmod,
	&omap44xx_i2c4_hwmod,

5278 5279 5280 5281 5282 5283 5284 5285
	/* ipu class */
	&omap44xx_ipu_hwmod,
	&omap44xx_ipu_c0_hwmod,
	&omap44xx_ipu_c1_hwmod,

	/* iss class */
/*	&omap44xx_iss_hwmod, */

5286 5287 5288 5289 5290
	/* iva class */
	&omap44xx_iva_hwmod,
	&omap44xx_iva_seq0_hwmod,
	&omap44xx_iva_seq1_hwmod,

5291
	/* kbd class */
S
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5292
	&omap44xx_kbd_hwmod,
5293

B
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5294 5295 5296
	/* mailbox class */
	&omap44xx_mailbox_hwmod,

B
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5297 5298 5299 5300 5301 5302
	/* mcbsp class */
	&omap44xx_mcbsp1_hwmod,
	&omap44xx_mcbsp2_hwmod,
	&omap44xx_mcbsp3_hwmod,
	&omap44xx_mcbsp4_hwmod,

5303 5304 5305
	/* mcpdm class */
/*	&omap44xx_mcpdm_hwmod, */

B
Benoit Cousson 已提交
5306 5307 5308 5309 5310 5311
	/* mcspi class */
	&omap44xx_mcspi1_hwmod,
	&omap44xx_mcspi2_hwmod,
	&omap44xx_mcspi3_hwmod,
	&omap44xx_mcspi4_hwmod,

5312
	/* mmc class */
A
Anand Gadiyar 已提交
5313 5314 5315 5316 5317
	&omap44xx_mmc1_hwmod,
	&omap44xx_mmc2_hwmod,
	&omap44xx_mmc3_hwmod,
	&omap44xx_mmc4_hwmod,
	&omap44xx_mmc5_hwmod,
5318

5319 5320
	/* mpu class */
	&omap44xx_mpu_hwmod,
5321

5322 5323 5324 5325 5326
	/* smartreflex class */
	&omap44xx_smartreflex_core_hwmod,
	&omap44xx_smartreflex_iva_hwmod,
	&omap44xx_smartreflex_mpu_hwmod,

5327 5328 5329
	/* spinlock class */
	&omap44xx_spinlock_hwmod,

B
Benoit Cousson 已提交
5330 5331 5332 5333 5334 5335 5336 5337 5338 5339 5340 5341 5342
	/* timer class */
	&omap44xx_timer1_hwmod,
	&omap44xx_timer2_hwmod,
	&omap44xx_timer3_hwmod,
	&omap44xx_timer4_hwmod,
	&omap44xx_timer5_hwmod,
	&omap44xx_timer6_hwmod,
	&omap44xx_timer7_hwmod,
	&omap44xx_timer8_hwmod,
	&omap44xx_timer9_hwmod,
	&omap44xx_timer10_hwmod,
	&omap44xx_timer11_hwmod,

5343 5344 5345 5346 5347
	/* uart class */
	&omap44xx_uart1_hwmod,
	&omap44xx_uart2_hwmod,
	&omap44xx_uart3_hwmod,
	&omap44xx_uart4_hwmod,
5348

B
Benoit Cousson 已提交
5349 5350 5351
	/* usb_otg_hs class */
	&omap44xx_usb_otg_hs_hwmod,

5352 5353 5354 5355
	/* wd_timer class */
	&omap44xx_wd_timer2_hwmod,
	&omap44xx_wd_timer3_hwmod,

5356 5357 5358 5359 5360
	NULL,
};

int __init omap44xx_hwmod_init(void)
{
5361
	return omap_hwmod_register(omap44xx_hwmods);
5362 5363
}