fsl_rio.c 42.0 KB
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/*
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 * Freescale MPC85xx/MPC86xx RapidIO support
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 *
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 * Copyright 2009 Sysgo AG
 * Thomas Moll <thomas.moll@sysgo.com>
 * - fixed maintenance access routines, check for aligned access
 *
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 * Copyright 2009 Integrated Device Technology, Inc.
 * Alex Bounine <alexandre.bounine@idt.com>
 * - Added Port-Write message handling
 * - Added Machine Check exception handling
 *
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 * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc.
 * Zhang Wei <wei.zhang@freescale.com>
 *
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 * Copyright 2005 MontaVista Software, Inc.
 * Matt Porter <mporter@kernel.crashing.org>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <linux/rio.h>
#include <linux/rio_drv.h>
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#include <linux/of_platform.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/kfifo.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
#include <asm/uaccess.h>
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#undef DEBUG_PW	/* Port-Write debugging */

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/* RapidIO definition irq, which read from OF-tree */
#define IRQ_RIO_BELL(m)		(((struct rio_priv *)(m->priv))->bellirq)
#define IRQ_RIO_TX(m)		(((struct rio_priv *)(m->priv))->txirq)
#define IRQ_RIO_RX(m)		(((struct rio_priv *)(m->priv))->rxirq)
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#define IRQ_RIO_PW(m)		(((struct rio_priv *)(m->priv))->pwirq)
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#define RIO_ATMU_REGS_OFFSET	0x10c00
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#define RIO_P_MSG_REGS_OFFSET	0x11000
#define RIO_S_MSG_REGS_OFFSET	0x13000
#define RIO_ESCSR		0x158
#define RIO_CCSR		0x15c
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#define RIO_LTLEDCSR		0x0608
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#define  RIO_LTLEDCSR_IER	0x80000000
#define  RIO_LTLEDCSR_PRT	0x01000000
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#define RIO_LTLEECSR		0x060c
#define RIO_EPWISR		0x10010
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#define RIO_ISR_AACR		0x10120
#define RIO_ISR_AACR_AA		0x1	/* Accept All ID */
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#define RIO_MAINT_WIN_SIZE	0x400000
#define RIO_DBELL_WIN_SIZE	0x1000

#define RIO_MSG_OMR_MUI		0x00000002
#define RIO_MSG_OSR_TE		0x00000080
#define RIO_MSG_OSR_QOI		0x00000020
#define RIO_MSG_OSR_QFI		0x00000010
#define RIO_MSG_OSR_MUB		0x00000004
#define RIO_MSG_OSR_EOMI	0x00000002
#define RIO_MSG_OSR_QEI		0x00000001

#define RIO_MSG_IMR_MI		0x00000002
#define RIO_MSG_ISR_TE		0x00000080
#define RIO_MSG_ISR_QFI		0x00000010
#define RIO_MSG_ISR_DIQI	0x00000001

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#define RIO_IPWMR_SEN		0x00100000
#define RIO_IPWMR_QFIE		0x00000100
#define RIO_IPWMR_EIE		0x00000020
#define RIO_IPWMR_CQ		0x00000002
#define RIO_IPWMR_PWE		0x00000001

#define RIO_IPWSR_QF		0x00100000
#define RIO_IPWSR_TE		0x00000080
#define RIO_IPWSR_QFI		0x00000010
#define RIO_IPWSR_PWD		0x00000008
#define RIO_IPWSR_PWB		0x00000004

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#define RIO_MSG_DESC_SIZE	32
#define RIO_MSG_BUFFER_SIZE	4096
#define RIO_MIN_TX_RING_SIZE	2
#define RIO_MAX_TX_RING_SIZE	2048
#define RIO_MIN_RX_RING_SIZE	2
#define RIO_MAX_RX_RING_SIZE	2048

#define DOORBELL_DMR_DI		0x00000002
#define DOORBELL_DSR_TE		0x00000080
#define DOORBELL_DSR_QFI	0x00000010
#define DOORBELL_DSR_DIQI	0x00000001
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#define DOORBELL_TID_OFFSET	0x02
#define DOORBELL_SID_OFFSET	0x04
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#define DOORBELL_INFO_OFFSET	0x06

#define DOORBELL_MESSAGE_SIZE	0x08
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#define DBELL_SID(x)		(*(u16 *)(x + DOORBELL_SID_OFFSET))
#define DBELL_TID(x)		(*(u16 *)(x + DOORBELL_TID_OFFSET))
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#define DBELL_INF(x)		(*(u16 *)(x + DOORBELL_INFO_OFFSET))

struct rio_atmu_regs {
	u32 rowtar;
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	u32 rowtear;
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	u32 rowbar;
	u32 pad2;
	u32 rowar;
	u32 pad3[3];
};

struct rio_msg_regs {
	u32 omr;
	u32 osr;
	u32 pad1;
	u32 odqdpar;
	u32 pad2;
	u32 osar;
	u32 odpr;
	u32 odatr;
	u32 odcr;
	u32 pad3;
	u32 odqepar;
	u32 pad4[13];
	u32 imr;
	u32 isr;
	u32 pad5;
	u32 ifqdpar;
	u32 pad6;
	u32 ifqepar;
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	u32 pad7[226];
	u32 odmr;
	u32 odsr;
	u32 res0[4];
	u32 oddpr;
	u32 oddatr;
	u32 res1[3];
	u32 odretcr;
	u32 res2[12];
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	u32 dmr;
	u32 dsr;
	u32 pad8;
	u32 dqdpar;
	u32 pad9;
	u32 dqepar;
	u32 pad10[26];
	u32 pwmr;
	u32 pwsr;
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	u32 epwqbar;
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	u32 pwqbar;
};

struct rio_tx_desc {
	u32 res1;
	u32 saddr;
	u32 dport;
	u32 dattr;
	u32 res2;
	u32 res3;
	u32 dwcnt;
	u32 res4;
};

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struct rio_dbell_ring {
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	void *virt;
	dma_addr_t phys;
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};
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struct rio_msg_tx_ring {
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	void *virt;
	dma_addr_t phys;
	void *virt_buffer[RIO_MAX_TX_RING_SIZE];
	dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
	int tx_slot;
	int size;
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	void *dev_id;
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};
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struct rio_msg_rx_ring {
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	void *virt;
	dma_addr_t phys;
	void *virt_buffer[RIO_MAX_RX_RING_SIZE];
	int rx_slot;
	int size;
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	void *dev_id;
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};

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struct rio_port_write_msg {
	void *virt;
	dma_addr_t phys;
	u32 msg_count;
	u32 err_count;
	u32 discard_count;
};

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struct rio_priv {
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	struct device *dev;
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	void __iomem *regs_win;
	struct rio_atmu_regs __iomem *atmu_regs;
	struct rio_atmu_regs __iomem *maint_atmu_regs;
	struct rio_atmu_regs __iomem *dbell_atmu_regs;
	void __iomem *dbell_win;
	void __iomem *maint_win;
	struct rio_msg_regs __iomem *msg_regs;
	struct rio_dbell_ring dbell_ring;
	struct rio_msg_tx_ring msg_tx_ring;
	struct rio_msg_rx_ring msg_rx_ring;
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	struct rio_port_write_msg port_write_msg;
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	int bellirq;
	int txirq;
	int rxirq;
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	int pwirq;
	struct work_struct pw_work;
	struct kfifo pw_fifo;
	spinlock_t pw_fifo_lock;
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};
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#define __fsl_read_rio_config(x, addr, err, op)		\
	__asm__ __volatile__(				\
		"1:	"op" %1,0(%2)\n"		\
		"	eieio\n"			\
		"2:\n"					\
		".section .fixup,\"ax\"\n"		\
		"3:	li %1,-1\n"			\
		"	li %0,%3\n"			\
		"	b 2b\n"				\
		".section __ex_table,\"a\"\n"		\
		"	.align 2\n"			\
		"	.long 1b,3b\n"			\
		".text"					\
		: "=r" (err), "=r" (x)			\
		: "b" (addr), "i" (-EFAULT), "0" (err))

static void __iomem *rio_regs_win;

static int (*saved_mcheck_exception)(struct pt_regs *regs);

static int fsl_rio_mcheck_exception(struct pt_regs *regs)
{
	const struct exception_table_entry *entry = NULL;
	unsigned long reason = (mfspr(SPRN_MCSR) & MCSR_MASK);

	if (reason & MCSR_BUS_RBERR) {
		reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
		if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
			/* Check if we are prepared to handle this fault */
			entry = search_exception_tables(regs->nip);
			if (entry) {
				pr_debug("RIO: %s - MC Exception handled\n",
					 __func__);
				out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
					 0);
				regs->msr |= MSR_RI;
				regs->nip = entry->fixup;
				return 1;
			}
		}
	}

	if (saved_mcheck_exception)
		return saved_mcheck_exception(regs);
	else
		return cur_cpu_spec->machine_check(regs);
}

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/**
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 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
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 * @mport: RapidIO master port info
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 * @index: ID of RapidIO interface
 * @destid: Destination ID of target device
 * @data: 16-bit info field of RapidIO doorbell message
 *
 * Sends a MPC85xx doorbell message. Returns %0 on success or
 * %-EINVAL on failure.
 */
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static int fsl_rio_doorbell_send(struct rio_mport *mport,
				int index, u16 destid, u16 data)
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{
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	struct rio_priv *priv = mport->priv;
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	pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
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		 index, destid, data);
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	switch (mport->phy_type) {
	case RIO_PHY_PARALLEL:
		out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
		out_be16(priv->dbell_win, data);
		break;
	case RIO_PHY_SERIAL:
		/* In the serial version silicons, such as MPC8548, MPC8641,
		 * below operations is must be.
		 */
		out_be32(&priv->msg_regs->odmr, 0x00000000);
		out_be32(&priv->msg_regs->odretcr, 0x00000004);
		out_be32(&priv->msg_regs->oddpr, destid << 16);
		out_be32(&priv->msg_regs->oddatr, data);
		out_be32(&priv->msg_regs->odmr, 0x00000001);
		break;
	}
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	return 0;
}

/**
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 * fsl_local_config_read - Generate a MPC85xx local config space read
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 * @mport: RapidIO master port info
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 * @index: ID of RapdiIO interface
 * @offset: Offset into configuration space
 * @len: Length (in bytes) of the maintenance transaction
 * @data: Value to be read into
 *
 * Generates a MPC85xx local configuration space read. Returns %0 on
 * success or %-EINVAL on failure.
 */
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static int fsl_local_config_read(struct rio_mport *mport,
				int index, u32 offset, int len, u32 *data)
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{
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	struct rio_priv *priv = mport->priv;
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	pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
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		 offset);
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	*data = in_be32(priv->regs_win + offset);
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	return 0;
}

/**
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 * fsl_local_config_write - Generate a MPC85xx local config space write
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 * @mport: RapidIO master port info
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 * @index: ID of RapdiIO interface
 * @offset: Offset into configuration space
 * @len: Length (in bytes) of the maintenance transaction
 * @data: Value to be written
 *
 * Generates a MPC85xx local configuration space write. Returns %0 on
 * success or %-EINVAL on failure.
 */
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static int fsl_local_config_write(struct rio_mport *mport,
				int index, u32 offset, int len, u32 data)
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{
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	struct rio_priv *priv = mport->priv;
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	pr_debug
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	    ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
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	     index, offset, data);
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	out_be32(priv->regs_win + offset, data);
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	return 0;
}

/**
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 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
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 * @mport: RapidIO master port info
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 * @index: ID of RapdiIO interface
 * @destid: Destination ID of transaction
 * @hopcount: Number of hops to target device
 * @offset: Offset into configuration space
 * @len: Length (in bytes) of the maintenance transaction
 * @val: Location to be read into
 *
 * Generates a MPC85xx read maintenance transaction. Returns %0 on
 * success or %-EINVAL on failure.
 */
static int
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fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
			u8 hopcount, u32 offset, int len, u32 *val)
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{
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	struct rio_priv *priv = mport->priv;
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	u8 *data;
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	u32 rval, err = 0;
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	pr_debug
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	    ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
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	     index, destid, hopcount, offset, len);
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	/* 16MB maintenance window possible */
	/* allow only aligned access to maintenance registers */
	if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
		return -EINVAL;

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	out_be32(&priv->maint_atmu_regs->rowtar,
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		 (destid << 22) | (hopcount << 12) | (offset >> 12));
	out_be32(&priv->maint_atmu_regs->rowtear,  (destid >> 10));
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	data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
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	switch (len) {
	case 1:
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		__fsl_read_rio_config(rval, data, err, "lbz");
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		break;
	case 2:
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		__fsl_read_rio_config(rval, data, err, "lhz");
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		break;
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	case 4:
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		__fsl_read_rio_config(rval, data, err, "lwz");
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		break;
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	default:
		return -EINVAL;
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	}

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	if (err) {
		pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
			 err, destid, hopcount, offset);
	}

	*val = rval;

	return err;
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}

/**
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 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
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 * @mport: RapidIO master port info
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 * @index: ID of RapdiIO interface
 * @destid: Destination ID of transaction
 * @hopcount: Number of hops to target device
 * @offset: Offset into configuration space
 * @len: Length (in bytes) of the maintenance transaction
 * @val: Value to be written
 *
 * Generates an MPC85xx write maintenance transaction. Returns %0 on
 * success or %-EINVAL on failure.
 */
static int
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fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
			u8 hopcount, u32 offset, int len, u32 val)
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{
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	struct rio_priv *priv = mport->priv;
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	u8 *data;
	pr_debug
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	    ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
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	     index, destid, hopcount, offset, len, val);
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	/* 16MB maintenance windows possible */
	/* allow only aligned access to maintenance registers */
	if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
		return -EINVAL;

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	out_be32(&priv->maint_atmu_regs->rowtar,
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		 (destid << 22) | (hopcount << 12) | (offset >> 12));
	out_be32(&priv->maint_atmu_regs->rowtear,  (destid >> 10));
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	data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
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	switch (len) {
	case 1:
		out_8((u8 *) data, val);
		break;
	case 2:
		out_be16((u16 *) data, val);
		break;
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	case 4:
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		out_be32((u32 *) data, val);
		break;
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	default:
		return -EINVAL;
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	}

	return 0;
}

/**
 * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
 * @mport: Master port with outbound message queue
 * @rdev: Target of outbound message
 * @mbox: Outbound mailbox
 * @buffer: Message to add to outbound queue
 * @len: Length of message
 *
 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
 * %0 on success or %-EINVAL on failure.
 */
int
rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
			void *buffer, size_t len)
{
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	struct rio_priv *priv = mport->priv;
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	u32 omr;
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	struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt
					+ priv->msg_tx_ring.tx_slot;
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	int ret = 0;

	pr_debug
	    ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
	     rdev->destid, mbox, (int)buffer, len);

	if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
		ret = -EINVAL;
		goto out;
	}

	/* Copy and clear rest of buffer */
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	memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer,
			len);
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	if (len < (RIO_MAX_MSG_SIZE - 4))
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		memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
				+ len, 0, RIO_MAX_MSG_SIZE - len);
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	switch (mport->phy_type) {
	case RIO_PHY_PARALLEL:
		/* Set mbox field for message */
		desc->dport = mbox & 0x3;
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		/* Enable EOMI interrupt, set priority, and set destid */
		desc->dattr = 0x28000000 | (rdev->destid << 2);
		break;
	case RIO_PHY_SERIAL:
		/* Set mbox field for message, and set destid */
		desc->dport = (rdev->destid << 16) | (mbox & 0x3);

		/* Enable EOMI interrupt and priority */
		desc->dattr = 0x28000000;
		break;
	}
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	/* Set transfer size aligned to next power of 2 (in double words) */
	desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);

	/* Set snooping and source buffer address */
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	desc->saddr = 0x00000004
		| priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
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	/* Increment enqueue pointer */
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	omr = in_be32(&priv->msg_regs->omr);
	out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
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	/* Go to next descriptor */
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	if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
		priv->msg_tx_ring.tx_slot = 0;
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      out:
	return ret;
}

EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);

/**
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 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
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 * @irq: Linux interrupt number
 * @dev_instance: Pointer to interrupt-specific data
 *
 * Handles outbound message interrupts. Executes a register outbound
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 * mailbox event handler and acks the interrupt occurrence.
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 */
static irqreturn_t
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fsl_rio_tx_handler(int irq, void *dev_instance)
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{
	int osr;
	struct rio_mport *port = (struct rio_mport *)dev_instance;
551
	struct rio_priv *priv = port->priv;
M
Matt Porter 已提交
552

553
	osr = in_be32(&priv->msg_regs->osr);
M
Matt Porter 已提交
554 555 556

	if (osr & RIO_MSG_OSR_TE) {
		pr_info("RIO: outbound message transmission error\n");
557
		out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
M
Matt Porter 已提交
558 559 560 561 562
		goto out;
	}

	if (osr & RIO_MSG_OSR_QOI) {
		pr_info("RIO: outbound message queue overflow\n");
563
		out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
M
Matt Porter 已提交
564 565 566 567
		goto out;
	}

	if (osr & RIO_MSG_OSR_EOMI) {
568 569 570 571
		u32 dqp = in_be32(&priv->msg_regs->odqdpar);
		int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
		port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1,
				slot);
M
Matt Porter 已提交
572 573

		/* Ack the end-of-message interrupt */
574
		out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
M
Matt Porter 已提交
575 576 577 578 579 580 581 582 583
	}

      out:
	return IRQ_HANDLED;
}

/**
 * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
 * @mport: Master port implementing the outbound message unit
584
 * @dev_id: Device specific pointer to pass on event
M
Matt Porter 已提交
585 586 587 588 589 590 591
 * @mbox: Mailbox to open
 * @entries: Number of entries in the outbound mailbox ring
 *
 * Initializes buffer ring, request the outbound message interrupt,
 * and enables the outbound message unit. Returns %0 on success and
 * %-EINVAL or %-ENOMEM on failure.
 */
592
int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
M
Matt Porter 已提交
593 594
{
	int i, j, rc = 0;
595
	struct rio_priv *priv = mport->priv;
M
Matt Porter 已提交
596 597 598 599 600 601 602 603

	if ((entries < RIO_MIN_TX_RING_SIZE) ||
	    (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
		rc = -EINVAL;
		goto out;
	}

	/* Initialize shadow copy ring */
604 605 606 607 608
	priv->msg_tx_ring.dev_id = dev_id;
	priv->msg_tx_ring.size = entries;

	for (i = 0; i < priv->msg_tx_ring.size; i++) {
		priv->msg_tx_ring.virt_buffer[i] =
609
			dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
610 611
				&priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
		if (!priv->msg_tx_ring.virt_buffer[i]) {
M
Matt Porter 已提交
612
			rc = -ENOMEM;
613 614
			for (j = 0; j < priv->msg_tx_ring.size; j++)
				if (priv->msg_tx_ring.virt_buffer[j])
615
					dma_free_coherent(priv->dev,
616 617 618 619 620
							RIO_MSG_BUFFER_SIZE,
							priv->msg_tx_ring.
							virt_buffer[j],
							priv->msg_tx_ring.
							phys_buffer[j]);
M
Matt Porter 已提交
621 622 623 624 625
			goto out;
		}
	}

	/* Initialize outbound message descriptor ring */
626
	priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
627 628 629
				priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
				&priv->msg_tx_ring.phys, GFP_KERNEL);
	if (!priv->msg_tx_ring.virt) {
M
Matt Porter 已提交
630 631 632
		rc = -ENOMEM;
		goto out_dma;
	}
633 634 635
	memset(priv->msg_tx_ring.virt, 0,
			priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
	priv->msg_tx_ring.tx_slot = 0;
M
Matt Porter 已提交
636 637

	/* Point dequeue/enqueue pointers at first entry in ring */
638 639
	out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
	out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
M
Matt Porter 已提交
640 641

	/* Configure for snooping */
642
	out_be32(&priv->msg_regs->osar, 0x00000004);
M
Matt Porter 已提交
643 644

	/* Clear interrupt status */
645
	out_be32(&priv->msg_regs->osr, 0x000000b3);
M
Matt Porter 已提交
646 647

	/* Hook up outbound message handler */
648 649 650
	rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
			 "msg_tx", (void *)mport);
	if (rc < 0)
M
Matt Porter 已提交
651 652 653 654 655 656 657 658 659
		goto out_irq;

	/*
	 * Configure outbound message unit
	 *      Snooping
	 *      Interrupts (all enabled, except QEIE)
	 *      Chaining mode
	 *      Disable
	 */
660
	out_be32(&priv->msg_regs->omr, 0x00100220);
M
Matt Porter 已提交
661 662

	/* Set number of entries */
663 664
	out_be32(&priv->msg_regs->omr,
		 in_be32(&priv->msg_regs->omr) |
M
Matt Porter 已提交
665 666 667
		 ((get_bitmask_order(entries) - 2) << 12));

	/* Now enable the unit */
668
	out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1);
M
Matt Porter 已提交
669 670 671 672 673

      out:
	return rc;

      out_irq:
674 675
	dma_free_coherent(priv->dev,
			  priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
676
			  priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
M
Matt Porter 已提交
677 678

      out_dma:
679
	for (i = 0; i < priv->msg_tx_ring.size; i++)
680
		dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
681 682
				  priv->msg_tx_ring.virt_buffer[i],
				  priv->msg_tx_ring.phys_buffer[i]);
M
Matt Porter 已提交
683 684 685 686 687 688 689 690 691 692 693 694 695 696

	return rc;
}

/**
 * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
 * @mport: Master port implementing the outbound message unit
 * @mbox: Mailbox to close
 *
 * Disables the outbound message unit, free all buffers, and
 * frees the outbound message interrupt.
 */
void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
{
697
	struct rio_priv *priv = mport->priv;
M
Matt Porter 已提交
698
	/* Disable inbound message unit */
699
	out_be32(&priv->msg_regs->omr, 0);
M
Matt Porter 已提交
700 701

	/* Free ring */
702 703
	dma_free_coherent(priv->dev,
			  priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
704
			  priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
M
Matt Porter 已提交
705 706

	/* Free interrupt */
707
	free_irq(IRQ_RIO_TX(mport), (void *)mport);
M
Matt Porter 已提交
708 709 710
}

/**
711
 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
M
Matt Porter 已提交
712 713 714 715
 * @irq: Linux interrupt number
 * @dev_instance: Pointer to interrupt-specific data
 *
 * Handles inbound message interrupts. Executes a registered inbound
716
 * mailbox event handler and acks the interrupt occurrence.
M
Matt Porter 已提交
717 718
 */
static irqreturn_t
719
fsl_rio_rx_handler(int irq, void *dev_instance)
M
Matt Porter 已提交
720 721 722
{
	int isr;
	struct rio_mport *port = (struct rio_mport *)dev_instance;
723
	struct rio_priv *priv = port->priv;
M
Matt Porter 已提交
724

725
	isr = in_be32(&priv->msg_regs->isr);
M
Matt Porter 已提交
726 727 728

	if (isr & RIO_MSG_ISR_TE) {
		pr_info("RIO: inbound message reception error\n");
729
		out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE);
M
Matt Porter 已提交
730 731 732 733 734 735 736 737 738 739 740
		goto out;
	}

	/* XXX Need to check/dispatch until queue empty */
	if (isr & RIO_MSG_ISR_DIQI) {
		/*
		 * We implement *only* mailbox 0, but can receive messages
		 * for any mailbox/letter to that mailbox destination. So,
		 * make the callback with an unknown/invalid mailbox number
		 * argument.
		 */
741
		port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
M
Matt Porter 已提交
742 743

		/* Ack the queueing interrupt */
744
		out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
M
Matt Porter 已提交
745 746 747 748 749 750 751 752 753
	}

      out:
	return IRQ_HANDLED;
}

/**
 * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
 * @mport: Master port implementing the inbound message unit
754
 * @dev_id: Device specific pointer to pass on event
M
Matt Porter 已提交
755 756 757 758 759 760 761
 * @mbox: Mailbox to open
 * @entries: Number of entries in the inbound mailbox ring
 *
 * Initializes buffer ring, request the inbound message interrupt,
 * and enables the inbound message unit. Returns %0 on success
 * and %-EINVAL or %-ENOMEM on failure.
 */
762
int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
M
Matt Porter 已提交
763 764
{
	int i, rc = 0;
765
	struct rio_priv *priv = mport->priv;
M
Matt Porter 已提交
766 767 768 769 770 771 772 773

	if ((entries < RIO_MIN_RX_RING_SIZE) ||
	    (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
		rc = -EINVAL;
		goto out;
	}

	/* Initialize client buffer ring */
774 775 776 777 778
	priv->msg_rx_ring.dev_id = dev_id;
	priv->msg_rx_ring.size = entries;
	priv->msg_rx_ring.rx_slot = 0;
	for (i = 0; i < priv->msg_rx_ring.size; i++)
		priv->msg_rx_ring.virt_buffer[i] = NULL;
M
Matt Porter 已提交
779 780

	/* Initialize inbound message ring */
781
	priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
782 783 784
				priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
				&priv->msg_rx_ring.phys, GFP_KERNEL);
	if (!priv->msg_rx_ring.virt) {
M
Matt Porter 已提交
785 786 787 788 789
		rc = -ENOMEM;
		goto out;
	}

	/* Point dequeue/enqueue pointers at first entry in ring */
790 791
	out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
	out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
M
Matt Porter 已提交
792 793

	/* Clear interrupt status */
794
	out_be32(&priv->msg_regs->isr, 0x00000091);
M
Matt Porter 已提交
795 796

	/* Hook up inbound message handler */
797 798 799
	rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
			 "msg_rx", (void *)mport);
	if (rc < 0) {
800
		dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
801 802
				  priv->msg_tx_ring.virt_buffer[i],
				  priv->msg_tx_ring.phys_buffer[i]);
M
Matt Porter 已提交
803 804 805 806 807 808 809 810 811 812
		goto out;
	}

	/*
	 * Configure inbound message unit:
	 *      Snooping
	 *      4KB max message size
	 *      Unmask all interrupt sources
	 *      Disable
	 */
813
	out_be32(&priv->msg_regs->imr, 0x001b0060);
M
Matt Porter 已提交
814 815

	/* Set number of queue entries */
816
	setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
M
Matt Porter 已提交
817 818

	/* Now enable the unit */
819
	setbits32(&priv->msg_regs->imr, 0x1);
M
Matt Porter 已提交
820 821 822 823 824 825 826 827 828 829 830 831 832 833 834

      out:
	return rc;
}

/**
 * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
 * @mport: Master port implementing the inbound message unit
 * @mbox: Mailbox to close
 *
 * Disables the inbound message unit, free all buffers, and
 * frees the inbound message interrupt.
 */
void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
{
835
	struct rio_priv *priv = mport->priv;
M
Matt Porter 已提交
836
	/* Disable inbound message unit */
837
	out_be32(&priv->msg_regs->imr, 0);
M
Matt Porter 已提交
838 839

	/* Free ring */
840
	dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
841
			  priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
M
Matt Porter 已提交
842 843

	/* Free interrupt */
844
	free_irq(IRQ_RIO_RX(mport), (void *)mport);
M
Matt Porter 已提交
845 846 847 848 849 850 851 852 853 854 855 856 857 858
}

/**
 * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
 * @mport: Master port implementing the inbound message unit
 * @mbox: Inbound mailbox number
 * @buf: Buffer to add to inbound queue
 *
 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
 * %0 on success or %-EINVAL on failure.
 */
int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
{
	int rc = 0;
859
	struct rio_priv *priv = mport->priv;
M
Matt Porter 已提交
860 861

	pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
862
		 priv->msg_rx_ring.rx_slot);
M
Matt Porter 已提交
863

864
	if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
M
Matt Porter 已提交
865 866
		printk(KERN_ERR
		       "RIO: error adding inbound buffer %d, buffer exists\n",
867
		       priv->msg_rx_ring.rx_slot);
M
Matt Porter 已提交
868 869 870 871
		rc = -EINVAL;
		goto out;
	}

872 873 874
	priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
	if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
		priv->msg_rx_ring.rx_slot = 0;
M
Matt Porter 已提交
875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891

      out:
	return rc;
}

EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);

/**
 * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
 * @mport: Master port implementing the inbound message unit
 * @mbox: Inbound mailbox number
 *
 * Gets the next available inbound message from the inbound message queue.
 * A pointer to the message is returned on success or NULL on failure.
 */
void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
{
892
	struct rio_priv *priv = mport->priv;
M
Matt Porter 已提交
893 894 895 896
	u32 phys_buf, virt_buf;
	void *buf = NULL;
	int buf_idx;

897
	phys_buf = in_be32(&priv->msg_regs->ifqdpar);
M
Matt Porter 已提交
898 899

	/* If no more messages, then bail out */
900
	if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
M
Matt Porter 已提交
901 902
		goto out2;

903 904 905 906
	virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf
						- priv->msg_rx_ring.phys);
	buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
	buf = priv->msg_rx_ring.virt_buffer[buf_idx];
M
Matt Porter 已提交
907 908 909 910 911 912 913 914 915 916 917

	if (!buf) {
		printk(KERN_ERR
		       "RIO: inbound message copy failed, no buffers\n");
		goto out1;
	}

	/* Copy max message size, caller is expected to allocate that big */
	memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);

	/* Clear the available buffer */
918
	priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
M
Matt Porter 已提交
919 920

      out1:
921
	setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
M
Matt Porter 已提交
922 923 924 925 926 927 928 929

      out2:
	return buf;
}

EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);

/**
930
 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
M
Matt Porter 已提交
931 932 933 934 935 936 937
 * @irq: Linux interrupt number
 * @dev_instance: Pointer to interrupt-specific data
 *
 * Handles doorbell interrupts. Parses a list of registered
 * doorbell event handlers and executes a matching event handler.
 */
static irqreturn_t
938
fsl_rio_dbell_handler(int irq, void *dev_instance)
M
Matt Porter 已提交
939 940 941
{
	int dsr;
	struct rio_mport *port = (struct rio_mport *)dev_instance;
942
	struct rio_priv *priv = port->priv;
M
Matt Porter 已提交
943

944
	dsr = in_be32(&priv->msg_regs->dsr);
M
Matt Porter 已提交
945 946 947

	if (dsr & DOORBELL_DSR_TE) {
		pr_info("RIO: doorbell reception error\n");
948
		out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
M
Matt Porter 已提交
949 950 951 952 953
		goto out;
	}

	if (dsr & DOORBELL_DSR_QFI) {
		pr_info("RIO: doorbell queue full\n");
954
		out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
M
Matt Porter 已提交
955 956 957 958 959 960
		goto out;
	}

	/* XXX Need to check/dispatch until queue empty */
	if (dsr & DOORBELL_DSR_DIQI) {
		u32 dmsg =
961 962
		    (u32) priv->dbell_ring.virt +
		    (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
M
Matt Porter 已提交
963 964 965 966 967 968 969 970 971 972 973 974 975 976 977
		struct rio_dbell *dbell;
		int found = 0;

		pr_debug
		    ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
		     DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));

		list_for_each_entry(dbell, &port->dbells, node) {
			if ((dbell->res->start <= DBELL_INF(dmsg)) &&
			    (dbell->res->end >= DBELL_INF(dmsg))) {
				found = 1;
				break;
			}
		}
		if (found) {
978
			dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
M
Matt Porter 已提交
979 980 981 982 983 984
				    DBELL_INF(dmsg));
		} else {
			pr_debug
			    ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
			     DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
		}
985 986
		setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
		out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
M
Matt Porter 已提交
987 988 989 990 991 992 993
	}

      out:
	return IRQ_HANDLED;
}

/**
994
 * fsl_rio_doorbell_init - MPC85xx doorbell interface init
M
Matt Porter 已提交
995 996 997
 * @mport: Master port implementing the inbound doorbell unit
 *
 * Initializes doorbell unit hardware and inbound DMA buffer
998
 * ring. Called from fsl_rio_setup(). Returns %0 on success
M
Matt Porter 已提交
999 1000
 * or %-ENOMEM on failure.
 */
1001
static int fsl_rio_doorbell_init(struct rio_mport *mport)
M
Matt Porter 已提交
1002
{
1003
	struct rio_priv *priv = mport->priv;
M
Matt Porter 已提交
1004 1005 1006
	int rc = 0;

	/* Map outbound doorbell window immediately after maintenance window */
1007 1008 1009
	priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
			    RIO_DBELL_WIN_SIZE);
	if (!priv->dbell_win) {
M
Matt Porter 已提交
1010 1011 1012 1013 1014 1015 1016
		printk(KERN_ERR
		       "RIO: unable to map outbound doorbell window\n");
		rc = -ENOMEM;
		goto out;
	}

	/* Initialize inbound doorbells */
1017
	priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 *
1018 1019
		    DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL);
	if (!priv->dbell_ring.virt) {
M
Matt Porter 已提交
1020 1021
		printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
		rc = -ENOMEM;
1022
		iounmap(priv->dbell_win);
M
Matt Porter 已提交
1023 1024 1025 1026
		goto out;
	}

	/* Point dequeue/enqueue pointers at first entry in ring */
1027 1028
	out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
	out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
M
Matt Porter 已提交
1029 1030

	/* Clear interrupt status */
1031
	out_be32(&priv->msg_regs->dsr, 0x00000091);
M
Matt Porter 已提交
1032 1033

	/* Hook up doorbell handler */
1034 1035 1036 1037
	rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
			 "dbell_rx", (void *)mport);
	if (rc < 0) {
		iounmap(priv->dbell_win);
1038
		dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE,
1039
				  priv->dbell_ring.virt, priv->dbell_ring.phys);
M
Matt Porter 已提交
1040 1041 1042 1043 1044 1045
		printk(KERN_ERR
		       "MPC85xx RIO: unable to request inbound doorbell irq");
		goto out;
	}

	/* Configure doorbells for snooping, 512 entries, and enable */
1046
	out_be32(&priv->msg_regs->dmr, 0x00108161);
M
Matt Porter 已提交
1047 1048 1049 1050 1051

      out:
	return rc;
}

1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268
/**
 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
 * @irq: Linux interrupt number
 * @dev_instance: Pointer to interrupt-specific data
 *
 * Handles port write interrupts. Parses a list of registered
 * port write event handlers and executes a matching event handler.
 */
static irqreturn_t
fsl_rio_port_write_handler(int irq, void *dev_instance)
{
	u32 ipwmr, ipwsr;
	struct rio_mport *port = (struct rio_mport *)dev_instance;
	struct rio_priv *priv = port->priv;
	u32 epwisr, tmp;

	ipwmr = in_be32(&priv->msg_regs->pwmr);
	ipwsr = in_be32(&priv->msg_regs->pwsr);

	epwisr = in_be32(priv->regs_win + RIO_EPWISR);
	if (epwisr & 0x80000000) {
		tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
		pr_info("RIO_LTLEDCSR = 0x%x\n", tmp);
		out_be32(priv->regs_win + RIO_LTLEDCSR, 0);
	}

	if (!(epwisr & 0x00000001))
		return IRQ_HANDLED;

#ifdef DEBUG_PW
	pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
	if (ipwsr & RIO_IPWSR_QF)
		pr_debug(" QF");
	if (ipwsr & RIO_IPWSR_TE)
		pr_debug(" TE");
	if (ipwsr & RIO_IPWSR_QFI)
		pr_debug(" QFI");
	if (ipwsr & RIO_IPWSR_PWD)
		pr_debug(" PWD");
	if (ipwsr & RIO_IPWSR_PWB)
		pr_debug(" PWB");
	pr_debug(" )\n");
#endif
	out_be32(&priv->msg_regs->pwsr,
		 ipwsr & (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));

	if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
		priv->port_write_msg.err_count++;
		pr_info("RIO: Port-Write Transaction Err (%d)\n",
			 priv->port_write_msg.err_count);
	}
	if (ipwsr & RIO_IPWSR_PWD) {
		priv->port_write_msg.discard_count++;
		pr_info("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
			 priv->port_write_msg.discard_count);
	}

	/* Schedule deferred processing if PW was received */
	if (ipwsr & RIO_IPWSR_QFI) {
		/* Save PW message (if there is room in FIFO),
		 * otherwise discard it.
		 */
		if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) {
			priv->port_write_msg.msg_count++;
			kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt,
				 RIO_PW_MSG_SIZE);
		} else {
			priv->port_write_msg.discard_count++;
			pr_info("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
				 priv->port_write_msg.discard_count);
		}
		schedule_work(&priv->pw_work);
	}

	/* Issue Clear Queue command. This allows another
	 * port-write to be received.
	 */
	out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ);

	return IRQ_HANDLED;
}

static void fsl_pw_dpc(struct work_struct *work)
{
	struct rio_priv *priv = container_of(work, struct rio_priv, pw_work);
	unsigned long flags;
	u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)];

	/*
	 * Process port-write messages
	 */
	spin_lock_irqsave(&priv->pw_fifo_lock, flags);
	while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer,
			 RIO_PW_MSG_SIZE)) {
		/* Process one message */
		spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
#ifdef DEBUG_PW
		{
		u32 i;
		pr_debug("%s : Port-Write Message:", __func__);
		for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
			if ((i%4) == 0)
				pr_debug("\n0x%02x: 0x%08x", i*4,
					 msg_buffer[i]);
			else
				pr_debug(" 0x%08x", msg_buffer[i]);
		}
		pr_debug("\n");
		}
#endif
		/* Pass the port-write message to RIO core for processing */
		rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
		spin_lock_irqsave(&priv->pw_fifo_lock, flags);
	}
	spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
}

/**
 * fsl_rio_pw_enable - enable/disable port-write interface init
 * @mport: Master port implementing the port write unit
 * @enable:    1=enable; 0=disable port-write message handling
 */
static int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
{
	struct rio_priv *priv = mport->priv;
	u32 rval;

	rval = in_be32(&priv->msg_regs->pwmr);

	if (enable)
		rval |= RIO_IPWMR_PWE;
	else
		rval &= ~RIO_IPWMR_PWE;

	out_be32(&priv->msg_regs->pwmr, rval);

	return 0;
}

/**
 * fsl_rio_port_write_init - MPC85xx port write interface init
 * @mport: Master port implementing the port write unit
 *
 * Initializes port write unit hardware and DMA buffer
 * ring. Called from fsl_rio_setup(). Returns %0 on success
 * or %-ENOMEM on failure.
 */
static int fsl_rio_port_write_init(struct rio_mport *mport)
{
	struct rio_priv *priv = mport->priv;
	int rc = 0;

	/* Following configurations require a disabled port write controller */
	out_be32(&priv->msg_regs->pwmr,
		 in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE);

	/* Initialize port write */
	priv->port_write_msg.virt = dma_alloc_coherent(priv->dev,
					RIO_PW_MSG_SIZE,
					&priv->port_write_msg.phys, GFP_KERNEL);
	if (!priv->port_write_msg.virt) {
		pr_err("RIO: unable allocate port write queue\n");
		return -ENOMEM;
	}

	priv->port_write_msg.err_count = 0;
	priv->port_write_msg.discard_count = 0;

	/* Point dequeue/enqueue pointers at first entry */
	out_be32(&priv->msg_regs->epwqbar, 0);
	out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys);

	pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
		 in_be32(&priv->msg_regs->epwqbar),
		 in_be32(&priv->msg_regs->pwqbar));

	/* Clear interrupt status IPWSR */
	out_be32(&priv->msg_regs->pwsr,
		 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));

	/* Configure port write contoller for snooping enable all reporting,
	   clear queue full */
	out_be32(&priv->msg_regs->pwmr,
		 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);


	/* Hook up port-write handler */
	rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 0,
			 "port-write", (void *)mport);
	if (rc < 0) {
		pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
		goto err_out;
	}

	INIT_WORK(&priv->pw_work, fsl_pw_dpc);
	spin_lock_init(&priv->pw_fifo_lock);
	if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
		pr_err("FIFO allocation failed\n");
		rc = -ENOMEM;
		goto err_out_irq;
	}

	pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
		 in_be32(&priv->msg_regs->pwmr),
		 in_be32(&priv->msg_regs->pwsr));

	return rc;

err_out_irq:
	free_irq(IRQ_RIO_PW(mport), (void *)mport);
err_out:
	dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE,
			  priv->port_write_msg.virt,
			  priv->port_write_msg.phys);
	return rc;
}

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1269 1270
static char *cmdline = NULL;

1271
static int fsl_rio_get_hdid(int index)
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1272 1273 1274 1275 1276 1277 1278 1279
{
	/* XXX Need to parse multiple entries in some format */
	if (!cmdline)
		return -1;

	return simple_strtol(cmdline, NULL, 0);
}

1280
static int fsl_rio_get_cmdline(char *s)
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Matt Porter 已提交
1281 1282 1283 1284 1285 1286 1287 1288
{
	if (!s)
		return 0;

	cmdline = s;
	return 1;
}

1289
__setup("riohdid=", fsl_rio_get_cmdline);
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1290

1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304
static inline void fsl_rio_info(struct device *dev, u32 ccsr)
{
	const char *str;
	if (ccsr & 1) {
		/* Serial phy */
		switch (ccsr >> 30) {
		case 0:
			str = "1";
			break;
		case 1:
			str = "4";
			break;
		default:
			str = "Unknown";
1305
			break;
1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332
		}
		dev_info(dev, "Hardware port width: %s\n", str);

		switch ((ccsr >> 27) & 7) {
		case 0:
			str = "Single-lane 0";
			break;
		case 1:
			str = "Single-lane 2";
			break;
		case 2:
			str = "Four-lane";
			break;
		default:
			str = "Unknown";
			break;
		}
		dev_info(dev, "Training connection status: %s\n", str);
	} else {
		/* Parallel phy */
		if (!(ccsr & 0x80000000))
			dev_info(dev, "Output port operating in 8-bit mode\n");
		if (!(ccsr & 0x08000000))
			dev_info(dev, "Input port operating in 8-bit mode\n");
	}
}

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1333
/**
1334 1335
 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
 * @dev: of_device pointer
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1336 1337 1338 1339 1340
 *
 * Initializes MPC85xx RapidIO hardware interface, configures
 * master port with system-specific info, and registers the
 * master port with the RapidIO subsystem.
 */
1341
int fsl_rio_setup(struct of_device *dev)
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1342 1343 1344
{
	struct rio_ops *ops;
	struct rio_mport *port;
1345 1346 1347 1348 1349
	struct rio_priv *priv;
	int rc = 0;
	const u32 *dt_range, *cell;
	struct resource regs;
	int rlen;
1350
	u32 ccsr;
1351 1352 1353
	u64 law_start, law_size;
	int paw, aw, sw;

1354
	if (!dev->dev.of_node) {
1355 1356 1357 1358
		dev_err(&dev->dev, "Device OF-Node is NULL");
		return -EFAULT;
	}

1359
	rc = of_address_to_resource(dev->dev.of_node, 0, &regs);
1360 1361
	if (rc) {
		dev_err(&dev->dev, "Can't get %s property 'reg'\n",
1362
				dev->dev.of_node->full_name);
1363 1364
		return -EFAULT;
	}
1365
	dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name);
1366
	dev_info(&dev->dev, "Regs: %pR\n", &regs);
1367

1368
	dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen);
1369 1370
	if (!dt_range) {
		dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
1371
				dev->dev.of_node->full_name);
1372 1373 1374 1375
		return -EFAULT;
	}

	/* Get node address wide */
1376
	cell = of_get_property(dev->dev.of_node, "#address-cells", NULL);
1377 1378 1379
	if (cell)
		aw = *cell;
	else
1380
		aw = of_n_addr_cells(dev->dev.of_node);
1381
	/* Get node size wide */
1382
	cell = of_get_property(dev->dev.of_node, "#size-cells", NULL);
1383 1384 1385
	if (cell)
		sw = *cell;
	else
1386
		sw = of_n_size_cells(dev->dev.of_node);
1387
	/* Get parent address wide wide */
1388
	paw = of_n_addr_cells(dev->dev.of_node);
1389 1390 1391 1392 1393 1394

	law_start = of_read_number(dt_range + aw, paw);
	law_size = of_read_number(dt_range + aw + paw, sw);

	dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n",
			law_start, law_size);
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1395

1396
	ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
1397 1398 1399 1400
	if (!ops) {
		rc = -ENOMEM;
		goto err_ops;
	}
1401 1402 1403 1404 1405
	ops->lcread = fsl_local_config_read;
	ops->lcwrite = fsl_local_config_write;
	ops->cread = fsl_rio_config_read;
	ops->cwrite = fsl_rio_config_write;
	ops->dsend = fsl_rio_doorbell_send;
1406
	ops->pwenable = fsl_rio_pw_enable;
M
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1407

1408
	port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
1409 1410 1411 1412
	if (!port) {
		rc = -ENOMEM;
		goto err_port;
	}
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	port->id = 0;
	port->index = 0;
1415 1416 1417 1418 1419

	priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
	if (!priv) {
		printk(KERN_ERR "Can't alloc memory for 'priv'\n");
		rc = -ENOMEM;
1420
		goto err_priv;
1421 1422
	}

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1423 1424
	INIT_LIST_HEAD(&port->dbells);
	port->iores.start = law_start;
1425
	port->iores.end = law_start + law_size - 1;
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1426
	port->iores.flags = IORESOURCE_MEM;
1427
	port->iores.name = "rio_io_win";
M
Matt Porter 已提交
1428

1429
	priv->pwirq   = irq_of_parse_and_map(dev->node, 0);
1430 1431 1432
	priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2);
	priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3);
	priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4);
1433 1434
	dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n",
		 priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq);
1435

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Matt Porter 已提交
1436 1437 1438 1439 1440
	rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
	rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
	rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
	strcpy(port->name, "RIO0 mport");

1441 1442
	priv->dev = &dev->dev;

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1443
	port->ops = ops;
1444
	port->host_deviceid = fsl_rio_get_hdid(port->id);
M
Matt Porter 已提交
1445

1446
	port->priv = priv;
M
Matt Porter 已提交
1447 1448
	rio_register_mport(port);

1449
	priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1);
1450
	rio_regs_win = priv->regs_win;
1451

1452 1453 1454 1455 1456 1457 1458
	/* Probe the master port phy type */
	ccsr = in_be32(priv->regs_win + RIO_CCSR);
	port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
	dev_info(&dev->dev, "RapidIO PHY type: %s\n",
			(port->phy_type == RIO_PHY_PARALLEL) ? "parallel" :
			((port->phy_type == RIO_PHY_SERIAL) ? "serial" :
			 "unknown"));
1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487
	/* Checking the port training status */
	if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
		dev_err(&dev->dev, "Port is not ready. "
				   "Try to restart connection...\n");
		switch (port->phy_type) {
		case RIO_PHY_SERIAL:
			/* Disable ports */
			out_be32(priv->regs_win + RIO_CCSR, 0);
			/* Set 1x lane */
			setbits32(priv->regs_win + RIO_CCSR, 0x02000000);
			/* Enable ports */
			setbits32(priv->regs_win + RIO_CCSR, 0x00600000);
			break;
		case RIO_PHY_PARALLEL:
			/* Disable ports */
			out_be32(priv->regs_win + RIO_CCSR, 0x22000000);
			/* Enable ports */
			out_be32(priv->regs_win + RIO_CCSR, 0x44000000);
			break;
		}
		msleep(100);
		if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
			dev_err(&dev->dev, "Port restart failed.\n");
			rc = -ENOLINK;
			goto err;
		}
		dev_info(&dev->dev, "Port restart success!\n");
	}
	fsl_rio_info(&dev->dev, ccsr);
1488

1489 1490 1491 1492 1493
	port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
					& RIO_PEF_CTLS) >> 4;
	dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
			port->sys_size ? 65536 : 256);

1494 1495 1496 1497
	priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
					+ RIO_ATMU_REGS_OFFSET);
	priv->maint_atmu_regs = priv->atmu_regs + 1;
	priv->dbell_atmu_regs = priv->atmu_regs + 2;
1498 1499 1500 1501 1502 1503 1504
	priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win +
				((port->phy_type == RIO_PHY_SERIAL) ?
				RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET));

	/* Set to receive any dist ID for serial RapidIO controller. */
	if (port->phy_type == RIO_PHY_SERIAL)
		out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA);
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1505 1506

	/* Configure maintenance transaction window */
1507
	out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12);
1508 1509
	out_be32(&priv->maint_atmu_regs->rowar,
		 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
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Matt Porter 已提交
1510

1511
	priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
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Matt Porter 已提交
1512 1513

	/* Configure outbound doorbell window */
1514 1515 1516
	out_be32(&priv->dbell_atmu_regs->rowbar,
			(law_start + RIO_MAINT_WIN_SIZE) >> 12);
	out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b);	/* 4k */
1517
	fsl_rio_doorbell_init(port);
1518
	fsl_rio_port_write_init(port);
1519

1520 1521 1522 1523 1524
	saved_mcheck_exception = ppc_md.machine_check_exception;
	ppc_md.machine_check_exception = fsl_rio_mcheck_exception;
	/* Ensure that RFXE is set */
	mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | 0x20000));

1525
	return 0;
1526
err:
1527
	iounmap(priv->regs_win);
1528
	kfree(priv);
1529
err_priv:
1530
	kfree(port);
1531 1532 1533
err_port:
	kfree(ops);
err_ops:
1534
	return rc;
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Matt Porter 已提交
1535
}
1536 1537 1538 1539 1540 1541 1542 1543

/* The probe function for RapidIO peer-to-peer network.
 */
static int __devinit fsl_of_rio_rpn_probe(struct of_device *dev,
				     const struct of_device_id *match)
{
	int rc;
	printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
1544
			dev->dev.of_node->full_name);
1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563

	rc = fsl_rio_setup(dev);
	if (rc)
		goto out;

	/* Enumerate all registered ports */
	rc = rio_init_mports();
out:
	return rc;
};

static const struct of_device_id fsl_of_rio_rpn_ids[] = {
	{
		.compatible = "fsl,rapidio-delta",
	},
	{},
};

static struct of_platform_driver fsl_of_rio_rpn_driver = {
1564 1565 1566 1567 1568
	.driver = {
		.name = "fsl-of-rio",
		.owner = THIS_MODULE,
		.of_match_table = fsl_of_rio_rpn_ids,
	},
1569 1570 1571 1572 1573 1574 1575 1576 1577
	.probe = fsl_of_rio_rpn_probe,
};

static __init int fsl_of_rio_rpn_init(void)
{
	return of_register_platform_driver(&fsl_of_rio_rpn_driver);
}

subsys_initcall(fsl_of_rio_rpn_init);