atmel_nand.c 62.3 KB
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/*
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 *  Copyright © 2003 Rick Bronson
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 *
 *  Derived from drivers/mtd/nand/autcpu12.c
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 *	 Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
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 *
 *  Derived from drivers/mtd/spia.c
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 *	 Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
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 *
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 *
 *  Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
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 *     Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
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 *
 *     Derived from Das U-Boot source code
 *     		(u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
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 *     © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
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 *
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 *  Add Programmable Multibit ECC support for various AT91 SoC
 *     © Copyright 2012 ATMEL, Hong Xu
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 *
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 *  Add Nand Flash Controller support for SAMA5 SoC
 *     © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
 *
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 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/of_mtd.h>
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#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>

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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/platform_data/atmel.h>
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static int use_dma = 1;
module_param(use_dma, int, 0);

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static int on_flash_bbt = 0;
module_param(on_flash_bbt, int, 0);

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/* Register access macros */
#define ecc_readl(add, reg)				\
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	__raw_readl(add + ATMEL_ECC_##reg)
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#define ecc_writel(add, reg, value)			\
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	__raw_writel((value), add + ATMEL_ECC_##reg)
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#include "atmel_nand_ecc.h"	/* Hardware ECC registers */
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#include "atmel_nand_nfc.h"	/* Nand Flash Controller definition */
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struct atmel_nand_caps {
	bool pmecc_correct_erase_page;
};

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/* oob layout for large page size
 * bad block info is on bytes 0 and 1
 * the bytes have to be consecutives to avoid
 * several NAND_CMD_RNDOUT during read
 */
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static struct nand_ecclayout atmel_oobinfo_large = {
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	.eccbytes = 4,
	.eccpos = {60, 61, 62, 63},
	.oobfree = {
		{2, 58}
	},
};

/* oob layout for small page size
 * bad block info is on bytes 4 and 5
 * the bytes have to be consecutives to avoid
 * several NAND_CMD_RNDOUT during read
 */
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static struct nand_ecclayout atmel_oobinfo_small = {
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	.eccbytes = 4,
	.eccpos = {0, 1, 2, 3},
	.oobfree = {
		{6, 10}
	},
};

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struct atmel_nfc {
	void __iomem		*base_cmd_regs;
	void __iomem		*hsmc_regs;
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	void			*sram_bank0;
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	dma_addr_t		sram_bank0_phys;
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	bool			use_nfc_sram;
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	bool			write_by_sram;
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	struct clk		*clk;

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	bool			is_initialized;
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	struct completion	comp_ready;
	struct completion	comp_cmd_done;
	struct completion	comp_xfer_done;
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	/* Point to the sram bank which include readed data via NFC */
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	void			*data_in_sram;
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	bool			will_write_sram;
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};
static struct atmel_nfc	nand_nfc;

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struct atmel_nand_host {
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	struct nand_chip	nand_chip;
	void __iomem		*io_base;
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	dma_addr_t		io_phys;
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	struct atmel_nand_data	board;
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	struct device		*dev;
	void __iomem		*ecc;
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	struct completion	comp;
	struct dma_chan		*dma_chan;
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	struct atmel_nfc	*nfc;

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	const struct atmel_nand_caps	*caps;
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	bool			has_pmecc;
	u8			pmecc_corr_cap;
	u16			pmecc_sector_size;
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	bool			has_no_lookup_table;
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	u32			pmecc_lookup_table_offset;
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	u32			pmecc_lookup_table_offset_512;
	u32			pmecc_lookup_table_offset_1024;
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	int			pmecc_degree;	/* Degree of remainders */
	int			pmecc_cw_len;	/* Length of codeword */

	void __iomem		*pmerrloc_base;
	void __iomem		*pmecc_rom_base;

	/* lookup table for alpha_to and index_of */
	void __iomem		*pmecc_alpha_to;
	void __iomem		*pmecc_index_of;

	/* data for pmecc computation */
	int16_t			*pmecc_partial_syn;
	int16_t			*pmecc_si;
	int16_t			*pmecc_smu;	/* Sigma table */
	int16_t			*pmecc_lmu;	/* polynomal order */
	int			*pmecc_mu;
	int			*pmecc_dmu;
	int			*pmecc_delta;
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};

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static struct nand_ecclayout atmel_pmecc_oobinfo;

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/*
 * Enable NAND.
 */
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static void atmel_nand_enable(struct atmel_nand_host *host)
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{
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	if (gpio_is_valid(host->board.enable_pin))
		gpio_set_value(host->board.enable_pin, 0);
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}

/*
 * Disable NAND.
 */
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static void atmel_nand_disable(struct atmel_nand_host *host)
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{
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	if (gpio_is_valid(host->board.enable_pin))
		gpio_set_value(host->board.enable_pin, 1);
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}

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/*
 * Hardware specific access to control-lines
 */
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static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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	struct nand_chip *nand_chip = mtd_to_nand(mtd);
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	struct atmel_nand_host *host = nand_chip->priv;
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	if (ctrl & NAND_CTRL_CHANGE) {
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		if (ctrl & NAND_NCE)
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			atmel_nand_enable(host);
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		else
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			atmel_nand_disable(host);
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	}
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	if (cmd == NAND_CMD_NONE)
		return;

	if (ctrl & NAND_CLE)
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		writeb(cmd, host->io_base + (1 << host->board.cle));
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	else
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		writeb(cmd, host->io_base + (1 << host->board.ale));
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}

/*
 * Read the Device Ready pin.
 */
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static int atmel_nand_device_ready(struct mtd_info *mtd)
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{
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	struct nand_chip *nand_chip = mtd_to_nand(mtd);
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	struct atmel_nand_host *host = nand_chip->priv;
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	return gpio_get_value(host->board.rdy_pin) ^
                !!host->board.rdy_pin_active_low;
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}

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/* Set up for hardware ready pin and enable pin. */
static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	struct atmel_nand_host *host = chip->priv;
	int res = 0;

	if (gpio_is_valid(host->board.rdy_pin)) {
		res = devm_gpio_request(host->dev,
				host->board.rdy_pin, "nand_rdy");
		if (res < 0) {
			dev_err(host->dev,
				"can't request rdy gpio %d\n",
				host->board.rdy_pin);
			return res;
		}

		res = gpio_direction_input(host->board.rdy_pin);
		if (res < 0) {
			dev_err(host->dev,
				"can't request input direction rdy gpio %d\n",
				host->board.rdy_pin);
			return res;
		}

		chip->dev_ready = atmel_nand_device_ready;
	}

	if (gpio_is_valid(host->board.enable_pin)) {
		res = devm_gpio_request(host->dev,
				host->board.enable_pin, "nand_enable");
		if (res < 0) {
			dev_err(host->dev,
				"can't request enable gpio %d\n",
				host->board.enable_pin);
			return res;
		}

		res = gpio_direction_output(host->board.enable_pin, 1);
		if (res < 0) {
			dev_err(host->dev,
				"can't request output direction enable gpio %d\n",
				host->board.enable_pin);
			return res;
		}
	}

	return res;
}

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/*
 * Minimal-overhead PIO for data access.
 */
static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
{
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	struct nand_chip	*nand_chip = mtd_to_nand(mtd);
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	struct atmel_nand_host *host = nand_chip->priv;
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	if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
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		memcpy(buf, host->nfc->data_in_sram, len);
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		host->nfc->data_in_sram += len;
	} else {
		__raw_readsb(nand_chip->IO_ADDR_R, buf, len);
	}
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}

static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
{
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	struct nand_chip	*nand_chip = mtd_to_nand(mtd);
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	struct atmel_nand_host *host = nand_chip->priv;
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	if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
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		memcpy(buf, host->nfc->data_in_sram, len);
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		host->nfc->data_in_sram += len;
	} else {
		__raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
	}
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}

static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
{
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	struct nand_chip	*nand_chip = mtd_to_nand(mtd);
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	__raw_writesb(nand_chip->IO_ADDR_W, buf, len);
}

static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
{
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	struct nand_chip	*nand_chip = mtd_to_nand(mtd);
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	__raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
}

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static void dma_complete_func(void *completion)
{
	complete(completion);
}

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static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank)
{
	/* NFC only has two banks. Must be 0 or 1 */
	if (bank > 1)
		return -EINVAL;

	if (bank) {
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		struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);

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		/* Only for a 2k-page or lower flash, NFC can handle 2 banks */
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		if (mtd->writesize > 2048)
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			return -EINVAL;
		nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1);
	} else {
		nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0);
	}

	return 0;
}

static uint nfc_get_sram_off(struct atmel_nand_host *host)
{
	if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
		return NFC_SRAM_BANK1_OFFSET;
	else
		return 0;
}

static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host)
{
	if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
		return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET;
	else
		return host->nfc->sram_bank0_phys;
}

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static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
			       int is_read)
{
	struct dma_device *dma_dev;
	enum dma_ctrl_flags flags;
	dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
	struct dma_async_tx_descriptor *tx = NULL;
	dma_cookie_t cookie;
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	struct atmel_nand_host *host = chip->priv;
	void *p = buf;
	int err = -EIO;
	enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
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	struct atmel_nfc *nfc = host->nfc;
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	if (buf >= high_memory)
		goto err_buf;
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	dma_dev = host->dma_chan->device;

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	flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
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	phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
	if (dma_mapping_error(dma_dev->dev, phys_addr)) {
		dev_err(host->dev, "Failed to dma_map_single\n");
		goto err_buf;
	}

	if (is_read) {
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		if (nfc && nfc->data_in_sram)
			dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram
				- (nfc->sram_bank0 + nfc_get_sram_off(host)));
		else
			dma_src_addr = host->io_phys;

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		dma_dst_addr = phys_addr;
	} else {
		dma_src_addr = phys_addr;
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		if (nfc && nfc->write_by_sram)
			dma_dst_addr = nfc_sram_phys(host);
		else
			dma_dst_addr = host->io_phys;
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	}

	tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
					     dma_src_addr, len, flags);
	if (!tx) {
		dev_err(host->dev, "Failed to prepare DMA memcpy\n");
		goto err_dma;
	}

	init_completion(&host->comp);
	tx->callback = dma_complete_func;
	tx->callback_param = &host->comp;

	cookie = tx->tx_submit(tx);
	if (dma_submit_error(cookie)) {
		dev_err(host->dev, "Failed to do DMA tx_submit\n");
		goto err_dma;
	}

	dma_async_issue_pending(host->dma_chan);
	wait_for_completion(&host->comp);

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	if (is_read && nfc && nfc->data_in_sram)
		/* After read data from SRAM, need to increase the position */
		nfc->data_in_sram += len;

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	err = 0;

err_dma:
	dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
err_buf:
	if (err != 0)
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		dev_dbg(host->dev, "Fall back to CPU I/O\n");
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	return err;
}

static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	struct atmel_nand_host *host = chip->priv;
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	if (use_dma && len > mtd->oobsize)
		/* only use DMA for bigger than oob size: better performances */
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		if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
			return;

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	if (host->board.bus_width_16)
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		atmel_read_buf16(mtd, buf, len);
	else
		atmel_read_buf8(mtd, buf, len);
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}

static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	struct atmel_nand_host *host = chip->priv;
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	if (use_dma && len > mtd->oobsize)
		/* only use DMA for bigger than oob size: better performances */
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		if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
			return;

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	if (host->board.bus_width_16)
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		atmel_write_buf16(mtd, buf, len);
	else
		atmel_write_buf8(mtd, buf, len);
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}

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/*
 * Return number of ecc bytes per sector according to sector size and
 * correction capability
 *
 * Following table shows what at91 PMECC supported:
 * Correction Capability	Sector_512_bytes	Sector_1024_bytes
 * =====================	================	=================
 *                2-bits                 4-bytes                  4-bytes
 *                4-bits                 7-bytes                  7-bytes
 *                8-bits                13-bytes                 14-bytes
 *               12-bits                20-bytes                 21-bytes
 *               24-bits                39-bytes                 42-bytes
 */
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static int pmecc_get_ecc_bytes(int cap, int sector_size)
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{
	int m = 12 + sector_size / 512;
	return (m * cap + 7) / 8;
}

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static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
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				    int oobsize, int ecc_len)
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{
	int i;

	layout->eccbytes = ecc_len;

	/* ECC will occupy the last ecc_len bytes continuously */
	for (i = 0; i < ecc_len; i++)
		layout->eccpos[i] = oobsize - ecc_len + i;

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	layout->oobfree[0].offset = PMECC_OOB_RESERVED_BYTES;
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	layout->oobfree[0].length =
		oobsize - ecc_len - layout->oobfree[0].offset;
}

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static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
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{
	int table_size;

	table_size = host->pmecc_sector_size == 512 ?
		PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;

	return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
			table_size * sizeof(int16_t);
}

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static int pmecc_data_alloc(struct atmel_nand_host *host)
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{
	const int cap = host->pmecc_corr_cap;
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	int size;

	size = (2 * cap + 1) * sizeof(int16_t);
	host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL);
	host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL);
	host->pmecc_lmu = devm_kzalloc(host->dev,
			(cap + 1) * sizeof(int16_t), GFP_KERNEL);
	host->pmecc_smu = devm_kzalloc(host->dev,
			(cap + 2) * size, GFP_KERNEL);

	size = (cap + 1) * sizeof(int);
	host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL);
	host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL);
	host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL);

	if (!host->pmecc_partial_syn ||
		!host->pmecc_si ||
		!host->pmecc_lmu ||
		!host->pmecc_smu ||
		!host->pmecc_mu ||
		!host->pmecc_dmu ||
		!host->pmecc_delta)
		return -ENOMEM;
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	return 0;
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}

static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
{
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	struct nand_chip *nand_chip = mtd_to_nand(mtd);
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	struct atmel_nand_host *host = nand_chip->priv;
	int i;
	uint32_t value;

	/* Fill odd syndromes */
	for (i = 0; i < host->pmecc_corr_cap; i++) {
		value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
		if (i & 1)
			value >>= 16;
		value &= 0xffff;
		host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
	}
}

static void pmecc_substitute(struct mtd_info *mtd)
{
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	struct nand_chip *nand_chip = mtd_to_nand(mtd);
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	struct atmel_nand_host *host = nand_chip->priv;
	int16_t __iomem *alpha_to = host->pmecc_alpha_to;
	int16_t __iomem *index_of = host->pmecc_index_of;
	int16_t *partial_syn = host->pmecc_partial_syn;
	const int cap = host->pmecc_corr_cap;
	int16_t *si;
	int i, j;

	/* si[] is a table that holds the current syndrome value,
	 * an element of that table belongs to the field
	 */
	si = host->pmecc_si;

	memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));

	/* Computation 2t syndromes based on S(x) */
	/* Odd syndromes */
	for (i = 1; i < 2 * cap; i += 2) {
		for (j = 0; j < host->pmecc_degree; j++) {
			if (partial_syn[i] & ((unsigned short)0x1 << j))
				si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
		}
	}
	/* Even syndrome = (Odd syndrome) ** 2 */
	for (i = 2, j = 1; j <= cap; i = ++j << 1) {
		if (si[j] == 0) {
			si[i] = 0;
		} else {
			int16_t tmp;

			tmp = readw_relaxed(index_of + si[j]);
			tmp = (tmp * 2) % host->pmecc_cw_len;
			si[i] = readw_relaxed(alpha_to + tmp);
		}
	}

	return;
}

static void pmecc_get_sigma(struct mtd_info *mtd)
{
596
	struct nand_chip *nand_chip = mtd_to_nand(mtd);
597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753
	struct atmel_nand_host *host = nand_chip->priv;

	int16_t *lmu = host->pmecc_lmu;
	int16_t *si = host->pmecc_si;
	int *mu = host->pmecc_mu;
	int *dmu = host->pmecc_dmu;	/* Discrepancy */
	int *delta = host->pmecc_delta; /* Delta order */
	int cw_len = host->pmecc_cw_len;
	const int16_t cap = host->pmecc_corr_cap;
	const int num = 2 * cap + 1;
	int16_t __iomem	*index_of = host->pmecc_index_of;
	int16_t __iomem	*alpha_to = host->pmecc_alpha_to;
	int i, j, k;
	uint32_t dmu_0_count, tmp;
	int16_t *smu = host->pmecc_smu;

	/* index of largest delta */
	int ro;
	int largest;
	int diff;

	dmu_0_count = 0;

	/* First Row */

	/* Mu */
	mu[0] = -1;

	memset(smu, 0, sizeof(int16_t) * num);
	smu[0] = 1;

	/* discrepancy set to 1 */
	dmu[0] = 1;
	/* polynom order set to 0 */
	lmu[0] = 0;
	delta[0] = (mu[0] * 2 - lmu[0]) >> 1;

	/* Second Row */

	/* Mu */
	mu[1] = 0;
	/* Sigma(x) set to 1 */
	memset(&smu[num], 0, sizeof(int16_t) * num);
	smu[num] = 1;

	/* discrepancy set to S1 */
	dmu[1] = si[1];

	/* polynom order set to 0 */
	lmu[1] = 0;

	delta[1] = (mu[1] * 2 - lmu[1]) >> 1;

	/* Init the Sigma(x) last row */
	memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);

	for (i = 1; i <= cap; i++) {
		mu[i + 1] = i << 1;
		/* Begin Computing Sigma (Mu+1) and L(mu) */
		/* check if discrepancy is set to 0 */
		if (dmu[i] == 0) {
			dmu_0_count++;

			tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
			if ((cap - (lmu[i] >> 1) - 1) & 0x1)
				tmp += 2;
			else
				tmp += 1;

			if (dmu_0_count == tmp) {
				for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
					smu[(cap + 1) * num + j] =
							smu[i * num + j];

				lmu[cap + 1] = lmu[i];
				return;
			}

			/* copy polynom */
			for (j = 0; j <= lmu[i] >> 1; j++)
				smu[(i + 1) * num + j] = smu[i * num + j];

			/* copy previous polynom order to the next */
			lmu[i + 1] = lmu[i];
		} else {
			ro = 0;
			largest = -1;
			/* find largest delta with dmu != 0 */
			for (j = 0; j < i; j++) {
				if ((dmu[j]) && (delta[j] > largest)) {
					largest = delta[j];
					ro = j;
				}
			}

			/* compute difference */
			diff = (mu[i] - mu[ro]);

			/* Compute degree of the new smu polynomial */
			if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
				lmu[i + 1] = lmu[i];
			else
				lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;

			/* Init smu[i+1] with 0 */
			for (k = 0; k < num; k++)
				smu[(i + 1) * num + k] = 0;

			/* Compute smu[i+1] */
			for (k = 0; k <= lmu[ro] >> 1; k++) {
				int16_t a, b, c;

				if (!(smu[ro * num + k] && dmu[i]))
					continue;
				a = readw_relaxed(index_of + dmu[i]);
				b = readw_relaxed(index_of + dmu[ro]);
				c = readw_relaxed(index_of + smu[ro * num + k]);
				tmp = a + (cw_len - b) + c;
				a = readw_relaxed(alpha_to + tmp % cw_len);
				smu[(i + 1) * num + (k + diff)] = a;
			}

			for (k = 0; k <= lmu[i] >> 1; k++)
				smu[(i + 1) * num + k] ^= smu[i * num + k];
		}

		/* End Computing Sigma (Mu+1) and L(mu) */
		/* In either case compute delta */
		delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;

		/* Do not compute discrepancy for the last iteration */
		if (i >= cap)
			continue;

		for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
			tmp = 2 * (i - 1);
			if (k == 0) {
				dmu[i + 1] = si[tmp + 3];
			} else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
				int16_t a, b, c;
				a = readw_relaxed(index_of +
						smu[(i + 1) * num + k]);
				b = si[2 * (i - 1) + 3 - k];
				c = readw_relaxed(index_of + b);
				tmp = a + c;
				tmp %= cw_len;
				dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
					dmu[i + 1];
			}
		}
	}

	return;
}

static int pmecc_err_location(struct mtd_info *mtd)
{
754
	struct nand_chip *nand_chip = mtd_to_nand(mtd);
755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805
	struct atmel_nand_host *host = nand_chip->priv;
	unsigned long end_time;
	const int cap = host->pmecc_corr_cap;
	const int num = 2 * cap + 1;
	int sector_size = host->pmecc_sector_size;
	int err_nbr = 0;	/* number of error */
	int roots_nbr;		/* number of roots */
	int i;
	uint32_t val;
	int16_t *smu = host->pmecc_smu;

	pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);

	for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
		pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
				      smu[(cap + 1) * num + i]);
		err_nbr++;
	}

	val = (err_nbr - 1) << 16;
	if (sector_size == 1024)
		val |= 1;

	pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
	pmerrloc_writel(host->pmerrloc_base, ELEN,
			sector_size * 8 + host->pmecc_degree * cap);

	end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
	while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
		 & PMERRLOC_CALC_DONE)) {
		if (unlikely(time_after(jiffies, end_time))) {
			dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
			return -1;
		}
		cpu_relax();
	}

	roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
		& PMERRLOC_ERR_NUM_MASK) >> 8;
	/* Number of roots == degree of smu hence <= cap */
	if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
		return err_nbr - 1;

	/* Number of roots does not match the degree of smu
	 * unable to correct error */
	return -1;
}

static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
		int sector_num, int extra_bytes, int err_nbr)
{
806
	struct nand_chip *nand_chip = mtd_to_nand(mtd);
807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831
	struct atmel_nand_host *host = nand_chip->priv;
	int i = 0;
	int byte_pos, bit_pos, sector_size, pos;
	uint32_t tmp;
	uint8_t err_byte;

	sector_size = host->pmecc_sector_size;

	while (err_nbr) {
		tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
		byte_pos = tmp / 8;
		bit_pos  = tmp % 8;

		if (byte_pos >= (sector_size + extra_bytes))
			BUG();	/* should never happen */

		if (byte_pos < sector_size) {
			err_byte = *(buf + byte_pos);
			*(buf + byte_pos) ^= (1 << bit_pos);

			pos = sector_num * host->pmecc_sector_size + byte_pos;
			dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
				pos, bit_pos, err_byte, *(buf + byte_pos));
		} else {
			/* Bit flip in OOB area */
832
			tmp = sector_num * nand_chip->ecc.bytes
833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851
					+ (byte_pos - sector_size);
			err_byte = ecc[tmp];
			ecc[tmp] ^= (1 << bit_pos);

			pos = tmp + nand_chip->ecc.layout->eccpos[0];
			dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
				pos, bit_pos, err_byte, ecc[tmp]);
		}

		i++;
		err_nbr--;
	}

	return;
}

static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
	u8 *ecc)
{
852
	struct nand_chip *nand_chip = mtd_to_nand(mtd);
853
	struct atmel_nand_host *host = nand_chip->priv;
854
	int i, err_nbr;
855
	uint8_t *buf_pos;
856
	int max_bitflips = 0;
857

858 859 860 861
	/* If can correct bitfilps from erased page, do the normal check */
	if (host->caps->pmecc_correct_erase_page)
		goto normal_check;

862
	for (i = 0; i < nand_chip->ecc.total; i++)
863 864 865 866 867 868
		if (ecc[i] != 0xff)
			goto normal_check;
	/* Erased page, return OK */
	return 0;

normal_check:
869
	for (i = 0; i < nand_chip->ecc.steps; i++) {
870 871 872 873 874 875 876 877 878 879 880 881 882 883 884
		err_nbr = 0;
		if (pmecc_stat & 0x1) {
			buf_pos = buf + i * host->pmecc_sector_size;

			pmecc_gen_syndrome(mtd, i);
			pmecc_substitute(mtd);
			pmecc_get_sigma(mtd);

			err_nbr = pmecc_err_location(mtd);
			if (err_nbr == -1) {
				dev_err(host->dev, "PMECC: Too many errors\n");
				mtd->ecc_stats.failed++;
				return -EIO;
			} else {
				pmecc_correct_data(mtd, buf_pos, ecc, i,
885
					nand_chip->ecc.bytes, err_nbr);
886
				mtd->ecc_stats.corrected += err_nbr;
887
				max_bitflips = max_t(int, max_bitflips, err_nbr);
888 889 890 891 892
			}
		}
		pmecc_stat >>= 1;
	}

893
	return max_bitflips;
894 895
}

896 897 898 899 900 901 902 903 904
static void pmecc_enable(struct atmel_nand_host *host, int ecc_op)
{
	u32 val;

	if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) {
		dev_err(host->dev, "atmel_nand: wrong pmecc operation type!");
		return;
	}

905 906 907 908
	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
	val = pmecc_readl_relaxed(host->ecc, CFG);

909 910 911 912 913 914 915 916 917 918 919
	if (ecc_op == NAND_ECC_READ)
		pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP)
			| PMECC_CFG_AUTO_ENABLE);
	else
		pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP)
			& ~PMECC_CFG_AUTO_ENABLE);

	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
}

920 921 922 923
static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
{
	struct atmel_nand_host *host = chip->priv;
924
	int eccsize = chip->ecc.size * chip->ecc.steps;
925 926 927 928
	uint8_t *oob = chip->oob_poi;
	uint32_t *eccpos = chip->ecc.layout->eccpos;
	uint32_t stat;
	unsigned long end_time;
929
	int bitflips = 0;
930

931 932
	if (!host->nfc || !host->nfc->use_nfc_sram)
		pmecc_enable(host, NAND_ECC_READ);
933 934 935 936 937 938 939 940 941 942 943 944 945 946

	chip->read_buf(mtd, buf, eccsize);
	chip->read_buf(mtd, oob, mtd->oobsize);

	end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
	while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
		if (unlikely(time_after(jiffies, end_time))) {
			dev_err(host->dev, "PMECC: Timeout to get error status.\n");
			return -EIO;
		}
		cpu_relax();
	}

	stat = pmecc_readl_relaxed(host->ecc, ISR);
947 948 949 950 951 952
	if (stat != 0) {
		bitflips = pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]);
		if (bitflips < 0)
			/* uncorrectable errors */
			return 0;
	}
953

954
	return bitflips;
955 956 957
}

static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
958 959
		struct nand_chip *chip, const uint8_t *buf, int oob_required,
		int page)
960 961 962 963 964 965
{
	struct atmel_nand_host *host = chip->priv;
	uint32_t *eccpos = chip->ecc.layout->eccpos;
	int i, j;
	unsigned long end_time;

966 967 968 969
	if (!host->nfc || !host->nfc->write_by_sram) {
		pmecc_enable(host, NAND_ECC_WRITE);
		chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
	}
970 971 972 973 974 975 976 977 978 979

	end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
	while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
		if (unlikely(time_after(jiffies, end_time))) {
			dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
			return -EIO;
		}
		cpu_relax();
	}

980
	for (i = 0; i < chip->ecc.steps; i++) {
981
		for (j = 0; j < chip->ecc.bytes; j++) {
982 983
			int pos;

984
			pos = i * chip->ecc.bytes + j;
985 986 987 988 989 990 991 992 993 994 995
			chip->oob_poi[eccpos[pos]] =
				pmecc_readb_ecc_relaxed(host->ecc, i, j);
		}
	}
	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);

	return 0;
}

static void atmel_pmecc_core_init(struct mtd_info *mtd)
{
996
	struct nand_chip *nand_chip = mtd_to_nand(mtd);
997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026
	struct atmel_nand_host *host = nand_chip->priv;
	uint32_t val = 0;
	struct nand_ecclayout *ecc_layout;

	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);

	switch (host->pmecc_corr_cap) {
	case 2:
		val = PMECC_CFG_BCH_ERR2;
		break;
	case 4:
		val = PMECC_CFG_BCH_ERR4;
		break;
	case 8:
		val = PMECC_CFG_BCH_ERR8;
		break;
	case 12:
		val = PMECC_CFG_BCH_ERR12;
		break;
	case 24:
		val = PMECC_CFG_BCH_ERR24;
		break;
	}

	if (host->pmecc_sector_size == 512)
		val |= PMECC_CFG_SECTOR512;
	else if (host->pmecc_sector_size == 1024)
		val |= PMECC_CFG_SECTOR1024;

1027
	switch (nand_chip->ecc.steps) {
1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056
	case 1:
		val |= PMECC_CFG_PAGE_1SECTOR;
		break;
	case 2:
		val |= PMECC_CFG_PAGE_2SECTORS;
		break;
	case 4:
		val |= PMECC_CFG_PAGE_4SECTORS;
		break;
	case 8:
		val |= PMECC_CFG_PAGE_8SECTORS;
		break;
	}

	val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
		| PMECC_CFG_AUTO_DISABLE);
	pmecc_writel(host->ecc, CFG, val);

	ecc_layout = nand_chip->ecc.layout;
	pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
	pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
	pmecc_writel(host->ecc, EADDR,
			ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
	/* See datasheet about PMECC Clock Control Register */
	pmecc_writel(host->ecc, CLK, 2);
	pmecc_writel(host->ecc, IDR, 0xff);
	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
}

1057
/*
1058
 * Get minimum ecc requirements from NAND.
1059
 * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
1060
 * will set them according to minimum ecc requirement. Otherwise, use the
1061 1062 1063 1064 1065 1066
 * value in DTS file.
 * return 0 if success. otherwise return error code.
 */
static int pmecc_choose_ecc(struct atmel_nand_host *host,
		int *cap, int *sector_size)
{
1067 1068 1069 1070 1071
	/* Get minimum ECC requirements */
	if (host->nand_chip.ecc_strength_ds) {
		*cap = host->nand_chip.ecc_strength_ds;
		*sector_size = host->nand_chip.ecc_step_ds;
		dev_info(host->dev, "minimum ECC: %d bits in %d bytes\n",
1072 1073 1074 1075
				*cap, *sector_size);
	} else {
		*cap = 2;
		*sector_size = 512;
1076
		dev_info(host->dev, "can't detect min. ECC, assume 2 bits in 512 bytes\n");
1077 1078
	}

1079
	/* If device tree doesn't specify, use NAND's minimum ECC parameters */
1080 1081 1082 1083 1084 1085
	if (host->pmecc_corr_cap == 0) {
		/* use the most fitable ecc bits (the near bigger one ) */
		if (*cap <= 2)
			host->pmecc_corr_cap = 2;
		else if (*cap <= 4)
			host->pmecc_corr_cap = 4;
1086
		else if (*cap <= 8)
1087
			host->pmecc_corr_cap = 8;
1088
		else if (*cap <= 12)
1089
			host->pmecc_corr_cap = 12;
1090
		else if (*cap <= 24)
1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106
			host->pmecc_corr_cap = 24;
		else
			return -EINVAL;
	}
	if (host->pmecc_sector_size == 0) {
		/* use the most fitable sector size (the near smaller one ) */
		if (*sector_size >= 1024)
			host->pmecc_sector_size = 1024;
		else if (*sector_size >= 512)
			host->pmecc_sector_size = 512;
		else
			return -EINVAL;
	}
	return 0;
}

1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159
static inline int deg(unsigned int poly)
{
	/* polynomial degree is the most-significant bit index */
	return fls(poly) - 1;
}

static int build_gf_tables(int mm, unsigned int poly,
		int16_t *index_of, int16_t *alpha_to)
{
	unsigned int i, x = 1;
	const unsigned int k = 1 << deg(poly);
	unsigned int nn = (1 << mm) - 1;

	/* primitive polynomial must be of degree m */
	if (k != (1u << mm))
		return -EINVAL;

	for (i = 0; i < nn; i++) {
		alpha_to[i] = x;
		index_of[x] = i;
		if (i && (x == 1))
			/* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
			return -EINVAL;
		x <<= 1;
		if (x & k)
			x ^= poly;
	}
	alpha_to[nn] = 1;
	index_of[0] = 0;

	return 0;
}

static uint16_t *create_lookup_table(struct device *dev, int sector_size)
{
	int degree = (sector_size == 512) ?
			PMECC_GF_DIMENSION_13 :
			PMECC_GF_DIMENSION_14;
	unsigned int poly = (sector_size == 512) ?
			PMECC_GF_13_PRIMITIVE_POLY :
			PMECC_GF_14_PRIMITIVE_POLY;
	int table_size = (sector_size == 512) ?
			PMECC_LOOKUP_TABLE_SIZE_512 :
			PMECC_LOOKUP_TABLE_SIZE_1024;

	int16_t *addr = devm_kzalloc(dev, 2 * table_size * sizeof(uint16_t),
			GFP_KERNEL);
	if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
		return NULL;

	return addr;
}

1160
static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
1161 1162 1163
					 struct atmel_nand_host *host)
{
	struct nand_chip *nand_chip = &host->nand_chip;
1164
	struct mtd_info *mtd = nand_to_mtd(nand_chip);
1165
	struct resource *regs, *regs_pmerr, *regs_rom;
1166
	uint16_t *galois_table;
1167 1168
	int cap, sector_size, err_no;

1169 1170 1171 1172 1173 1174
	err_no = pmecc_choose_ecc(host, &cap, &sector_size);
	if (err_no) {
		dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
		return err_no;
	}

1175
	if (cap > host->pmecc_corr_cap ||
1176 1177
			sector_size != host->pmecc_sector_size)
		dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1178

1179 1180
	cap = host->pmecc_corr_cap;
	sector_size = host->pmecc_sector_size;
1181 1182 1183 1184
	host->pmecc_lookup_table_offset = (sector_size == 512) ?
			host->pmecc_lookup_table_offset_512 :
			host->pmecc_lookup_table_offset_1024;

1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195
	dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
		 cap, sector_size);

	regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!regs) {
		dev_warn(host->dev,
			"Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
		nand_chip->ecc.mode = NAND_ECC_SOFT;
		return 0;
	}

1196 1197 1198 1199
	host->ecc = devm_ioremap_resource(&pdev->dev, regs);
	if (IS_ERR(host->ecc)) {
		err_no = PTR_ERR(host->ecc);
		goto err;
1200 1201 1202
	}

	regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1203 1204 1205 1206
	host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr);
	if (IS_ERR(host->pmerrloc_base)) {
		err_no = PTR_ERR(host->pmerrloc_base);
		goto err;
1207 1208
	}

1209 1210 1211 1212 1213
	if (!host->has_no_lookup_table) {
		regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
		host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev,
								regs_rom);
		if (IS_ERR(host->pmecc_rom_base)) {
1214
			dev_err(host->dev, "Can not get I/O resource for ROM, will build a lookup table in runtime!\n");
1215 1216
			host->has_no_lookup_table = true;
		}
1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229
	}

	if (host->has_no_lookup_table) {
		/* Build the look-up table in runtime */
		galois_table = create_lookup_table(host->dev, sector_size);
		if (!galois_table) {
			dev_err(host->dev, "Failed to build a lookup table in runtime!\n");
			err_no = -EINVAL;
			goto err;
		}

		host->pmecc_rom_base = (void __iomem *)galois_table;
		host->pmecc_lookup_table_offset = 0;
1230 1231
	}

1232
	nand_chip->ecc.size = sector_size;
1233 1234 1235

	/* set ECC page size and oob layout */
	switch (mtd->writesize) {
1236 1237
	case 512:
	case 1024:
1238
	case 2048:
1239 1240 1241 1242 1243 1244 1245 1246
	case 4096:
	case 8192:
		if (sector_size > mtd->writesize) {
			dev_err(host->dev, "pmecc sector size is bigger than the page size!\n");
			err_no = -EINVAL;
			goto err;
		}

1247 1248
		host->pmecc_degree = (sector_size == 512) ?
			PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
1249 1250 1251 1252 1253 1254
		host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
		host->pmecc_alpha_to = pmecc_get_alpha_to(host);
		host->pmecc_index_of = host->pmecc_rom_base +
			host->pmecc_lookup_table_offset;

		nand_chip->ecc.strength = cap;
1255
		nand_chip->ecc.bytes = pmecc_get_ecc_bytes(cap, sector_size);
1256 1257 1258
		nand_chip->ecc.steps = mtd->writesize / sector_size;
		nand_chip->ecc.total = nand_chip->ecc.bytes *
			nand_chip->ecc.steps;
1259 1260
		if (nand_chip->ecc.total >
				mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
1261 1262
			dev_err(host->dev, "No room for ECC bytes\n");
			err_no = -EINVAL;
1263
			goto err;
1264 1265 1266
		}
		pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
					mtd->oobsize,
1267 1268
					nand_chip->ecc.total);

1269 1270
		nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
		break;
1271
	default:
1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284
		dev_warn(host->dev,
			"Unsupported page size for PMECC, use Software ECC\n");
		/* page size not handled by HW ECC */
		/* switching back to soft ECC */
		nand_chip->ecc.mode = NAND_ECC_SOFT;
		return 0;
	}

	/* Allocate data for PMECC computation */
	err_no = pmecc_data_alloc(host);
	if (err_no) {
		dev_err(host->dev,
				"Cannot allocate memory for PMECC computation!\n");
1285
		goto err;
1286 1287
	}

1288
	nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
1289 1290 1291 1292 1293 1294 1295
	nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
	nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;

	atmel_pmecc_core_init(mtd);

	return 0;

1296
err:
1297 1298 1299
	return err_no;
}

1300 1301 1302 1303 1304 1305 1306 1307 1308
/*
 * Calculate HW ECC
 *
 * function called after a write
 *
 * mtd:        MTD block structure
 * dat:        raw data (unused)
 * ecc_code:   buffer for ECC
 */
1309
static int atmel_nand_calculate(struct mtd_info *mtd,
1310 1311
		const u_char *dat, unsigned char *ecc_code)
{
1312
	struct nand_chip *nand_chip = mtd_to_nand(mtd);
1313
	struct atmel_nand_host *host = nand_chip->priv;
1314 1315 1316
	unsigned int ecc_value;

	/* get the first 2 ECC bytes */
1317
	ecc_value = ecc_readl(host->ecc, PR);
1318

1319 1320
	ecc_code[0] = ecc_value & 0xFF;
	ecc_code[1] = (ecc_value >> 8) & 0xFF;
1321 1322

	/* get the last 2 ECC bytes */
1323
	ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
1324

1325 1326
	ecc_code[2] = ecc_value & 0xFF;
	ecc_code[3] = (ecc_value >> 8) & 0xFF;
1327 1328 1329 1330 1331 1332 1333 1334 1335 1336

	return 0;
}

/*
 * HW ECC read page function
 *
 * mtd:        mtd info structure
 * chip:       nand chip info structure
 * buf:        buffer to store read data
1337
 * oob_required:    caller expects OOB data read to chip->oob_poi
1338
 */
1339 1340
static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
				uint8_t *buf, int oob_required, int page)
1341 1342 1343 1344 1345 1346 1347 1348
{
	int eccsize = chip->ecc.size;
	int eccbytes = chip->ecc.bytes;
	uint32_t *eccpos = chip->ecc.layout->eccpos;
	uint8_t *p = buf;
	uint8_t *oob = chip->oob_poi;
	uint8_t *ecc_pos;
	int stat;
1349
	unsigned int max_bitflips = 0;
1350

1351 1352 1353 1354 1355 1356 1357 1358
	/*
	 * Errata: ALE is incorrectly wired up to the ECC controller
	 * on the AP7000, so it will include the address cycles in the
	 * ECC calculation.
	 *
	 * Workaround: Reset the parity registers before reading the
	 * actual data.
	 */
1359 1360
	struct atmel_nand_host *host = chip->priv;
	if (host->board.need_reset_workaround)
1361 1362
		ecc_writel(host->ecc, CR, ATMEL_ECC_RST);

1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384
	/* read the page */
	chip->read_buf(mtd, p, eccsize);

	/* move to ECC position if needed */
	if (eccpos[0] != 0) {
		/* This only works on large pages
		 * because the ECC controller waits for
		 * NAND_CMD_RNDOUTSTART after the
		 * NAND_CMD_RNDOUT.
		 * anyway, for small pages, the eccpos[0] == 0
		 */
		chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
				mtd->writesize + eccpos[0], -1);
	}

	/* the ECC controller needs to read the ECC just after the data */
	ecc_pos = oob + eccpos[0];
	chip->read_buf(mtd, ecc_pos, eccbytes);

	/* check if there's an error */
	stat = chip->ecc.correct(mtd, p, oob, NULL);

1385
	if (stat < 0) {
1386
		mtd->ecc_stats.failed++;
1387
	} else {
1388
		mtd->ecc_stats.corrected += stat;
1389 1390
		max_bitflips = max_t(unsigned int, max_bitflips, stat);
	}
1391 1392 1393 1394 1395 1396 1397

	/* get back to oob start (end of page) */
	chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);

	/* read the oob */
	chip->read_buf(mtd, oob, mtd->oobsize);

1398
	return max_bitflips;
1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412
}

/*
 * HW ECC Correction
 *
 * function called after a read
 *
 * mtd:        MTD block structure
 * dat:        raw data read from the chip
 * read_ecc:   ECC from the chip (unused)
 * isnull:     unused
 *
 * Detect and correct a 1 bit error for a page
 */
1413
static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1414 1415
		u_char *read_ecc, u_char *isnull)
{
1416
	struct nand_chip *nand_chip = mtd_to_nand(mtd);
1417
	struct atmel_nand_host *host = nand_chip->priv;
1418 1419 1420 1421 1422 1423 1424
	unsigned int ecc_status;
	unsigned int ecc_word, ecc_bit;

	/* get the status from the Status Register */
	ecc_status = ecc_readl(host->ecc, SR);

	/* if there's no error */
1425
	if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1426 1427 1428
		return 0;

	/* get error bit offset (4 bits) */
1429
	ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
1430
	/* get word address (12 bits) */
1431
	ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
1432 1433 1434
	ecc_word >>= 4;

	/* if there are multiple errors */
1435
	if (ecc_status & ATMEL_ECC_MULERR) {
1436 1437
		/* check if it is a freshly erased block
		 * (filled with 0xff) */
1438 1439
		if ((ecc_bit == ATMEL_ECC_BITADDR)
				&& (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1440 1441 1442 1443 1444 1445
			/* the block has just been erased, return OK */
			return 0;
		}
		/* it doesn't seems to be a freshly
		 * erased block.
		 * We can't correct so many errors */
1446
		dev_dbg(host->dev, "atmel_nand : multiple errors detected."
1447 1448 1449 1450 1451
				" Unable to correct.\n");
		return -EIO;
	}

	/* if there's a single bit error : we can correct it */
1452
	if (ecc_status & ATMEL_ECC_ECCERR) {
1453 1454 1455
		/* there's nothing much to do here.
		 * the bit error is on the ECC itself.
		 */
1456
		dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
1457 1458 1459 1460
				" Nothing to correct\n");
		return 0;
	}

1461
	dev_dbg(host->dev, "atmel_nand : one bit error on data."
1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472
			" (word offset in the page :"
			" 0x%x bit offset : 0x%x)\n",
			ecc_word, ecc_bit);
	/* correct the error */
	if (nand_chip->options & NAND_BUSWIDTH_16) {
		/* 16 bits words */
		((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
	} else {
		/* 8 bits words */
		dat[ecc_word] ^= (1 << ecc_bit);
	}
1473
	dev_dbg(host->dev, "atmel_nand : error corrected\n");
1474 1475 1476 1477
	return 1;
}

/*
1478
 * Enable HW ECC : unused on most chips
1479
 */
1480 1481
static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
{
1482
	struct nand_chip *nand_chip = mtd_to_nand(mtd);
1483 1484 1485
	struct atmel_nand_host *host = nand_chip->priv;

	if (host->board.need_reset_workaround)
1486 1487
		ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
}
1488

1489 1490
static const struct of_device_id atmel_nand_dt_ids[];

1491
static int atmel_of_init_port(struct atmel_nand_host *host,
1492
			      struct device_node *np)
1493
{
1494
	u32 val;
1495
	u32 offset[2];
1496 1497
	int ecc_mode;
	struct atmel_nand_data *board = &host->board;
1498
	enum of_gpio_flags flags = 0;
1499

1500 1501 1502
	host->caps = (struct atmel_nand_caps *)
		of_match_device(atmel_nand_dt_ids, host->dev)->data;

1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524
	if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
		if (val >= 32) {
			dev_err(host->dev, "invalid addr-offset %u\n", val);
			return -EINVAL;
		}
		board->ale = val;
	}

	if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
		if (val >= 32) {
			dev_err(host->dev, "invalid cmd-offset %u\n", val);
			return -EINVAL;
		}
		board->cle = val;
	}

	ecc_mode = of_get_nand_ecc_mode(np);

	board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;

	board->on_flash_bbt = of_get_nand_on_flash_bbt(np);

1525 1526
	board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");

1527 1528 1529 1530 1531 1532 1533 1534 1535
	if (of_get_nand_bus_width(np) == 16)
		board->bus_width_16 = 1;

	board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
	board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);

	board->enable_pin = of_get_gpio(np, 1);
	board->det_pin = of_get_gpio(np, 2);

1536 1537
	host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");

1538 1539 1540
	/* load the nfc driver if there is */
	of_platform_populate(np, NULL, NULL, host->dev);

1541 1542 1543 1544 1545
	if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
		return 0;	/* Not using PMECC */

	/* use PMECC, get correction capability, sector size and lookup
	 * table offset.
1546 1547
	 * If correction bits and sector size are not specified, then find
	 * them from NAND ONFI parameters.
1548
	 */
1549 1550 1551 1552 1553 1554 1555 1556 1557
	if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
		if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
				(val != 24)) {
			dev_err(host->dev,
				"Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
				val);
			return -EINVAL;
		}
		host->pmecc_corr_cap = (u8)val;
1558 1559
	}

1560 1561 1562 1563 1564 1565 1566 1567
	if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
		if ((val != 512) && (val != 1024)) {
			dev_err(host->dev,
				"Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
				val);
			return -EINVAL;
		}
		host->pmecc_sector_size = (u16)val;
1568 1569 1570 1571
	}

	if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
			offset, 2) != 0) {
1572 1573 1574 1575
		dev_err(host->dev, "Cannot get PMECC lookup table offset, will build a lookup table in runtime.\n");
		host->has_no_lookup_table = true;
		/* Will build a lookup table and initialize the offset later */
		return 0;
1576
	}
1577
	if (!offset[0] && !offset[1]) {
1578 1579 1580
		dev_err(host->dev, "Invalid PMECC lookup table offset\n");
		return -EINVAL;
	}
1581 1582
	host->pmecc_lookup_table_offset_512 = offset[0];
	host->pmecc_lookup_table_offset_1024 = offset[1];
1583

1584 1585 1586
	return 0;
}

1587
static int atmel_hw_nand_init_params(struct platform_device *pdev,
1588 1589 1590
					 struct atmel_nand_host *host)
{
	struct nand_chip *nand_chip = &host->nand_chip;
1591
	struct mtd_info *mtd = nand_to_mtd(nand_chip);
1592 1593 1594 1595 1596 1597 1598 1599 1600 1601
	struct resource		*regs;

	regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!regs) {
		dev_err(host->dev,
			"Can't get I/O resource regs, use software ECC\n");
		nand_chip->ecc.mode = NAND_ECC_SOFT;
		return 0;
	}

1602
	host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1603
	if (IS_ERR(host->ecc))
1604
		return PTR_ERR(host->ecc);
1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644

	/* ECC is calculated for the whole page (1 step) */
	nand_chip->ecc.size = mtd->writesize;

	/* set ECC page size and oob layout */
	switch (mtd->writesize) {
	case 512:
		nand_chip->ecc.layout = &atmel_oobinfo_small;
		ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
		break;
	case 1024:
		nand_chip->ecc.layout = &atmel_oobinfo_large;
		ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
		break;
	case 2048:
		nand_chip->ecc.layout = &atmel_oobinfo_large;
		ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
		break;
	case 4096:
		nand_chip->ecc.layout = &atmel_oobinfo_large;
		ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
		break;
	default:
		/* page size not handled by HW ECC */
		/* switching back to soft ECC */
		nand_chip->ecc.mode = NAND_ECC_SOFT;
		return 0;
	}

	/* set up for HW ECC */
	nand_chip->ecc.calculate = atmel_nand_calculate;
	nand_chip->ecc.correct = atmel_nand_correct;
	nand_chip->ecc.hwctl = atmel_nand_hwctl;
	nand_chip->ecc.read_page = atmel_nand_read_page;
	nand_chip->ecc.bytes = 4;
	nand_chip->ecc.strength = 1;

	return 0;
}

1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663
static inline u32 nfc_read_status(struct atmel_nand_host *host)
{
	u32 err_flags = NFC_SR_DTOE | NFC_SR_UNDEF | NFC_SR_AWB | NFC_SR_ASE;
	u32 nfc_status = nfc_readl(host->nfc->hsmc_regs, SR);

	if (unlikely(nfc_status & err_flags)) {
		if (nfc_status & NFC_SR_DTOE)
			dev_err(host->dev, "NFC: Waiting Nand R/B Timeout Error\n");
		else if (nfc_status & NFC_SR_UNDEF)
			dev_err(host->dev, "NFC: Access Undefined Area Error\n");
		else if (nfc_status & NFC_SR_AWB)
			dev_err(host->dev, "NFC: Access memory While NFC is busy\n");
		else if (nfc_status & NFC_SR_ASE)
			dev_err(host->dev, "NFC: Access memory Size Error\n");
	}

	return nfc_status;
}

1664 1665 1666 1667 1668
/* SMC interrupt service routine */
static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
{
	struct atmel_nand_host *host = dev_id;
	u32 status, mask, pending;
1669
	irqreturn_t ret = IRQ_NONE;
1670

1671
	status = nfc_read_status(host);
1672 1673 1674 1675
	mask = nfc_readl(host->nfc->hsmc_regs, IMR);
	pending = status & mask;

	if (pending & NFC_SR_XFR_DONE) {
1676
		complete(&host->nfc->comp_xfer_done);
1677
		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
1678 1679 1680 1681
		ret = IRQ_HANDLED;
	}
	if (pending & NFC_SR_RB_EDGE) {
		complete(&host->nfc->comp_ready);
1682
		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
1683 1684 1685 1686
		ret = IRQ_HANDLED;
	}
	if (pending & NFC_SR_CMD_DONE) {
		complete(&host->nfc->comp_cmd_done);
1687
		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE);
1688
		ret = IRQ_HANDLED;
1689 1690 1691 1692 1693 1694
	}

	return ret;
}

/* NFC(Nand Flash Controller) related functions */
1695
static void nfc_prepare_interrupt(struct atmel_nand_host *host, u32 flag)
1696
{
1697 1698 1699 1700 1701 1702 1703 1704
	if (flag & NFC_SR_XFR_DONE)
		init_completion(&host->nfc->comp_xfer_done);

	if (flag & NFC_SR_RB_EDGE)
		init_completion(&host->nfc->comp_ready);

	if (flag & NFC_SR_CMD_DONE)
		init_completion(&host->nfc->comp_cmd_done);
1705 1706 1707

	/* Enable interrupt that need to wait for */
	nfc_writel(host->nfc->hsmc_regs, IER, flag);
1708
}
1709

1710 1711 1712 1713 1714 1715 1716 1717 1718 1719
static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
{
	int i, index = 0;
	struct completion *comp[3];	/* Support 3 interrupt completion */

	if (flag & NFC_SR_XFR_DONE)
		comp[index++] = &host->nfc->comp_xfer_done;

	if (flag & NFC_SR_RB_EDGE)
		comp[index++] = &host->nfc->comp_ready;
1720

1721 1722 1723 1724
	if (flag & NFC_SR_CMD_DONE)
		comp[index++] = &host->nfc->comp_cmd_done;

	if (index == 0) {
1725
		dev_err(host->dev, "Unknown interrupt flag: 0x%08x\n", flag);
1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739
		return -EINVAL;
	}

	for (i = 0; i < index; i++) {
		if (wait_for_completion_timeout(comp[i],
				msecs_to_jiffies(NFC_TIME_OUT_MS)))
			continue;	/* wait for next completion */
		else
			goto err_timeout;
	}

	return 0;

err_timeout:
1740
	dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
1741 1742
	/* Disable the interrupt as it is not handled by interrupt handler */
	nfc_writel(host->nfc->hsmc_regs, IDR, flag);
1743 1744 1745 1746 1747 1748 1749
	return -ETIMEDOUT;
}

static int nfc_send_command(struct atmel_nand_host *host,
	unsigned int cmd, unsigned int addr, unsigned char cycle0)
{
	unsigned long timeout;
1750 1751 1752
	u32 flag = NFC_SR_CMD_DONE;
	flag |= cmd & NFCADDR_CMD_DATAEN ? NFC_SR_XFR_DONE : 0;

1753 1754 1755 1756 1757
	dev_dbg(host->dev,
		"nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
		cmd, addr, cycle0);

	timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1758
	while (nfc_readl(host->nfc->hsmc_regs, SR) & NFC_SR_BUSY) {
1759 1760
		if (time_after(jiffies, timeout)) {
			dev_err(host->dev,
1761
				"Time out to wait for NFC ready!\n");
1762 1763 1764
			return -ETIMEDOUT;
		}
	}
1765 1766

	nfc_prepare_interrupt(host, flag);
1767 1768
	nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0);
	nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs);
1769
	return nfc_wait_interrupt(host, flag);
1770 1771 1772 1773
}

static int nfc_device_ready(struct mtd_info *mtd)
{
1774
	u32 status, mask;
1775
	struct nand_chip *nand_chip = mtd_to_nand(mtd);
1776
	struct atmel_nand_host *host = nand_chip->priv;
1777 1778 1779 1780 1781 1782 1783 1784 1785 1786

	status = nfc_read_status(host);
	mask = nfc_readl(host->nfc->hsmc_regs, IMR);

	/* The mask should be 0. If not we may lost interrupts */
	if (unlikely(mask & status))
		dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
				mask & status);

	return status & NFC_SR_RB_EDGE;
1787 1788 1789 1790
}

static void nfc_select_chip(struct mtd_info *mtd, int chip)
{
1791
	struct nand_chip *nand_chip = mtd_to_nand(mtd);
1792 1793 1794 1795 1796 1797 1798 1799
	struct atmel_nand_host *host = nand_chip->priv;

	if (chip == -1)
		nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE);
	else
		nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE);
}

1800 1801
static int nfc_make_addr(struct mtd_info *mtd, int command, int column,
		int page_addr, unsigned int *addr1234, unsigned int *cycle0)
1802
{
1803
	struct nand_chip *chip = mtd_to_nand(mtd);
1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814

	int acycle = 0;
	unsigned char addr_bytes[8];
	int index = 0, bit_shift;

	BUG_ON(addr1234 == NULL || cycle0 == NULL);

	*cycle0 = 0;
	*addr1234 = 0;

	if (column != -1) {
1815 1816
		if (chip->options & NAND_BUSWIDTH_16 &&
				!nand_opcode_8bits(command))
1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842
			column >>= 1;
		addr_bytes[acycle++] = column & 0xff;
		if (mtd->writesize > 512)
			addr_bytes[acycle++] = (column >> 8) & 0xff;
	}

	if (page_addr != -1) {
		addr_bytes[acycle++] = page_addr & 0xff;
		addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
		if (chip->chipsize > (128 << 20))
			addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
	}

	if (acycle > 4)
		*cycle0 = addr_bytes[index++];

	for (bit_shift = 0; index < acycle; bit_shift += 8)
		*addr1234 += addr_bytes[index++] << bit_shift;

	/* return acycle in cmd register */
	return acycle << NFCADDR_CMD_ACYCLE_BIT_POS;
}

static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
				int column, int page_addr)
{
1843
	struct nand_chip *chip = mtd_to_nand(mtd);
1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859
	struct atmel_nand_host *host = chip->priv;
	unsigned long timeout;
	unsigned int nfc_addr_cmd = 0;

	unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;

	/* Set default settings: no cmd2, no addr cycle. read from nand */
	unsigned int cmd2 = 0;
	unsigned int vcmd2 = 0;
	int acycle = NFCADDR_CMD_ACYCLE_NONE;
	int csid = NFCADDR_CMD_CSID_3;
	int dataen = NFCADDR_CMD_DATADIS;
	int nfcwr = NFCADDR_CMD_NFCRD;
	unsigned int addr1234 = 0;
	unsigned int cycle0 = 0;
	bool do_addr = true;
1860
	host->nfc->data_in_sram = NULL;
1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901

	dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
	     __func__, command, column, page_addr);

	switch (command) {
	case NAND_CMD_RESET:
		nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
		nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
		udelay(chip->chip_delay);

		nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
		timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
		while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
			if (time_after(jiffies, timeout)) {
				dev_err(host->dev,
					"Time out to wait status ready!\n");
				break;
			}
		}
		return;
	case NAND_CMD_STATUS:
		do_addr = false;
		break;
	case NAND_CMD_PARAM:
	case NAND_CMD_READID:
		do_addr = false;
		acycle = NFCADDR_CMD_ACYCLE_1;
		if (column != -1)
			addr1234 = column;
		break;
	case NAND_CMD_RNDOUT:
		cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS;
		vcmd2 = NFCADDR_CMD_VCMD2;
		break;
	case NAND_CMD_READ0:
	case NAND_CMD_READOOB:
		if (command == NAND_CMD_READOOB) {
			column += mtd->writesize;
			command = NAND_CMD_READ0; /* only READ0 is valid */
			cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
		}
1902 1903 1904 1905 1906 1907 1908 1909 1910 1911
		if (host->nfc->use_nfc_sram) {
			/* Enable Data transfer to sram */
			dataen = NFCADDR_CMD_DATAEN;

			/* Need enable PMECC now, since NFC will transfer
			 * data in bus after sending nfc read command.
			 */
			if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
				pmecc_enable(host, NAND_ECC_READ);
		}
1912 1913 1914 1915 1916 1917 1918 1919 1920

		cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS;
		vcmd2 = NFCADDR_CMD_VCMD2;
		break;
	/* For prgramming command, the cmd need set to write enable */
	case NAND_CMD_PAGEPROG:
	case NAND_CMD_SEQIN:
	case NAND_CMD_RNDIN:
		nfcwr = NFCADDR_CMD_NFCWR;
1921 1922
		if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN)
			dataen = NFCADDR_CMD_DATAEN;
1923 1924 1925 1926 1927 1928
		break;
	default:
		break;
	}

	if (do_addr)
1929 1930
		acycle = nfc_make_addr(mtd, command, column, page_addr,
				&addr1234, &cycle0);
1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951

	nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
	nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);

	/*
	 * Program and erase have their own busy handlers status, sequential
	 * in, and deplete1 need no delay.
	 */
	switch (command) {
	case NAND_CMD_CACHEDPROG:
	case NAND_CMD_PAGEPROG:
	case NAND_CMD_ERASE1:
	case NAND_CMD_ERASE2:
	case NAND_CMD_RNDIN:
	case NAND_CMD_STATUS:
	case NAND_CMD_RNDOUT:
	case NAND_CMD_SEQIN:
	case NAND_CMD_READID:
		return;

	case NAND_CMD_READ0:
1952 1953 1954 1955 1956
		if (dataen == NFCADDR_CMD_DATAEN) {
			host->nfc->data_in_sram = host->nfc->sram_bank0 +
				nfc_get_sram_off(host);
			return;
		}
1957 1958
		/* fall through */
	default:
1959
		nfc_prepare_interrupt(host, NFC_SR_RB_EDGE);
1960 1961 1962 1963
		nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
	}
}

1964 1965 1966 1967 1968 1969 1970
static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
			uint32_t offset, int data_len, const uint8_t *buf,
			int oob_required, int page, int cached, int raw)
{
	int cfg, len;
	int status = 0;
	struct atmel_nand_host *host = chip->priv;
1971
	void *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host);
1972 1973 1974 1975 1976 1977 1978 1979 1980 1981

	/* Subpage write is not supported */
	if (offset || (data_len < mtd->writesize))
		return -EINVAL;

	len = mtd->writesize;
	/* Copy page data to sram that will write to nand via NFC */
	if (use_dma) {
		if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
			/* Fall back to use cpu copy */
1982
			memcpy(sram, buf, len);
1983
	} else {
1984
		memcpy(sram, buf, len);
1985 1986
	}

1987 1988
	cfg = nfc_readl(host->nfc->hsmc_regs, CFG);
	if (unlikely(raw) && oob_required) {
1989
		memcpy(sram + len, chip->oob_poi, mtd->oobsize);
1990 1991 1992 1993 1994 1995
		len += mtd->oobsize;
		nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE);
	} else {
		nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE);
	}

1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009
	if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
		/*
		 * When use NFC sram, need set up PMECC before send
		 * NAND_CMD_SEQIN command. Since when the nand command
		 * is sent, nfc will do transfer from sram and nand.
		 */
		pmecc_enable(host, NAND_ECC_WRITE);

	host->nfc->will_write_sram = true;
	chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
	host->nfc->will_write_sram = false;

	if (likely(!raw))
		/* Need to write ecc into oob */
2010 2011
		status = chip->ecc.write_page(mtd, chip, buf, oob_required,
					      page);
2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027

	if (status < 0)
		return status;

	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
	status = chip->waitfunc(mtd, chip);

	if ((status & NAND_STATUS_FAIL) && (chip->errstat))
		status = chip->errstat(mtd, chip, FL_WRITING, status, page);

	if (status & NAND_STATUS_FAIL)
		return -EIO;

	return 0;
}

2028 2029
static int nfc_sram_init(struct mtd_info *mtd)
{
2030
	struct nand_chip *chip = mtd_to_nand(mtd);
2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069
	struct atmel_nand_host *host = chip->priv;
	int res = 0;

	/* Initialize the NFC CFG register */
	unsigned int cfg_nfc = 0;

	/* set page size and oob layout */
	switch (mtd->writesize) {
	case 512:
		cfg_nfc = NFC_CFG_PAGESIZE_512;
		break;
	case 1024:
		cfg_nfc = NFC_CFG_PAGESIZE_1024;
		break;
	case 2048:
		cfg_nfc = NFC_CFG_PAGESIZE_2048;
		break;
	case 4096:
		cfg_nfc = NFC_CFG_PAGESIZE_4096;
		break;
	case 8192:
		cfg_nfc = NFC_CFG_PAGESIZE_8192;
		break;
	default:
		dev_err(host->dev, "Unsupported page size for NFC.\n");
		res = -ENXIO;
		return res;
	}

	/* oob bytes size = (NFCSPARESIZE + 1) * 4
	 * Max support spare size is 512 bytes. */
	cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
		& NFC_CFG_NFC_SPARESIZE);
	/* default set a max timeout */
	cfg_nfc |= NFC_CFG_RSPARE |
			NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL;

	nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc);

2070
	host->nfc->will_write_sram = false;
2071 2072
	nfc_set_sram_bank(host, 0);

2073 2074 2075 2076 2077 2078 2079 2080
	/* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
	if (host->nfc->write_by_sram) {
		if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
				chip->ecc.mode == NAND_ECC_NONE)
			chip->write_page = nfc_sram_write_page;
		else
			host->nfc->write_by_sram = false;
	}
2081

2082 2083
	dev_info(host->dev, "Using NFC Sram read %s\n",
			host->nfc->write_by_sram ? "and write" : "");
2084 2085 2086
	return 0;
}

2087
static struct platform_driver atmel_nand_nfc_driver;
2088 2089 2090
/*
 * Probe for the NAND device.
 */
2091
static int atmel_nand_probe(struct platform_device *pdev)
2092
{
2093
	struct atmel_nand_host *host;
2094 2095
	struct mtd_info *mtd;
	struct nand_chip *nand_chip;
2096
	struct resource *mem;
2097
	int res, irq;
2098 2099

	/* Allocate memory for the device structure (and zero it) */
2100
	host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2101
	if (!host)
2102 2103
		return -ENOMEM;

2104 2105 2106 2107
	res = platform_driver_register(&atmel_nand_nfc_driver);
	if (res)
		dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n");

2108 2109 2110 2111
	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	host->io_base = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(host->io_base)) {
		res = PTR_ERR(host->io_base);
2112
		goto err_nand_ioremap;
2113
	}
2114
	host->io_phys = (dma_addr_t)mem->start;
2115 2116

	nand_chip = &host->nand_chip;
2117
	mtd = nand_to_mtd(nand_chip);
2118
	host->dev = &pdev->dev;
2119
	if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
2120
		nand_set_flash_node(nand_chip, pdev->dev.of_node);
2121
		/* Only when CONFIG_OF is enabled of_node can be parsed */
2122 2123
		res = atmel_of_init_port(host, pdev->dev.of_node);
		if (res)
2124
			goto err_nand_ioremap;
2125
	} else {
2126
		memcpy(&host->board, dev_get_platdata(&pdev->dev),
2127 2128
		       sizeof(struct atmel_nand_data));
	}
2129 2130 2131

	nand_chip->priv = host;		/* link the private data structures */
	mtd->priv = nand_chip;
2132
	mtd->dev.parent = &pdev->dev;
2133 2134 2135 2136

	/* Set address of NAND IO lines */
	nand_chip->IO_ADDR_R = host->io_base;
	nand_chip->IO_ADDR_W = host->io_base;
2137

2138 2139 2140
	if (nand_nfc.is_initialized) {
		/* NFC driver is probed and initialized */
		host->nfc = &nand_nfc;
2141

2142 2143 2144
		nand_chip->select_chip = nfc_select_chip;
		nand_chip->dev_ready = nfc_device_ready;
		nand_chip->cmdfunc = nfc_nand_command;
2145

2146 2147 2148 2149
		/* Initialize the interrupt for NFC */
		irq = platform_get_irq(pdev, 0);
		if (irq < 0) {
			dev_err(host->dev, "Cannot get HSMC irq!\n");
2150
			res = irq;
2151
			goto err_nand_ioremap;
2152 2153
		}

2154 2155 2156 2157 2158
		res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt,
				0, "hsmc", host);
		if (res) {
			dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
				irq);
2159
			goto err_nand_ioremap;
2160
		}
2161 2162 2163 2164 2165 2166
	} else {
		res = atmel_nand_set_enable_ready_pins(mtd);
		if (res)
			goto err_nand_ioremap;

		nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
2167
	}
2168

2169
	nand_chip->ecc.mode = host->board.ecc_mode;
2170
	nand_chip->chip_delay = 40;		/* 40us command delay time */
2171

2172
	if (host->board.bus_width_16)	/* 16-bit bus width */
2173
		nand_chip->options |= NAND_BUSWIDTH_16;
2174 2175 2176

	nand_chip->read_buf = atmel_read_buf;
	nand_chip->write_buf = atmel_write_buf;
2177

2178
	platform_set_drvdata(pdev, host);
2179
	atmel_nand_enable(host);
2180

2181
	if (gpio_is_valid(host->board.det_pin)) {
2182 2183
		res = devm_gpio_request(&pdev->dev,
				host->board.det_pin, "nand_det");
2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198
		if (res < 0) {
			dev_err(&pdev->dev,
				"can't request det gpio %d\n",
				host->board.det_pin);
			goto err_no_card;
		}

		res = gpio_direction_input(host->board.det_pin);
		if (res < 0) {
			dev_err(&pdev->dev,
				"can't request input direction det gpio %d\n",
				host->board.det_pin);
			goto err_no_card;
		}

2199
		if (gpio_get_value(host->board.det_pin)) {
2200
			dev_info(&pdev->dev, "No SmartMedia card inserted.\n");
2201
			res = -ENXIO;
2202
			goto err_no_card;
2203 2204 2205
		}
	}

2206
	if (host->board.on_flash_bbt || on_flash_bbt) {
2207
		dev_info(&pdev->dev, "Use On Flash BBT\n");
2208
		nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
2209 2210
	}

2211
	if (!host->board.has_dma)
2212 2213 2214
		use_dma = 0;

	if (use_dma) {
2215 2216 2217 2218
		dma_cap_mask_t mask;

		dma_cap_zero(mask);
		dma_cap_set(DMA_MEMCPY, mask);
2219
		host->dma_chan = dma_request_channel(mask, NULL, NULL);
2220 2221 2222 2223 2224 2225
		if (!host->dma_chan) {
			dev_err(host->dev, "Failed to request DMA channel\n");
			use_dma = 0;
		}
	}
	if (use_dma)
2226 2227
		dev_info(host->dev, "Using %s for DMA transfers.\n",
					dma_chan_name(host->dma_chan));
2228 2229 2230
	else
		dev_info(host->dev, "No DMA support for NAND access.\n");

2231
	/* first scan to find the device and get the page size */
2232
	if (nand_scan_ident(mtd, 1, NULL)) {
2233
		res = -ENXIO;
2234
		goto err_scan_ident;
2235 2236
	}

2237
	if (nand_chip->ecc.mode == NAND_ECC_HW) {
2238 2239 2240 2241 2242
		if (host->has_pmecc)
			res = atmel_pmecc_nand_init_params(pdev, host);
		else
			res = atmel_hw_nand_init_params(pdev, host);

2243 2244
		if (res != 0)
			goto err_hw_ecc;
2245 2246
	}

2247 2248 2249 2250 2251 2252 2253 2254 2255
	/* initialize the nfc configuration register */
	if (host->nfc && host->nfc->use_nfc_sram) {
		res = nfc_sram_init(mtd);
		if (res) {
			host->nfc->use_nfc_sram = false;
			dev_err(host->dev, "Disable use nfc sram for data transfer.\n");
		}
	}

2256 2257
	/* second phase scan */
	if (nand_scan_tail(mtd)) {
2258
		res = -ENXIO;
2259
		goto err_scan_tail;
2260 2261
	}

2262
	mtd->name = "atmel_nand";
2263 2264
	res = mtd_device_register(mtd, host->board.parts,
				  host->board.num_parts);
2265 2266 2267
	if (!res)
		return res;

2268
err_scan_tail:
2269
	if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW)
2270
		pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2271
err_hw_ecc:
2272 2273
err_scan_ident:
err_no_card:
2274
	atmel_nand_disable(host);
2275 2276
	if (host->dma_chan)
		dma_release_channel(host->dma_chan);
2277
err_nand_ioremap:
2278 2279 2280 2281 2282 2283
	return res;
}

/*
 * Remove a NAND device.
 */
2284
static int atmel_nand_remove(struct platform_device *pdev)
2285
{
2286
	struct atmel_nand_host *host = platform_get_drvdata(pdev);
2287
	struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
2288 2289 2290

	nand_release(mtd);

2291
	atmel_nand_disable(host);
2292

2293 2294 2295 2296 2297 2298
	if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
		pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
		pmerrloc_writel(host->pmerrloc_base, ELDIS,
				PMERRLOC_DISABLE);
	}

2299 2300 2301
	if (host->dma_chan)
		dma_release_channel(host->dma_chan);

2302 2303
	platform_driver_unregister(&atmel_nand_nfc_driver);

2304 2305 2306
	return 0;
}

2307
static const struct atmel_nand_caps at91rm9200_caps = {
2308 2309 2310
	.pmecc_correct_erase_page = false,
};

2311
static const struct atmel_nand_caps sama5d4_caps = {
2312 2313 2314
	.pmecc_correct_erase_page = true,
};

2315
static const struct of_device_id atmel_nand_dt_ids[] = {
2316 2317
	{ .compatible = "atmel,at91rm9200-nand", .data = &at91rm9200_caps },
	{ .compatible = "atmel,sama5d4-nand", .data = &sama5d4_caps },
2318 2319 2320 2321 2322
	{ /* sentinel */ }
};

MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);

2323 2324 2325 2326
static int atmel_nand_nfc_probe(struct platform_device *pdev)
{
	struct atmel_nfc *nfc = &nand_nfc;
	struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
2327
	int ret;
2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340

	nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
	if (IS_ERR(nfc->base_cmd_regs))
		return PTR_ERR(nfc->base_cmd_regs);

	nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
	if (IS_ERR(nfc->hsmc_regs))
		return PTR_ERR(nfc->hsmc_regs);

	nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2);
	if (nfc_sram) {
2341 2342
		nfc->sram_bank0 = (void * __force)
				devm_ioremap_resource(&pdev->dev, nfc_sram);
2343
		if (IS_ERR(nfc->sram_bank0)) {
2344 2345
			dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
					PTR_ERR(nfc->sram_bank0));
2346 2347
		} else {
			nfc->use_nfc_sram = true;
2348
			nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
2349 2350 2351 2352 2353

			if (pdev->dev.of_node)
				nfc->write_by_sram = of_property_read_bool(
						pdev->dev.of_node,
						"atmel,write-by-sram");
2354
		}
2355 2356
	}

2357 2358 2359
	nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
	nfc_readl(nfc->hsmc_regs, SR);	/* clear the NFC_SR */

2360 2361 2362 2363 2364 2365 2366 2367 2368
	nfc->clk = devm_clk_get(&pdev->dev, NULL);
	if (!IS_ERR(nfc->clk)) {
		ret = clk_prepare_enable(nfc->clk);
		if (ret)
			return ret;
	} else {
		dev_warn(&pdev->dev, "NFC clock missing, update your Device Tree");
	}

2369 2370
	nfc->is_initialized = true;
	dev_info(&pdev->dev, "NFC is probed.\n");
2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381

	return 0;
}

static int atmel_nand_nfc_remove(struct platform_device *pdev)
{
	struct atmel_nfc *nfc = &nand_nfc;

	if (!IS_ERR(nfc->clk))
		clk_disable_unprepare(nfc->clk);

2382 2383 2384
	return 0;
}

2385
static const struct of_device_id atmel_nand_nfc_match[] = {
2386 2387 2388
	{ .compatible = "atmel,sama5d3-nfc" },
	{ /* sentinel */ }
};
2389
MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
2390 2391 2392 2393 2394 2395 2396

static struct platform_driver atmel_nand_nfc_driver = {
	.driver = {
		.name = "atmel_nand_nfc",
		.of_match_table = of_match_ptr(atmel_nand_nfc_match),
	},
	.probe = atmel_nand_nfc_probe,
2397
	.remove = atmel_nand_nfc_remove,
2398 2399
};

2400
static struct platform_driver atmel_nand_driver = {
2401 2402
	.probe		= atmel_nand_probe,
	.remove		= atmel_nand_remove,
2403
	.driver		= {
2404
		.name	= "atmel_nand",
2405
		.of_match_table	= of_match_ptr(atmel_nand_dt_ids),
2406 2407 2408
	},
};

2409
module_platform_driver(atmel_nand_driver);
2410 2411 2412

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Rick Bronson");
2413
MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
2414
MODULE_ALIAS("platform:atmel_nand");