dss.c 18.6 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
/*
 * linux/drivers/video/omap2/dss/dss.c
 *
 * Copyright (C) 2009 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * Some code and ideas taken from drivers/video/omap/ driver
 * by Imre Deak.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#define DSS_SUBSYS_NAME "DSS"

#include <linux/kernel.h>
#include <linux/io.h>
27
#include <linux/export.h>
28 29 30 31
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/clk.h>
32
#include <linux/platform_device.h>
33
#include <linux/pm_runtime.h>
34

35
#include <video/omapdss.h>
36 37

#include <plat/cpu.h>
38
#include <plat/clock.h>
39

40
#include "dss.h"
41
#include "dss_features.h"
42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

#define DSS_SZ_REGS			SZ_512

struct dss_reg {
	u16 idx;
};

#define DSS_REG(idx)			((const struct dss_reg) { idx })

#define DSS_REVISION			DSS_REG(0x0000)
#define DSS_SYSCONFIG			DSS_REG(0x0010)
#define DSS_SYSSTATUS			DSS_REG(0x0014)
#define DSS_CONTROL			DSS_REG(0x0040)
#define DSS_SDI_CONTROL			DSS_REG(0x0044)
#define DSS_PLL_CONTROL			DSS_REG(0x0048)
#define DSS_SDI_STATUS			DSS_REG(0x005C)

#define REG_GET(idx, start, end) \
	FLD_GET(dss_read_reg(idx), start, end)

#define REG_FLD_MOD(idx, val, start, end) \
	dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))

static struct {
66
	struct platform_device *pdev;
67
	void __iomem    *base;
68

69
	struct clk	*dpll4_m4_ck;
70
	struct clk	*dss_clk;
71 72 73 74 75 76

	unsigned long	cache_req_pck;
	unsigned long	cache_prate;
	struct dss_clock_info cache_dss_cinfo;
	struct dispc_clock_info cache_dispc_cinfo;

77
	enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
78 79
	enum omap_dss_clk_source dispc_clk_source;
	enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
80

81
	bool		ctx_valid;
82 83 84
	u32		ctx[DSS_SZ_REGS / sizeof(u32)];
} dss;

85
static const char * const dss_generic_clk_source_names[] = {
86 87 88
	[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]	= "DSI_PLL_HSDIV_DISPC",
	[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]	= "DSI_PLL_HSDIV_DSI",
	[OMAP_DSS_CLK_SRC_FCK]			= "DSS_FCK",
89 90
};

91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
static inline void dss_write_reg(const struct dss_reg idx, u32 val)
{
	__raw_writel(val, dss.base + idx.idx);
}

static inline u32 dss_read_reg(const struct dss_reg idx)
{
	return __raw_readl(dss.base + idx.idx);
}

#define SR(reg) \
	dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
#define RR(reg) \
	dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])

106
static void dss_save_context(void)
107
{
108
	DSSDBG("dss_save_context\n");
109 110 111

	SR(CONTROL);

112 113 114 115 116
	if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
			OMAP_DISPLAY_TYPE_SDI) {
		SR(SDI_CONTROL);
		SR(PLL_CONTROL);
	}
117 118 119 120

	dss.ctx_valid = true;

	DSSDBG("context saved\n");
121 122
}

123
static void dss_restore_context(void)
124
{
125
	DSSDBG("dss_restore_context\n");
126

127 128 129
	if (!dss.ctx_valid)
		return;

130 131
	RR(CONTROL);

132 133 134 135 136
	if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
			OMAP_DISPLAY_TYPE_SDI) {
		RR(SDI_CONTROL);
		RR(PLL_CONTROL);
	}
137 138

	DSSDBG("context restored\n");
139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230
}

#undef SR
#undef RR

void dss_sdi_init(u8 datapairs)
{
	u32 l;

	BUG_ON(datapairs > 3 || datapairs < 1);

	l = dss_read_reg(DSS_SDI_CONTROL);
	l = FLD_MOD(l, 0xf, 19, 15);		/* SDI_PDIV */
	l = FLD_MOD(l, datapairs-1, 3, 2);	/* SDI_PRSEL */
	l = FLD_MOD(l, 2, 1, 0);		/* SDI_BWSEL */
	dss_write_reg(DSS_SDI_CONTROL, l);

	l = dss_read_reg(DSS_PLL_CONTROL);
	l = FLD_MOD(l, 0x7, 25, 22);	/* SDI_PLL_FREQSEL */
	l = FLD_MOD(l, 0xb, 16, 11);	/* SDI_PLL_REGN */
	l = FLD_MOD(l, 0xb4, 10, 1);	/* SDI_PLL_REGM */
	dss_write_reg(DSS_PLL_CONTROL, l);
}

int dss_sdi_enable(void)
{
	unsigned long timeout;

	dispc_pck_free_enable(1);

	/* Reset SDI PLL */
	REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
	udelay(1);	/* wait 2x PCLK */

	/* Lock SDI PLL */
	REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */

	/* Waiting for PLL lock request to complete */
	timeout = jiffies + msecs_to_jiffies(500);
	while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
		if (time_after_eq(jiffies, timeout)) {
			DSSERR("PLL lock request timed out\n");
			goto err1;
		}
	}

	/* Clearing PLL_GO bit */
	REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);

	/* Waiting for PLL to lock */
	timeout = jiffies + msecs_to_jiffies(500);
	while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
		if (time_after_eq(jiffies, timeout)) {
			DSSERR("PLL lock timed out\n");
			goto err1;
		}
	}

	dispc_lcd_enable_signal(1);

	/* Waiting for SDI reset to complete */
	timeout = jiffies + msecs_to_jiffies(500);
	while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
		if (time_after_eq(jiffies, timeout)) {
			DSSERR("SDI reset timed out\n");
			goto err2;
		}
	}

	return 0;

 err2:
	dispc_lcd_enable_signal(0);
 err1:
	/* Reset SDI PLL */
	REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */

	dispc_pck_free_enable(0);

	return -ETIMEDOUT;
}

void dss_sdi_disable(void)
{
	dispc_lcd_enable_signal(0);

	dispc_pck_free_enable(0);

	/* Reset SDI PLL */
	REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
}

231
const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
232
{
233
	return dss_generic_clk_source_names[clk_src];
234 235
}

236

237 238 239 240
void dss_dump_clocks(struct seq_file *s)
{
	unsigned long dpll4_ck_rate;
	unsigned long dpll4_m4_ck_rate;
241 242
	const char *fclk_name, *fclk_real_name;
	unsigned long fclk_rate;
243

244 245
	if (dss_runtime_get())
		return;
246 247 248

	seq_printf(s, "- DSS -\n");

249 250
	fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
	fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
251
	fclk_rate = clk_get_rate(dss.dss_clk);
252

253 254 255 256 257 258
	if (dss.dpll4_m4_ck) {
		dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
		dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);

		seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);

259
		if (cpu_is_omap3630() || cpu_is_omap44xx())
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275
			seq_printf(s, "%s (%s) = %lu / %lu  = %lu\n",
					fclk_name, fclk_real_name,
					dpll4_ck_rate,
					dpll4_ck_rate / dpll4_m4_ck_rate,
					fclk_rate);
		else
			seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
					fclk_name, fclk_real_name,
					dpll4_ck_rate,
					dpll4_ck_rate / dpll4_m4_ck_rate,
					fclk_rate);
	} else {
		seq_printf(s, "%s (%s) = %lu\n",
				fclk_name, fclk_real_name,
				fclk_rate);
	}
276

277
	dss_runtime_put();
278 279 280 281 282 283
}

void dss_dump_regs(struct seq_file *s)
{
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))

284 285
	if (dss_runtime_get())
		return;
286 287 288 289 290

	DUMPREG(DSS_REVISION);
	DUMPREG(DSS_SYSCONFIG);
	DUMPREG(DSS_SYSSTATUS);
	DUMPREG(DSS_CONTROL);
291 292 293 294 295 296 297

	if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
			OMAP_DISPLAY_TYPE_SDI) {
		DUMPREG(DSS_SDI_CONTROL);
		DUMPREG(DSS_PLL_CONTROL);
		DUMPREG(DSS_SDI_STATUS);
	}
298

299
	dss_runtime_put();
300 301 302
#undef DUMPREG
}

303
void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
304
{
305
	struct platform_device *dsidev;
306
	int b;
307
	u8 start, end;
308

309
	switch (clk_src) {
310
	case OMAP_DSS_CLK_SRC_FCK:
311 312
		b = 0;
		break;
313
	case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
314
		b = 1;
315 316
		dsidev = dsi_get_dsidev_from_id(0);
		dsi_wait_pll_hsdiv_dispc_active(dsidev);
317
		break;
318 319 320 321 322
	case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
		b = 2;
		dsidev = dsi_get_dsidev_from_id(1);
		dsi_wait_pll_hsdiv_dispc_active(dsidev);
		break;
323 324 325
	default:
		BUG();
	}
326

327 328 329
	dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);

	REG_FLD_MOD(DSS_CONTROL, b, start, end);	/* DISPC_CLK_SWITCH */
330 331 332 333

	dss.dispc_clk_source = clk_src;
}

334 335
void dss_select_dsi_clk_source(int dsi_module,
		enum omap_dss_clk_source clk_src)
336
{
337
	struct platform_device *dsidev;
338 339
	int b;

340
	switch (clk_src) {
341
	case OMAP_DSS_CLK_SRC_FCK:
342 343
		b = 0;
		break;
344
	case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
345
		BUG_ON(dsi_module != 0);
346
		b = 1;
347 348
		dsidev = dsi_get_dsidev_from_id(0);
		dsi_wait_pll_hsdiv_dsi_active(dsidev);
349
		break;
350 351 352 353 354 355
	case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
		BUG_ON(dsi_module != 1);
		b = 1;
		dsidev = dsi_get_dsidev_from_id(1);
		dsi_wait_pll_hsdiv_dsi_active(dsidev);
		break;
356 357 358
	default:
		BUG();
	}
359

360 361
	REG_FLD_MOD(DSS_CONTROL, b, 1, 1);	/* DSI_CLK_SWITCH */

362
	dss.dsi_clk_source[dsi_module] = clk_src;
363 364
}

365
void dss_select_lcd_clk_source(enum omap_channel channel,
366
		enum omap_dss_clk_source clk_src)
367
{
368
	struct platform_device *dsidev;
369 370 371 372 373 374
	int b, ix, pos;

	if (!dss_has_feature(FEAT_LCD_CLK_SRC))
		return;

	switch (clk_src) {
375
	case OMAP_DSS_CLK_SRC_FCK:
376 377
		b = 0;
		break;
378
	case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
379 380
		BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
		b = 1;
381 382
		dsidev = dsi_get_dsidev_from_id(0);
		dsi_wait_pll_hsdiv_dispc_active(dsidev);
383
		break;
384 385 386 387 388 389
	case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
		BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2);
		b = 1;
		dsidev = dsi_get_dsidev_from_id(1);
		dsi_wait_pll_hsdiv_dispc_active(dsidev);
		break;
390 391 392 393 394 395 396 397 398 399 400
	default:
		BUG();
	}

	pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12;
	REG_FLD_MOD(DSS_CONTROL, b, pos, pos);	/* LCDx_CLK_SWITCH */

	ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
	dss.lcd_clk_source[ix] = clk_src;
}

401
enum omap_dss_clk_source dss_get_dispc_clk_source(void)
402
{
403
	return dss.dispc_clk_source;
404 405
}

406
enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
407
{
408
	return dss.dsi_clk_source[dsi_module];
409 410
}

411
enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
412
{
413 414 415 416 417 418 419 420
	if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
		int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
		return dss.lcd_clk_source[ix];
	} else {
		/* LCD_CLK source is the same as DISPC_FCLK source for
		 * OMAP2 and OMAP3 */
		return dss.dispc_clk_source;
	}
421 422
}

423 424 425
/* calculate clock rates using dividers in cinfo */
int dss_calc_clock_rates(struct dss_clock_info *cinfo)
{
426 427
	if (dss.dpll4_m4_ck) {
		unsigned long prate;
428
		u16 fck_div_max = 16;
429

430 431 432 433
		if (cpu_is_omap3630() || cpu_is_omap44xx())
			fck_div_max = 32;

		if (cinfo->fck_div > fck_div_max || cinfo->fck_div == 0)
434
			return -EINVAL;
435

436
		prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
437

438 439 440 441
		cinfo->fck = prate / cinfo->fck_div;
	} else {
		if (cinfo->fck_div != 0)
			return -EINVAL;
442
		cinfo->fck = clk_get_rate(dss.dss_clk);
443
	}
444 445 446 447 448 449

	return 0;
}

int dss_set_clock_div(struct dss_clock_info *cinfo)
{
450 451 452
	if (dss.dpll4_m4_ck) {
		unsigned long prate;
		int r;
453 454 455 456 457 458 459

		prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
		DSSDBG("dpll4_m4 = %ld\n", prate);

		r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
		if (r)
			return r;
460 461 462
	} else {
		if (cinfo->fck_div != 0)
			return -EINVAL;
463 464 465 466 467 468 469 470 471
	}

	DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);

	return 0;
}

int dss_get_clock_div(struct dss_clock_info *cinfo)
{
472
	cinfo->fck = clk_get_rate(dss.dss_clk);
473

474
	if (dss.dpll4_m4_ck) {
475
		unsigned long prate;
476

477
		prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
478

479
		if (cpu_is_omap3630() || cpu_is_omap44xx())
480 481 482
			cinfo->fck_div = prate / (cinfo->fck);
		else
			cinfo->fck_div = prate / (cinfo->fck / 2);
483 484 485 486 487 488 489 490 491
	} else {
		cinfo->fck_div = 0;
	}

	return 0;
}

unsigned long dss_get_dpll4_rate(void)
{
492
	if (dss.dpll4_m4_ck)
493 494 495 496 497 498 499 500 501 502 503 504 505
		return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
	else
		return 0;
}

int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
		struct dss_clock_info *dss_cinfo,
		struct dispc_clock_info *dispc_cinfo)
{
	unsigned long prate;
	struct dss_clock_info best_dss;
	struct dispc_clock_info best_dispc;

506
	unsigned long fck, max_dss_fck;
507

508
	u16 fck_div, fck_div_max = 16;
509 510 511 512 513 514

	int match = 0;
	int min_fck_per_pck;

	prate = dss_get_dpll4_rate();

515
	max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
516

517
	fck = clk_get_rate(dss.dss_clk);
518 519 520 521 522 523 524 525 526 527 528 529
	if (req_pck == dss.cache_req_pck &&
			((cpu_is_omap34xx() && prate == dss.cache_prate) ||
			 dss.cache_dss_cinfo.fck == fck)) {
		DSSDBG("dispc clock info found from cache.\n");
		*dss_cinfo = dss.cache_dss_cinfo;
		*dispc_cinfo = dss.cache_dispc_cinfo;
		return 0;
	}

	min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;

	if (min_fck_per_pck &&
530
		req_pck * min_fck_per_pck > max_dss_fck) {
531 532 533 534 535 536 537 538 539 540
		DSSERR("Requested pixel clock not possible with the current "
				"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
				"the constraint off.\n");
		min_fck_per_pck = 0;
	}

retry:
	memset(&best_dss, 0, sizeof(best_dss));
	memset(&best_dispc, 0, sizeof(best_dispc));

541
	if (dss.dpll4_m4_ck == NULL) {
542 543
		struct dispc_clock_info cur_dispc;
		/* XXX can we change the clock on omap2? */
544
		fck = clk_get_rate(dss.dss_clk);
545 546 547 548 549 550 551 552 553 554 555
		fck_div = 1;

		dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
		match = 1;

		best_dss.fck = fck;
		best_dss.fck_div = fck_div;

		best_dispc = cur_dispc;

		goto found;
556 557 558 559 560
	} else {
		if (cpu_is_omap3630() || cpu_is_omap44xx())
			fck_div_max = 32;

		for (fck_div = fck_div_max; fck_div > 0; --fck_div) {
561 562
			struct dispc_clock_info cur_dispc;

563
			if (fck_div_max == 32)
564 565 566
				fck = prate / fck_div;
			else
				fck = prate / fck_div * 2;
567

568
			if (fck > max_dss_fck)
569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640
				continue;

			if (min_fck_per_pck &&
					fck < req_pck * min_fck_per_pck)
				continue;

			match = 1;

			dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);

			if (abs(cur_dispc.pck - req_pck) <
					abs(best_dispc.pck - req_pck)) {

				best_dss.fck = fck;
				best_dss.fck_div = fck_div;

				best_dispc = cur_dispc;

				if (cur_dispc.pck == req_pck)
					goto found;
			}
		}
	}

found:
	if (!match) {
		if (min_fck_per_pck) {
			DSSERR("Could not find suitable clock settings.\n"
					"Turning FCK/PCK constraint off and"
					"trying again.\n");
			min_fck_per_pck = 0;
			goto retry;
		}

		DSSERR("Could not find suitable clock settings.\n");

		return -EINVAL;
	}

	if (dss_cinfo)
		*dss_cinfo = best_dss;
	if (dispc_cinfo)
		*dispc_cinfo = best_dispc;

	dss.cache_req_pck = req_pck;
	dss.cache_prate = prate;
	dss.cache_dss_cinfo = best_dss;
	dss.cache_dispc_cinfo = best_dispc;

	return 0;
}

void dss_set_venc_output(enum omap_dss_venc_type type)
{
	int l = 0;

	if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
		l = 0;
	else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
		l = 1;
	else
		BUG();

	/* venc out selection. 0 = comp, 1 = svideo */
	REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
}

void dss_set_dac_pwrdn_bgz(bool enable)
{
	REG_FLD_MOD(DSS_CONTROL, enable, 5, 5);	/* DAC Power-Down Control */
}

641 642 643 644 645
void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi)
{
	REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15);	/* VENC_HDMI_SWITCH */
}

646 647 648 649 650 651 652 653 654 655 656
enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
{
	enum omap_display_type displays;

	displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
	if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
		return DSS_VENC_TV_CLK;

	return REG_GET(DSS_CONTROL, 15, 15);
}

657 658
static int dss_get_clocks(void)
{
659
	struct clk *clk;
660 661
	int r;

662 663 664 665
	clk = clk_get(&dss.pdev->dev, "fck");
	if (IS_ERR(clk)) {
		DSSERR("can't get clock fck\n");
		r = PTR_ERR(clk);
666
		goto err;
667
	}
668

669
	dss.dss_clk = clk;
670

671
	if (cpu_is_omap34xx()) {
672 673
		clk = clk_get(NULL, "dpll4_m4_ck");
		if (IS_ERR(clk)) {
674
			DSSERR("Failed to get dpll4_m4_ck\n");
675
			r = PTR_ERR(clk);
676 677 678
			goto err;
		}
	} else if (cpu_is_omap44xx()) {
679 680
		clk = clk_get(NULL, "dpll_per_m5x2_ck");
		if (IS_ERR(clk)) {
681
			DSSERR("Failed to get dpll_per_m5x2_ck\n");
682
			r = PTR_ERR(clk);
683 684 685
			goto err;
		}
	} else { /* omap24xx */
686
		clk = NULL;
687 688
	}

689
	dss.dpll4_m4_ck = clk;
690

691 692 693
	return 0;

err:
694 695
	if (dss.dss_clk)
		clk_put(dss.dss_clk);
696 697
	if (dss.dpll4_m4_ck)
		clk_put(dss.dpll4_m4_ck);
698 699 700 701 702 703

	return r;
}

static void dss_put_clocks(void)
{
704 705
	if (dss.dpll4_m4_ck)
		clk_put(dss.dpll4_m4_ck);
706
	clk_put(dss.dss_clk);
707 708
}

709
int dss_runtime_get(void)
710
{
711
	int r;
712

713
	DSSDBG("dss_runtime_get\n");
714

715 716 717
	r = pm_runtime_get_sync(&dss.pdev->dev);
	WARN_ON(r < 0);
	return r < 0 ? r : 0;
718 719
}

720
void dss_runtime_put(void)
721
{
722
	int r;
723

724
	DSSDBG("dss_runtime_put\n");
725

726
	r = pm_runtime_put_sync(&dss.pdev->dev);
727
	WARN_ON(r < 0);
728 729 730 731 732 733 734 735 736 737 738 739 740 741
}

/* DEBUGFS */
#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
void dss_debug_dump_clocks(struct seq_file *s)
{
	dss_dump_clocks(s);
	dispc_dump_clocks(s);
#ifdef CONFIG_OMAP2_DSS_DSI
	dsi_dump_clocks(s);
#endif
}
#endif

742 743 744
/* DSS HW IP initialisation */
static int omap_dsshw_probe(struct platform_device *pdev)
{
745 746
	struct resource *dss_mem;
	u32 rev;
747 748 749 750
	int r;

	dss.pdev = pdev;

751 752 753
	dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
	if (!dss_mem) {
		DSSERR("can't get IORESOURCE_MEM DSS\n");
754
		return -EINVAL;
755
	}
756

J
Julia Lawall 已提交
757 758
	dss.base = devm_ioremap(&pdev->dev, dss_mem->start,
				resource_size(dss_mem));
759 760
	if (!dss.base) {
		DSSERR("can't ioremap DSS\n");
761
		return -ENOMEM;
762 763
	}

764 765
	r = dss_get_clocks();
	if (r)
766
		return r;
767

768
	pm_runtime_enable(&pdev->dev);
769

770 771 772
	r = dss_runtime_get();
	if (r)
		goto err_runtime_get;
773 774 775 776 777 778 779 780 781 782 783 784 785 786

	/* Select DPLL */
	REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);

#ifdef CONFIG_OMAP2_DSS_VENC
	REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);	/* venc dac demen */
	REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);	/* venc clock 4x enable */
	REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);	/* venc clock mode = normal */
#endif
	dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
	dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
	dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
	dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
	dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
787

788 789 790 791 792 793 794 795 796 797 798 799
	r = dpi_init();
	if (r) {
		DSSERR("Failed to initialize DPI\n");
		goto err_dpi;
	}

	r = sdi_init();
	if (r) {
		DSSERR("Failed to initialize SDI\n");
		goto err_sdi;
	}

800 801 802 803
	rev = dss_read_reg(DSS_REVISION);
	printk(KERN_INFO "OMAP DSS rev %d.%d\n",
			FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));

804
	dss_runtime_put();
805

806
	return 0;
807 808 809
err_sdi:
	dpi_exit();
err_dpi:
810 811 812
	dss_runtime_put();
err_runtime_get:
	pm_runtime_disable(&pdev->dev);
813
	dss_put_clocks();
814 815 816 817 818
	return r;
}

static int omap_dsshw_remove(struct platform_device *pdev)
{
819 820
	dpi_exit();
	sdi_exit();
821

822
	pm_runtime_disable(&pdev->dev);
823 824

	dss_put_clocks();
825

826 827 828
	return 0;
}

829 830 831
static int dss_runtime_suspend(struct device *dev)
{
	dss_save_context();
832
	dss_set_min_bus_tput(dev, 0);
833 834 835 836 837
	return 0;
}

static int dss_runtime_resume(struct device *dev)
{
838 839 840 841 842 843 844 845 846 847 848 849
	int r;
	/*
	 * Set an arbitrarily high tput request to ensure OPP100.
	 * What we should really do is to make a request to stay in OPP100,
	 * without any tput requirements, but that is not currently possible
	 * via the PM layer.
	 */

	r = dss_set_min_bus_tput(dev, 1000000000);
	if (r)
		return r;

850
	dss_restore_context();
851 852 853 854 855 856 857 858
	return 0;
}

static const struct dev_pm_ops dss_pm_ops = {
	.runtime_suspend = dss_runtime_suspend,
	.runtime_resume = dss_runtime_resume,
};

859 860 861 862 863 864
static struct platform_driver omap_dsshw_driver = {
	.probe          = omap_dsshw_probe,
	.remove         = omap_dsshw_remove,
	.driver         = {
		.name   = "omapdss_dss",
		.owner  = THIS_MODULE,
865
		.pm	= &dss_pm_ops,
866 867 868 869 870 871 872 873 874 875 876 877
	},
};

int dss_init_platform_driver(void)
{
	return platform_driver_register(&omap_dsshw_driver);
}

void dss_uninit_platform_driver(void)
{
	return platform_driver_unregister(&omap_dsshw_driver);
}