exynos_tmu.c 26.2 KB
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/*
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 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
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 *
 *  Copyright (C) 2011 Samsung Electronics
 *  Donggeun Kim <dg77.kim@samsung.com>
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 *  Amit Daniel Kachhap <amit.kachhap@linaro.org>
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

#include <linux/clk.h>
#include <linux/io.h>
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#include <linux/interrupt.h>
#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include "exynos_thermal_common.h"
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#include "exynos_tmu.h"
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#include "exynos_tmu_data.h"
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/**
 * struct exynos_tmu_data : A structure to hold the private data of the TMU
	driver
 * @id: identifier of the one instance of the TMU controller.
 * @pdata: pointer to the tmu platform/configuration data
 * @base: base address of the single instance of the TMU controller.
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 * @base_second: base address of the common registers of the TMU controller.
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 * @irq: irq number of the TMU controller.
 * @soc: id of the SOC type.
 * @irq_work: pointer to the irq work structure.
 * @lock: lock to implement synchronization.
 * @clk: pointer to the clock structure.
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 * @clk_sec: pointer to the clock structure for accessing the base_second.
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 * @temp_error1: fused value of the first point trim.
 * @temp_error2: fused value of the second point trim.
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 * @regulator: pointer to the TMU regulator structure.
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 * @reg_conf: pointer to structure to register with core thermal.
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 * @tmu_initialize: SoC specific TMU initialization method
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 * @tmu_control: SoC specific TMU control method
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 * @tmu_read: SoC specific TMU temperature read method
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 * @tmu_set_emulation: SoC specific TMU emulation setting method
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 * @tmu_clear_irqs: SoC specific TMU interrupts clearing method
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 */
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struct exynos_tmu_data {
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	int id;
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	struct exynos_tmu_platform_data *pdata;
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	void __iomem *base;
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	void __iomem *base_second;
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	int irq;
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	enum soc_type soc;
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	struct work_struct irq_work;
	struct mutex lock;
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	struct clk *clk, *clk_sec;
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	u8 temp_error1, temp_error2;
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	struct regulator *regulator;
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	struct thermal_sensor_conf *reg_conf;
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	int (*tmu_initialize)(struct platform_device *pdev);
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	void (*tmu_control)(struct platform_device *pdev, bool on);
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	int (*tmu_read)(struct exynos_tmu_data *data);
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	void (*tmu_set_emulation)(struct exynos_tmu_data *data,
				  unsigned long temp);
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	void (*tmu_clear_irqs)(struct exynos_tmu_data *data);
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};

/*
 * TMU treats temperature as a mapped temperature code.
 * The temperature is converted differently depending on the calibration type.
 */
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static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
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{
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	struct exynos_tmu_platform_data *pdata = data->pdata;
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	int temp_code;

	switch (pdata->cal_type) {
	case TYPE_TWO_POINT_TRIMMING:
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		temp_code = (temp - pdata->first_point_trim) *
			(data->temp_error2 - data->temp_error1) /
			(pdata->second_point_trim - pdata->first_point_trim) +
			data->temp_error1;
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		break;
	case TYPE_ONE_POINT_TRIMMING:
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		temp_code = temp + data->temp_error1 - pdata->first_point_trim;
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		break;
	default:
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		temp_code = temp + pdata->default_temp_offset;
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		break;
	}
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	return temp_code;
}

/*
 * Calculate a temperature value from a temperature code.
 * The unit of the temperature is degree Celsius.
 */
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static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
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{
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	struct exynos_tmu_platform_data *pdata = data->pdata;
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	int temp;

	switch (pdata->cal_type) {
	case TYPE_TWO_POINT_TRIMMING:
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		temp = (temp_code - data->temp_error1) *
			(pdata->second_point_trim - pdata->first_point_trim) /
			(data->temp_error2 - data->temp_error1) +
			pdata->first_point_trim;
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		break;
	case TYPE_ONE_POINT_TRIMMING:
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		temp = temp_code - data->temp_error1 + pdata->first_point_trim;
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		break;
	default:
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		temp = temp_code - pdata->default_temp_offset;
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		break;
	}
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	return temp;
}

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static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
{
	struct exynos_tmu_platform_data *pdata = data->pdata;

	data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
	data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
				EXYNOS_TMU_TEMP_MASK);

	if (!data->temp_error1 ||
		(pdata->min_efuse_value > data->temp_error1) ||
		(data->temp_error1 > pdata->max_efuse_value))
		data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;

	if (!data->temp_error2)
		data->temp_error2 =
			(pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
			EXYNOS_TMU_TEMP_MASK;
}

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static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling)
{
	struct exynos_tmu_platform_data *pdata = data->pdata;
	int i;

	for (i = 0; i < pdata->non_hw_trigger_levels; i++) {
		u8 temp = pdata->trigger_levels[i];

		if (falling)
			temp -= pdata->threshold_falling;
		else
			threshold &= ~(0xff << 8 * i);

		threshold |= temp_to_code(data, temp) << 8 * i;
	}

	return threshold;
}

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static int exynos_tmu_initialize(struct platform_device *pdev)
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{
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	struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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	int ret;
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	mutex_lock(&data->lock);
	clk_enable(data->clk);
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	if (!IS_ERR(data->clk_sec))
		clk_enable(data->clk_sec);
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	ret = data->tmu_initialize(pdev);
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	clk_disable(data->clk);
	mutex_unlock(&data->lock);
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	if (!IS_ERR(data->clk_sec))
		clk_disable(data->clk_sec);
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	return ret;
}

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static u32 get_con_reg(struct exynos_tmu_data *data, u32 con)
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{
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	struct exynos_tmu_platform_data *pdata = data->pdata;

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	if (pdata->test_mux)
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		con |= (pdata->test_mux << EXYNOS4412_MUX_ADDR_SHIFT);
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	con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT);
	con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
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	con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
	con |= (pdata->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
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	if (pdata->noise_cancel_mode) {
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		con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT);
		con |= (pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT);
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	}

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	return con;
}

static void exynos_tmu_control(struct platform_device *pdev, bool on)
{
	struct exynos_tmu_data *data = platform_get_drvdata(pdev);

	mutex_lock(&data->lock);
	clk_enable(data->clk);
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	data->tmu_control(pdev, on);
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	clk_disable(data->clk);
	mutex_unlock(&data->lock);
}

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static int exynos4210_tmu_initialize(struct platform_device *pdev)
{
	struct exynos_tmu_data *data = platform_get_drvdata(pdev);
	struct exynos_tmu_platform_data *pdata = data->pdata;
	unsigned int status;
	int ret = 0, threshold_code, i;

	status = readb(data->base + EXYNOS_TMU_REG_STATUS);
	if (!status) {
		ret = -EBUSY;
		goto out;
	}

	sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));

	/* Write temperature code for threshold */
	threshold_code = temp_to_code(data, pdata->threshold);
	writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);

	for (i = 0; i < pdata->non_hw_trigger_levels; i++)
		writeb(pdata->trigger_levels[i], data->base +
		       EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);

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	data->tmu_clear_irqs(data);
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out:
	return ret;
}

static int exynos4412_tmu_initialize(struct platform_device *pdev)
{
	struct exynos_tmu_data *data = platform_get_drvdata(pdev);
	struct exynos_tmu_platform_data *pdata = data->pdata;
	unsigned int status, trim_info, con, ctrl, rising_threshold;
	int ret = 0, threshold_code, i;

	status = readb(data->base + EXYNOS_TMU_REG_STATUS);
	if (!status) {
		ret = -EBUSY;
		goto out;
	}

	if (data->soc == SOC_ARCH_EXYNOS3250 ||
	    data->soc == SOC_ARCH_EXYNOS4412 ||
	    data->soc == SOC_ARCH_EXYNOS5250) {
		if (data->soc == SOC_ARCH_EXYNOS3250) {
			ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1);
			ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
			writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
		}
		ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2);
		ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
		writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
	}

	/* On exynos5420 the triminfo register is in the shared space */
	if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
		trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO);
	else
		trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);

	sanitize_temp_error(data, trim_info);

	/* Write temperature code for rising and falling threshold */
	rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE);
	rising_threshold = get_th_reg(data, rising_threshold, false);
	writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
	writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL);

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	data->tmu_clear_irqs(data);
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	/* if last threshold limit is also present */
	i = pdata->max_trigger_level - 1;
	if (pdata->trigger_levels[i] && pdata->trigger_type[i] == HW_TRIP) {
		threshold_code = temp_to_code(data, pdata->trigger_levels[i]);
		/* 1-4 level to be assigned in th0 reg */
		rising_threshold &= ~(0xff << 8 * i);
		rising_threshold |= threshold_code << 8 * i;
		writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
		con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
		con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
		writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
	}
out:
	return ret;
}

static int exynos5440_tmu_initialize(struct platform_device *pdev)
{
	struct exynos_tmu_data *data = platform_get_drvdata(pdev);
	struct exynos_tmu_platform_data *pdata = data->pdata;
	unsigned int trim_info = 0, con, rising_threshold;
	int ret = 0, threshold_code, i;

	/*
	 * For exynos5440 soc triminfo value is swapped between TMU0 and
	 * TMU2, so the below logic is needed.
	 */
	switch (data->id) {
	case 0:
		trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET +
				 EXYNOS5440_TMU_S0_7_TRIM);
		break;
	case 1:
		trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM);
		break;
	case 2:
		trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET +
				  EXYNOS5440_TMU_S0_7_TRIM);
	}
	sanitize_temp_error(data, trim_info);

	/* Write temperature code for rising and falling threshold */
	rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0);
	rising_threshold = get_th_reg(data, rising_threshold, false);
	writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0);
	writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1);

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	data->tmu_clear_irqs(data);
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	/* if last threshold limit is also present */
	i = pdata->max_trigger_level - 1;
	if (pdata->trigger_levels[i] && pdata->trigger_type[i] == HW_TRIP) {
		threshold_code = temp_to_code(data, pdata->trigger_levels[i]);
		/* 5th level to be assigned in th2 reg */
		rising_threshold =
			threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;
		writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2);
		con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL);
		con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
		writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
	}
	/* Clear the PMIN in the common TMU register */
	if (!data->id)
		writel(0, data->base_second + EXYNOS5440_TMU_PMIN);
	return ret;
}

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static void exynos4210_tmu_control(struct platform_device *pdev, bool on)
{
	struct exynos_tmu_data *data = platform_get_drvdata(pdev);
	struct exynos_tmu_platform_data *pdata = data->pdata;
	unsigned int con, interrupt_en;

	con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));

	if (on) {
		con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
		interrupt_en =
			pdata->trigger_enable[3] << EXYNOS_TMU_INTEN_RISE3_SHIFT |
			pdata->trigger_enable[2] << EXYNOS_TMU_INTEN_RISE2_SHIFT |
			pdata->trigger_enable[1] << EXYNOS_TMU_INTEN_RISE1_SHIFT |
			pdata->trigger_enable[0] << EXYNOS_TMU_INTEN_RISE0_SHIFT;
		if (TMU_SUPPORTS(pdata, FALLING_TRIP))
			interrupt_en |=
				interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
	} else {
		con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
		interrupt_en = 0; /* Disable all interrupts */
	}
	writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
	writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
}

static void exynos5440_tmu_control(struct platform_device *pdev, bool on)
{
	struct exynos_tmu_data *data = platform_get_drvdata(pdev);
	struct exynos_tmu_platform_data *pdata = data->pdata;
	unsigned int con, interrupt_en;

	con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL));

	if (on) {
		con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
		interrupt_en =
			pdata->trigger_enable[3] << EXYNOS5440_TMU_INTEN_RISE3_SHIFT |
			pdata->trigger_enable[2] << EXYNOS5440_TMU_INTEN_RISE2_SHIFT |
			pdata->trigger_enable[1] << EXYNOS5440_TMU_INTEN_RISE1_SHIFT |
			pdata->trigger_enable[0] << EXYNOS5440_TMU_INTEN_RISE0_SHIFT;
		if (TMU_SUPPORTS(pdata, FALLING_TRIP))
			interrupt_en |=
				interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT;
	} else {
		con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
		interrupt_en = 0; /* Disable all interrupts */
	}
	writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN);
	writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
}

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static int exynos_tmu_read(struct exynos_tmu_data *data)
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{
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	int ret;
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	mutex_lock(&data->lock);
	clk_enable(data->clk);
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	ret = data->tmu_read(data);
	if (ret >= 0)
		ret = code_to_temp(data, ret);
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	clk_disable(data->clk);
	mutex_unlock(&data->lock);

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	return ret;
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}

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#ifdef CONFIG_THERMAL_EMULATION
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static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val,
			    unsigned long temp)
{
	struct exynos_tmu_platform_data *pdata = data->pdata;

	if (temp) {
		temp /= MCELSIUS;

		if (TMU_SUPPORTS(pdata, EMUL_TIME)) {
			val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT);
			val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT);
		}
		val &= ~(EXYNOS_EMUL_DATA_MASK << EXYNOS_EMUL_DATA_SHIFT);
		val |= (temp_to_code(data, temp) << EXYNOS_EMUL_DATA_SHIFT) |
			EXYNOS_EMUL_ENABLE;
	} else {
		val &= ~EXYNOS_EMUL_ENABLE;
	}

	return val;
}

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static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data,
					 unsigned long temp)
{
	unsigned int val;
	u32 emul_con;

	if (data->soc == SOC_ARCH_EXYNOS5260)
		emul_con = EXYNOS5260_EMUL_CON;
	else
		emul_con = EXYNOS_EMUL_CON;

	val = readl(data->base + emul_con);
	val = get_emul_con_reg(data, val, temp);
	writel(val, data->base + emul_con);
}

static void exynos5440_tmu_set_emulation(struct exynos_tmu_data *data,
					 unsigned long temp)
{
	unsigned int val;

	val = readl(data->base + EXYNOS5440_TMU_S0_7_DEBUG);
	val = get_emul_con_reg(data, val, temp);
	writel(val, data->base + EXYNOS5440_TMU_S0_7_DEBUG);
}

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static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
{
	struct exynos_tmu_data *data = drv_data;
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	struct exynos_tmu_platform_data *pdata = data->pdata;
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	int ret = -EINVAL;

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	if (!TMU_SUPPORTS(pdata, EMULATION))
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		goto out;

	if (temp && temp < MCELSIUS)
		goto out;

	mutex_lock(&data->lock);
	clk_enable(data->clk);
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	data->tmu_set_emulation(data, temp);
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	clk_disable(data->clk);
	mutex_unlock(&data->lock);
	return 0;
out:
	return ret;
}
#else
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#define exynos4412_tmu_set_emulation NULL
#define exynos5440_tmu_set_emulation NULL
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static int exynos_tmu_set_emulation(void *drv_data,	unsigned long temp)
	{ return -EINVAL; }
#endif/*CONFIG_THERMAL_EMULATION*/

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static int exynos4210_tmu_read(struct exynos_tmu_data *data)
{
	int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);

	/* "temp_code" should range between 75 and 175 */
	return (ret < 75 || ret > 175) ? -ENODATA : ret;
}

static int exynos4412_tmu_read(struct exynos_tmu_data *data)
{
	return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
}

static int exynos5440_tmu_read(struct exynos_tmu_data *data)
{
	return readb(data->base + EXYNOS5440_TMU_S0_7_TEMP);
}

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static void exynos_tmu_work(struct work_struct *work)
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{
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	struct exynos_tmu_data *data = container_of(work,
			struct exynos_tmu_data, irq_work);
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	unsigned int val_type;
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	if (!IS_ERR(data->clk_sec))
		clk_enable(data->clk_sec);
531
	/* Find which sensor generated this interrupt */
532 533
	if (data->soc == SOC_ARCH_EXYNOS5440) {
		val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS);
534 535 536
		if (!((val_type >> data->id) & 0x1))
			goto out;
	}
537 538
	if (!IS_ERR(data->clk_sec))
		clk_disable(data->clk_sec);
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540
	exynos_report_trigger(data->reg_conf);
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	mutex_lock(&data->lock);
	clk_enable(data->clk);
543

544
	/* TODO: take action based on particular interrupt */
545
	data->tmu_clear_irqs(data);
546

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	clk_disable(data->clk);
	mutex_unlock(&data->lock);
549
out:
550
	enable_irq(data->irq);
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}

553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586
static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data)
{
	unsigned int val_irq;
	u32 tmu_intstat, tmu_intclear;

	if (data->soc == SOC_ARCH_EXYNOS5260) {
		tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT;
		tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR;
	} else {
		tmu_intstat = EXYNOS_TMU_REG_INTSTAT;
		tmu_intclear = EXYNOS_TMU_REG_INTCLEAR;
	}

	val_irq = readl(data->base + tmu_intstat);
	/*
	 * Clear the interrupts.  Please note that the documentation for
	 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly
	 * states that INTCLEAR register has a different placing of bits
	 * responsible for FALL IRQs than INTSTAT register.  Exynos5420
	 * and Exynos5440 documentation is correct (Exynos4210 doesn't
	 * support FALL IRQs at all).
	 */
	writel(val_irq, data->base + tmu_intclear);
}

static void exynos5440_tmu_clear_irqs(struct exynos_tmu_data *data)
{
	unsigned int val_irq;

	val_irq = readl(data->base + EXYNOS5440_TMU_S0_7_IRQ);
	/* clear the interrupts */
	writel(val_irq, data->base + EXYNOS5440_TMU_S0_7_IRQ);
}

587
static irqreturn_t exynos_tmu_irq(int irq, void *id)
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{
589
	struct exynos_tmu_data *data = id;
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	disable_irq_nosync(irq);
	schedule_work(&data->irq_work);

	return IRQ_HANDLED;
}
596 597

static const struct of_device_id exynos_tmu_match[] = {
598 599 600 601
	{
		.compatible = "samsung,exynos3250-tmu",
		.data = (void *)EXYNOS3250_TMU_DRV_DATA,
	},
602 603 604 605
	{
		.compatible = "samsung,exynos4210-tmu",
		.data = (void *)EXYNOS4210_TMU_DRV_DATA,
	},
606 607
	{
		.compatible = "samsung,exynos4412-tmu",
608
		.data = (void *)EXYNOS4412_TMU_DRV_DATA,
609
	},
610 611
	{
		.compatible = "samsung,exynos5250-tmu",
612
		.data = (void *)EXYNOS5250_TMU_DRV_DATA,
613
	},
614 615 616 617
	{
		.compatible = "samsung,exynos5260-tmu",
		.data = (void *)EXYNOS5260_TMU_DRV_DATA,
	},
618 619 620 621 622 623 624 625
	{
		.compatible = "samsung,exynos5420-tmu",
		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
	},
	{
		.compatible = "samsung,exynos5420-tmu-ext-triminfo",
		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
	},
626 627 628 629
	{
		.compatible = "samsung,exynos5440-tmu",
		.data = (void *)EXYNOS5440_TMU_DRV_DATA,
	},
630 631 632 633 634
	{},
};
MODULE_DEVICE_TABLE(of, exynos_tmu_match);

static inline struct  exynos_tmu_platform_data *exynos_get_driver_data(
635
			struct platform_device *pdev, int id)
636
{
637 638
	struct  exynos_tmu_init_data *data_table;
	struct exynos_tmu_platform_data *tmu_data;
639 640 641 642 643 644 645 646 647 648
	const struct of_device_id *match;

	match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
	if (!match)
		return NULL;
	data_table = (struct exynos_tmu_init_data *) match->data;
	if (!data_table || id >= data_table->tmu_count)
		return NULL;
	tmu_data = data_table->tmu_data;
	return (struct exynos_tmu_platform_data *) (tmu_data + id);
649
}
650

651
static int exynos_map_dt_data(struct platform_device *pdev)
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{
653 654 655
	struct exynos_tmu_data *data = platform_get_drvdata(pdev);
	struct exynos_tmu_platform_data *pdata;
	struct resource res;
656
	int ret;
657

658
	if (!data || !pdev->dev.of_node)
659
		return -ENODEV;
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661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676
	/*
	 * Try enabling the regulator if found
	 * TODO: Add regulator as an SOC feature, so that regulator enable
	 * is a compulsory call.
	 */
	data->regulator = devm_regulator_get(&pdev->dev, "vtmu");
	if (!IS_ERR(data->regulator)) {
		ret = regulator_enable(data->regulator);
		if (ret) {
			dev_err(&pdev->dev, "failed to enable vtmu\n");
			return ret;
		}
	} else {
		dev_info(&pdev->dev, "Regulator node (vtmu) not found\n");
	}

677 678 679
	data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl");
	if (data->id < 0)
		data->id = 0;
680

681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698
	data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
	if (data->irq <= 0) {
		dev_err(&pdev->dev, "failed to get IRQ\n");
		return -ENODEV;
	}

	if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
		dev_err(&pdev->dev, "failed to get Resource 0\n");
		return -ENODEV;
	}

	data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
	if (!data->base) {
		dev_err(&pdev->dev, "Failed to ioremap memory\n");
		return -EADDRNOTAVAIL;
	}

	pdata = exynos_get_driver_data(pdev, data->id);
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	if (!pdata) {
		dev_err(&pdev->dev, "No platform init data supplied.\n");
		return -ENODEV;
	}
703
	data->pdata = pdata;
704 705 706 707
	/*
	 * Check if the TMU shares some registers and then try to map the
	 * memory of common registers.
	 */
708
	if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
709 710 711 712 713 714 715
		return 0;

	if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
		dev_err(&pdev->dev, "failed to get Resource 1\n");
		return -ENODEV;
	}

716
	data->base_second = devm_ioremap(&pdev->dev, res.start,
717
					resource_size(&res));
718
	if (!data->base_second) {
719 720 721
		dev_err(&pdev->dev, "Failed to ioremap memory\n");
		return -ENOMEM;
	}
722 723 724 725 726 727 728 729 730 731 732

	return 0;
}

static int exynos_tmu_probe(struct platform_device *pdev)
{
	struct exynos_tmu_data *data;
	struct exynos_tmu_platform_data *pdata;
	struct thermal_sensor_conf *sensor_conf;
	int ret, i;

733 734
	data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
					GFP_KERNEL);
735
	if (!data)
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		return -ENOMEM;

738 739
	platform_set_drvdata(pdev, data);
	mutex_init(&data->lock);
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741 742 743
	ret = exynos_map_dt_data(pdev);
	if (ret)
		return ret;
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745
	pdata = data->pdata;
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746

747
	INIT_WORK(&data->irq_work, exynos_tmu_work);
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748

749
	data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
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750 751
	if (IS_ERR(data->clk)) {
		dev_err(&pdev->dev, "Failed to get clock\n");
752
		return  PTR_ERR(data->clk);
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	}

755 756 757 758 759 760 761 762 763 764 765 766 767 768
	data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
	if (IS_ERR(data->clk_sec)) {
		if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
			dev_err(&pdev->dev, "Failed to get triminfo clock\n");
			return PTR_ERR(data->clk_sec);
		}
	} else {
		ret = clk_prepare(data->clk_sec);
		if (ret) {
			dev_err(&pdev->dev, "Failed to get clock\n");
			return ret;
		}
	}

769
	ret = clk_prepare(data->clk);
770 771 772 773
	if (ret) {
		dev_err(&pdev->dev, "Failed to get clock\n");
		goto err_clk_sec;
	}
774

775 776 777 778 779
	data->soc = pdata->type;

	switch (data->soc) {
	case SOC_ARCH_EXYNOS4210:
		data->tmu_initialize = exynos4210_tmu_initialize;
780
		data->tmu_control = exynos4210_tmu_control;
781
		data->tmu_read = exynos4210_tmu_read;
782
		data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
783 784 785 786 787 788 789 790
		break;
	case SOC_ARCH_EXYNOS3250:
	case SOC_ARCH_EXYNOS4412:
	case SOC_ARCH_EXYNOS5250:
	case SOC_ARCH_EXYNOS5260:
	case SOC_ARCH_EXYNOS5420:
	case SOC_ARCH_EXYNOS5420_TRIMINFO:
		data->tmu_initialize = exynos4412_tmu_initialize;
791
		data->tmu_control = exynos4210_tmu_control;
792
		data->tmu_read = exynos4412_tmu_read;
793
		data->tmu_set_emulation = exynos4412_tmu_set_emulation;
794
		data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
795 796 797
		break;
	case SOC_ARCH_EXYNOS5440:
		data->tmu_initialize = exynos5440_tmu_initialize;
798
		data->tmu_control = exynos5440_tmu_control;
799
		data->tmu_read = exynos5440_tmu_read;
800
		data->tmu_set_emulation = exynos5440_tmu_set_emulation;
801
		data->tmu_clear_irqs = exynos5440_tmu_clear_irqs;
802 803
		break;
	default:
804 805 806 807 808 809
		ret = -EINVAL;
		dev_err(&pdev->dev, "Platform not supported\n");
		goto err_clk;
	}

	ret = exynos_tmu_initialize(pdev);
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	if (ret) {
		dev_err(&pdev->dev, "Failed to initialize TMU\n");
		goto err_clk;
	}

815
	exynos_tmu_control(pdev, true);
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817 818 819 820 821 822 823 824 825 826 827 828 829
	/* Allocate a structure to register with the exynos core thermal */
	sensor_conf = devm_kzalloc(&pdev->dev,
				sizeof(struct thermal_sensor_conf), GFP_KERNEL);
	if (!sensor_conf) {
		ret = -ENOMEM;
		goto err_clk;
	}
	sprintf(sensor_conf->name, "therm_zone%d", data->id);
	sensor_conf->read_temperature = (int (*)(void *))exynos_tmu_read;
	sensor_conf->write_emul_temp =
		(int (*)(void *, unsigned long))exynos_tmu_set_emulation;
	sensor_conf->driver_data = data;
	sensor_conf->trip_data.trip_count = pdata->trigger_enable[0] +
830 831
			pdata->trigger_enable[1] + pdata->trigger_enable[2]+
			pdata->trigger_enable[3];
832

833 834
	for (i = 0; i < sensor_conf->trip_data.trip_count; i++) {
		sensor_conf->trip_data.trip_val[i] =
835
			pdata->threshold + pdata->trigger_levels[i];
836
		sensor_conf->trip_data.trip_type[i] =
837 838
					pdata->trigger_type[i];
	}
839

840
	sensor_conf->trip_data.trigger_falling = pdata->threshold_falling;
841

842
	sensor_conf->cooling_data.freq_clip_count = pdata->freq_tab_count;
843
	for (i = 0; i < pdata->freq_tab_count; i++) {
844
		sensor_conf->cooling_data.freq_data[i].freq_clip_max =
845
					pdata->freq_tab[i].freq_clip_max;
846
		sensor_conf->cooling_data.freq_data[i].temp_level =
847 848
					pdata->freq_tab[i].temp_level;
	}
849 850 851
	sensor_conf->dev = &pdev->dev;
	/* Register the sensor with thermal management interface */
	ret = exynos_register_thermal(sensor_conf);
852 853 854 855
	if (ret) {
		dev_err(&pdev->dev, "Failed to register thermal interface\n");
		goto err_clk;
	}
856 857 858 859 860 861 862 863
	data->reg_conf = sensor_conf;

	ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
		IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
	if (ret) {
		dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
		goto err_clk;
	}
864

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865 866
	return 0;
err_clk:
867
	clk_unprepare(data->clk);
868 869 870
err_clk_sec:
	if (!IS_ERR(data->clk_sec))
		clk_unprepare(data->clk_sec);
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871 872 873
	return ret;
}

874
static int exynos_tmu_remove(struct platform_device *pdev)
D
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875
{
876
	struct exynos_tmu_data *data = platform_get_drvdata(pdev);
D
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877

878
	exynos_unregister_thermal(data->reg_conf);
879

880 881
	exynos_tmu_control(pdev, false);

882
	clk_unprepare(data->clk);
883 884
	if (!IS_ERR(data->clk_sec))
		clk_unprepare(data->clk_sec);
D
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885

886 887 888
	if (!IS_ERR(data->regulator))
		regulator_disable(data->regulator);

D
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889 890 891
	return 0;
}

892
#ifdef CONFIG_PM_SLEEP
893
static int exynos_tmu_suspend(struct device *dev)
D
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894
{
895
	exynos_tmu_control(to_platform_device(dev), false);
D
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896 897 898 899

	return 0;
}

900
static int exynos_tmu_resume(struct device *dev)
D
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901
{
902 903
	struct platform_device *pdev = to_platform_device(dev);

904 905
	exynos_tmu_initialize(pdev);
	exynos_tmu_control(pdev, true);
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906 907 908

	return 0;
}
909

910 911 912
static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
			 exynos_tmu_suspend, exynos_tmu_resume);
#define EXYNOS_TMU_PM	(&exynos_tmu_pm)
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913
#else
914
#define EXYNOS_TMU_PM	NULL
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915 916
#endif

917
static struct platform_driver exynos_tmu_driver = {
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918
	.driver = {
919
		.name   = "exynos-tmu",
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920
		.owner  = THIS_MODULE,
921
		.pm     = EXYNOS_TMU_PM,
922
		.of_match_table = exynos_tmu_match,
D
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923
	},
924
	.probe = exynos_tmu_probe,
925
	.remove	= exynos_tmu_remove,
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926 927
};

928
module_platform_driver(exynos_tmu_driver);
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929

930
MODULE_DESCRIPTION("EXYNOS TMU Driver");
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931 932
MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
MODULE_LICENSE("GPL");
933
MODULE_ALIAS("platform:exynos-tmu");