xhci-mem.c 75.1 KB
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/*
 * xHCI host controller driver
 *
 * Copyright (C) 2008 Intel Corp.
 *
 * Author: Sarah Sharp
 * Some code borrowed from the Linux EHCI driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/usb.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/dmapool.h>
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#include <linux/dma-mapping.h>
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#include "xhci.h"
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#include "xhci-trace.h"
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/*
 * Allocates a generic ring segment from the ring pool, sets the dma address,
 * initializes the segment to zero, and sets the private next pointer to NULL.
 *
 * Section 4.11.1.1:
 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
 */
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static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
					unsigned int cycle_state, gfp_t flags)
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{
	struct xhci_segment *seg;
	dma_addr_t	dma;
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	int		i;
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	seg = kzalloc(sizeof *seg, flags);
	if (!seg)
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		return NULL;
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	seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
	if (!seg->trbs) {
		kfree(seg);
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		return NULL;
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	}

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	memset(seg->trbs, 0, TRB_SEGMENT_SIZE);
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	/* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
	if (cycle_state == 0) {
		for (i = 0; i < TRBS_PER_SEGMENT; i++)
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			seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE);
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	}
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	seg->dma = dma;
	seg->next = NULL;

	return seg;
}

static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
{
	if (seg->trbs) {
		dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
		seg->trbs = NULL;
	}
	kfree(seg);
}

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static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
				struct xhci_segment *first)
{
	struct xhci_segment *seg;

	seg = first->next;
	while (seg != first) {
		struct xhci_segment *next = seg->next;
		xhci_segment_free(xhci, seg);
		seg = next;
	}
	xhci_segment_free(xhci, first);
}

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/*
 * Make the prev segment point to the next segment.
 *
 * Change the last TRB in the prev segment to be a Link TRB which points to the
 * DMA address of the next segment.  The caller needs to set any Link TRB
 * related flags, such as End TRB, Toggle Cycle, and no snoop.
 */
static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
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		struct xhci_segment *next, enum xhci_ring_type type)
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{
	u32 val;

	if (!prev || !next)
		return;
	prev->next = next;
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	if (type != TYPE_EVENT) {
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		prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
			cpu_to_le64(next->dma);
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		/* Set the last TRB in the segment to have a TRB type ID of Link TRB */
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		val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
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		val &= ~TRB_TYPE_BITMASK;
		val |= TRB_TYPE(TRB_LINK);
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		/* Always set the chain bit with 0.95 hardware */
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		/* Set chain bit for isoc rings on AMD 0.96 host */
		if (xhci_link_trb_quirk(xhci) ||
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				(type == TYPE_ISOC &&
				 (xhci->quirks & XHCI_AMD_0x96_HOST)))
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			val |= TRB_CHAIN;
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		prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
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	}
}

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/*
 * Link the ring to the new segments.
 * Set Toggle Cycle for the new ring if needed.
 */
static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
		struct xhci_segment *first, struct xhci_segment *last,
		unsigned int num_segs)
{
	struct xhci_segment *next;

	if (!ring || !first || !last)
		return;

	next = ring->enq_seg->next;
	xhci_link_segments(xhci, ring->enq_seg, first, ring->type);
	xhci_link_segments(xhci, last, next, ring->type);
	ring->num_segs += num_segs;
	ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs;

	if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) {
		ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
			&= ~cpu_to_le32(LINK_TOGGLE);
		last->trbs[TRBS_PER_SEGMENT-1].link.control
			|= cpu_to_le32(LINK_TOGGLE);
		ring->last_seg = last;
	}
}

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/*
 * We need a radix tree for mapping physical addresses of TRBs to which stream
 * ID they belong to.  We need to do this because the host controller won't tell
 * us which stream ring the TRB came from.  We could store the stream ID in an
 * event data TRB, but that doesn't help us for the cancellation case, since the
 * endpoint may stop before it reaches that event data TRB.
 *
 * The radix tree maps the upper portion of the TRB DMA address to a ring
 * segment that has the same upper portion of DMA addresses.  For example, say I
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 * have segments of size 1KB, that are always 1KB aligned.  A segment may
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 * start at 0x10c91000 and end at 0x10c913f0.  If I use the upper 10 bits, the
 * key to the stream ID is 0x43244.  I can use the DMA address of the TRB to
 * pass the radix tree a key to get the right stream ID:
 *
 *	0x10c90fff >> 10 = 0x43243
 *	0x10c912c0 >> 10 = 0x43244
 *	0x10c91400 >> 10 = 0x43245
 *
 * Obviously, only those TRBs with DMA addresses that are within the segment
 * will make the radix tree return the stream ID for that ring.
 *
 * Caveats for the radix tree:
 *
 * The radix tree uses an unsigned long as a key pair.  On 32-bit systems, an
 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
 * 64-bits.  Since we only request 32-bit DMA addresses, we can use that as the
 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
 * PCI DMA addresses on a 64-bit system).  There might be a problem on 32-bit
 * extended systems (where the DMA address can be bigger than 32-bits),
 * if we allow the PCI dma mask to be bigger than 32-bits.  So don't do that.
 */
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static int xhci_insert_segment_mapping(struct radix_tree_root *trb_address_map,
		struct xhci_ring *ring,
		struct xhci_segment *seg,
		gfp_t mem_flags)
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{
	unsigned long key;
	int ret;

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	key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
	/* Skip any segments that were already added. */
	if (radix_tree_lookup(trb_address_map, key))
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		return 0;

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	ret = radix_tree_maybe_preload(mem_flags);
	if (ret)
		return ret;
	ret = radix_tree_insert(trb_address_map,
			key, ring);
	radix_tree_preload_end();
	return ret;
}
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static void xhci_remove_segment_mapping(struct radix_tree_root *trb_address_map,
		struct xhci_segment *seg)
{
	unsigned long key;

	key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
	if (radix_tree_lookup(trb_address_map, key))
		radix_tree_delete(trb_address_map, key);
}

static int xhci_update_stream_segment_mapping(
		struct radix_tree_root *trb_address_map,
		struct xhci_ring *ring,
		struct xhci_segment *first_seg,
		struct xhci_segment *last_seg,
		gfp_t mem_flags)
{
	struct xhci_segment *seg;
	struct xhci_segment *failed_seg;
	int ret;

	if (WARN_ON_ONCE(trb_address_map == NULL))
		return 0;

	seg = first_seg;
	do {
		ret = xhci_insert_segment_mapping(trb_address_map,
				ring, seg, mem_flags);
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		if (ret)
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			goto remove_streams;
		if (seg == last_seg)
			return 0;
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		seg = seg->next;
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	} while (seg != first_seg);
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	return 0;
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remove_streams:
	failed_seg = seg;
	seg = first_seg;
	do {
		xhci_remove_segment_mapping(trb_address_map, seg);
		if (seg == failed_seg)
			return ret;
		seg = seg->next;
	} while (seg != first_seg);

	return ret;
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}

static void xhci_remove_stream_mapping(struct xhci_ring *ring)
{
	struct xhci_segment *seg;

	if (WARN_ON_ONCE(ring->trb_address_map == NULL))
		return;

	seg = ring->first_seg;
	do {
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		xhci_remove_segment_mapping(ring->trb_address_map, seg);
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		seg = seg->next;
	} while (seg != ring->first_seg);
}

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static int xhci_update_stream_mapping(struct xhci_ring *ring, gfp_t mem_flags)
{
	return xhci_update_stream_segment_mapping(ring->trb_address_map, ring,
			ring->first_seg, ring->last_seg, mem_flags);
}

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/* XXX: Do we need the hcd structure in all these functions? */
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void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
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{
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	if (!ring)
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		return;
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	if (ring->first_seg) {
		if (ring->type == TYPE_STREAM)
			xhci_remove_stream_mapping(ring);
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		xhci_free_segments_for_ring(xhci, ring->first_seg);
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	}
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	kfree(ring);
}

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static void xhci_initialize_ring_info(struct xhci_ring *ring,
					unsigned int cycle_state)
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{
	/* The ring is empty, so the enqueue pointer == dequeue pointer */
	ring->enqueue = ring->first_seg->trbs;
	ring->enq_seg = ring->first_seg;
	ring->dequeue = ring->enqueue;
	ring->deq_seg = ring->first_seg;
	/* The ring is initialized to 0. The producer must write 1 to the cycle
	 * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
	 * compare CCS to the cycle bit to check ownership, so CCS = 1.
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	 *
	 * New rings are initialized with cycle state equal to 1; if we are
	 * handling ring expansion, set the cycle state equal to the old ring.
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	 */
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	ring->cycle_state = cycle_state;
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	/* Not necessary for new rings, but needed for re-initialized rings */
	ring->enq_updates = 0;
	ring->deq_updates = 0;
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	/*
	 * Each segment has a link TRB, and leave an extra TRB for SW
	 * accounting purpose
	 */
	ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
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}

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/* Allocate segments and link them for a ring */
static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
		struct xhci_segment **first, struct xhci_segment **last,
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		unsigned int num_segs, unsigned int cycle_state,
		enum xhci_ring_type type, gfp_t flags)
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{
	struct xhci_segment *prev;

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	prev = xhci_segment_alloc(xhci, cycle_state, flags);
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	if (!prev)
		return -ENOMEM;
	num_segs--;

	*first = prev;
	while (num_segs > 0) {
		struct xhci_segment	*next;

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		next = xhci_segment_alloc(xhci, cycle_state, flags);
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		if (!next) {
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			prev = *first;
			while (prev) {
				next = prev->next;
				xhci_segment_free(xhci, prev);
				prev = next;
			}
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			return -ENOMEM;
		}
		xhci_link_segments(xhci, prev, next, type);

		prev = next;
		num_segs--;
	}
	xhci_link_segments(xhci, prev, *first, type);
	*last = prev;

	return 0;
}

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/**
 * Create a new ring with zero or more segments.
 *
 * Link each segment together into a ring.
 * Set the end flag and the cycle toggle bit on the last segment.
 * See section 4.9.1 and figures 15 and 16.
 */
static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
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		unsigned int num_segs, unsigned int cycle_state,
		enum xhci_ring_type type, gfp_t flags)
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{
	struct xhci_ring	*ring;
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	int ret;
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	ring = kzalloc(sizeof *(ring), flags);
	if (!ring)
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		return NULL;
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	ring->num_segs = num_segs;
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	INIT_LIST_HEAD(&ring->td_list);
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	ring->type = type;
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	if (num_segs == 0)
		return ring;

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	ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
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			&ring->last_seg, num_segs, cycle_state, type, flags);
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	if (ret)
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		goto fail;

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	/* Only event ring does not use link TRB */
	if (type != TYPE_EVENT) {
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		/* See section 4.9.2.1 and 6.4.4.1 */
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		ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |=
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			cpu_to_le32(LINK_TOGGLE);
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	}
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	xhci_initialize_ring_info(ring, cycle_state);
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	return ring;

fail:
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	kfree(ring);
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	return NULL;
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}

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void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
		struct xhci_virt_device *virt_dev,
		unsigned int ep_index)
{
	int rings_cached;

	rings_cached = virt_dev->num_rings_cached;
	if (rings_cached < XHCI_MAX_RINGS_CACHED) {
		virt_dev->ring_cache[rings_cached] =
			virt_dev->eps[ep_index].ring;
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		virt_dev->num_rings_cached++;
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		xhci_dbg(xhci, "Cached old ring, "
				"%d ring%s cached\n",
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				virt_dev->num_rings_cached,
				(virt_dev->num_rings_cached > 1) ? "s" : "");
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	} else {
		xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
		xhci_dbg(xhci, "Ring cache full (%d rings), "
				"freeing ring\n",
				virt_dev->num_rings_cached);
	}
	virt_dev->eps[ep_index].ring = NULL;
}

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/* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
 * pointers to the beginning of the ring.
 */
static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
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			struct xhci_ring *ring, unsigned int cycle_state,
			enum xhci_ring_type type)
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{
	struct xhci_segment	*seg = ring->first_seg;
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	int i;

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	do {
		memset(seg->trbs, 0,
				sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
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		if (cycle_state == 0) {
			for (i = 0; i < TRBS_PER_SEGMENT; i++)
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				seg->trbs[i].link.control |=
					cpu_to_le32(TRB_CYCLE);
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		}
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		/* All endpoint rings have link TRBs */
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		xhci_link_segments(xhci, seg, seg->next, type);
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		seg = seg->next;
	} while (seg != ring->first_seg);
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	ring->type = type;
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	xhci_initialize_ring_info(ring, cycle_state);
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	/* td list should be empty since all URBs have been cancelled,
	 * but just in case...
	 */
	INIT_LIST_HEAD(&ring->td_list);
}

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/*
 * Expand an existing ring.
 * Look for a cached ring or allocate a new ring which has same segment numbers
 * and link the two rings.
 */
int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
				unsigned int num_trbs, gfp_t flags)
{
	struct xhci_segment	*first;
	struct xhci_segment	*last;
	unsigned int		num_segs;
	unsigned int		num_segs_needed;
	int			ret;

	num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) /
				(TRBS_PER_SEGMENT - 1);

	/* Allocate number of segments we needed, or double the ring size */
	num_segs = ring->num_segs > num_segs_needed ?
			ring->num_segs : num_segs_needed;

	ret = xhci_alloc_segments_for_ring(xhci, &first, &last,
			num_segs, ring->cycle_state, ring->type, flags);
	if (ret)
		return -ENOMEM;

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	if (ring->type == TYPE_STREAM)
		ret = xhci_update_stream_segment_mapping(ring->trb_address_map,
						ring, first, last, flags);
	if (ret) {
		struct xhci_segment *next;
		do {
			next = first->next;
			xhci_segment_free(xhci, first);
			if (first == last)
				break;
			first = next;
		} while (true);
		return ret;
	}

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	xhci_link_rings(xhci, ring, first, last, num_segs);
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	xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
			"ring expansion succeed, now has %d segments",
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			ring->num_segs);

	return 0;
}

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#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)

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static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
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						    int type, gfp_t flags)
{
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	struct xhci_container_ctx *ctx;

	if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT))
		return NULL;

	ctx = kzalloc(sizeof(*ctx), flags);
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	if (!ctx)
		return NULL;

	ctx->type = type;
	ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
	if (type == XHCI_CTX_TYPE_INPUT)
		ctx->size += CTX_SIZE(xhci->hcc_params);

	ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
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	if (!ctx->bytes) {
		kfree(ctx);
		return NULL;
	}
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	memset(ctx->bytes, 0, ctx->size);
	return ctx;
}

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static void xhci_free_container_ctx(struct xhci_hcd *xhci,
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			     struct xhci_container_ctx *ctx)
{
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	if (!ctx)
		return;
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	dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
	kfree(ctx);
}

struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
					      struct xhci_container_ctx *ctx)
{
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	if (ctx->type != XHCI_CTX_TYPE_INPUT)
		return NULL;

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	return (struct xhci_input_control_ctx *)ctx->bytes;
}

struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
					struct xhci_container_ctx *ctx)
{
	if (ctx->type == XHCI_CTX_TYPE_DEVICE)
		return (struct xhci_slot_ctx *)ctx->bytes;

	return (struct xhci_slot_ctx *)
		(ctx->bytes + CTX_SIZE(xhci->hcc_params));
}

struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
				    struct xhci_container_ctx *ctx,
				    unsigned int ep_index)
{
	/* increment ep index by offset of start of ep ctx array */
	ep_index++;
	if (ctx->type == XHCI_CTX_TYPE_INPUT)
		ep_index++;

	return (struct xhci_ep_ctx *)
		(ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
}

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/***************** Streams structures manipulation *************************/

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static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
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		unsigned int num_stream_ctxs,
		struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
{
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	struct device *dev = xhci_to_hcd(xhci)->self.controller;
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	size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs;
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	if (size > MEDIUM_STREAM_ARRAY_SIZE)
		dma_free_coherent(dev, size,
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				stream_ctx, dma);
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	else if (size <= SMALL_STREAM_ARRAY_SIZE)
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		return dma_pool_free(xhci->small_streams_pool,
				stream_ctx, dma);
	else
		return dma_pool_free(xhci->medium_streams_pool,
				stream_ctx, dma);
}

/*
 * The stream context array for each endpoint with bulk streams enabled can
 * vary in size, based on:
 *  - how many streams the endpoint supports,
 *  - the maximum primary stream array size the host controller supports,
 *  - and how many streams the device driver asks for.
 *
 * The stream context array must be a power of 2, and can be as small as
 * 64 bytes or as large as 1MB.
 */
601
static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
602 603 604
		unsigned int num_stream_ctxs, dma_addr_t *dma,
		gfp_t mem_flags)
{
605
	struct device *dev = xhci_to_hcd(xhci)->self.controller;
606
	size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs;
607

608 609
	if (size > MEDIUM_STREAM_ARRAY_SIZE)
		return dma_alloc_coherent(dev, size,
610
				dma, mem_flags);
611
	else if (size <= SMALL_STREAM_ARRAY_SIZE)
612 613 614 615 616 617 618
		return dma_pool_alloc(xhci->small_streams_pool,
				mem_flags, dma);
	else
		return dma_pool_alloc(xhci->medium_streams_pool,
				mem_flags, dma);
}

619 620 621 622 623 624
struct xhci_ring *xhci_dma_to_transfer_ring(
		struct xhci_virt_ep *ep,
		u64 address)
{
	if (ep->ep_state & EP_HAS_STREAMS)
		return radix_tree_lookup(&ep->stream_info->trb_address_map,
625
				address >> TRB_SEGMENT_SHIFT);
626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645
	return ep->ring;
}

struct xhci_ring *xhci_stream_id_to_ring(
		struct xhci_virt_device *dev,
		unsigned int ep_index,
		unsigned int stream_id)
{
	struct xhci_virt_ep *ep = &dev->eps[ep_index];

	if (stream_id == 0)
		return ep->ring;
	if (!ep->stream_info)
		return NULL;

	if (stream_id > ep->stream_info->num_streams)
		return NULL;
	return ep->stream_info->stream_rings[stream_id];
}

646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710
/*
 * Change an endpoint's internal structure so it supports stream IDs.  The
 * number of requested streams includes stream 0, which cannot be used by device
 * drivers.
 *
 * The number of stream contexts in the stream context array may be bigger than
 * the number of streams the driver wants to use.  This is because the number of
 * stream context array entries must be a power of two.
 */
struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
		unsigned int num_stream_ctxs,
		unsigned int num_streams, gfp_t mem_flags)
{
	struct xhci_stream_info *stream_info;
	u32 cur_stream;
	struct xhci_ring *cur_ring;
	u64 addr;
	int ret;

	xhci_dbg(xhci, "Allocating %u streams and %u "
			"stream context array entries.\n",
			num_streams, num_stream_ctxs);
	if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
		xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
		return NULL;
	}
	xhci->cmd_ring_reserved_trbs++;

	stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
	if (!stream_info)
		goto cleanup_trbs;

	stream_info->num_streams = num_streams;
	stream_info->num_stream_ctxs = num_stream_ctxs;

	/* Initialize the array of virtual pointers to stream rings. */
	stream_info->stream_rings = kzalloc(
			sizeof(struct xhci_ring *)*num_streams,
			mem_flags);
	if (!stream_info->stream_rings)
		goto cleanup_info;

	/* Initialize the array of DMA addresses for stream rings for the HW. */
	stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
			num_stream_ctxs, &stream_info->ctx_array_dma,
			mem_flags);
	if (!stream_info->stream_ctx_array)
		goto cleanup_ctx;
	memset(stream_info->stream_ctx_array, 0,
			sizeof(struct xhci_stream_ctx)*num_stream_ctxs);

	/* Allocate everything needed to free the stream rings later */
	stream_info->free_streams_command =
		xhci_alloc_command(xhci, true, true, mem_flags);
	if (!stream_info->free_streams_command)
		goto cleanup_ctx;

	INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);

	/* Allocate rings for all the streams that the driver will use,
	 * and add their segment DMA addresses to the radix tree.
	 * Stream 0 is reserved.
	 */
	for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
		stream_info->stream_rings[cur_stream] =
711
			xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, mem_flags);
712 713 714
		cur_ring = stream_info->stream_rings[cur_stream];
		if (!cur_ring)
			goto cleanup_rings;
715
		cur_ring->stream_id = cur_stream;
G
Gerd Hoffmann 已提交
716
		cur_ring->trb_address_map = &stream_info->trb_address_map;
717 718 719 720
		/* Set deq ptr, cycle bit, and stream context type */
		addr = cur_ring->first_seg->dma |
			SCT_FOR_CTX(SCT_PRI_TR) |
			cur_ring->cycle_state;
721 722
		stream_info->stream_ctx_array[cur_stream].stream_ring =
			cpu_to_le64(addr);
723 724 725
		xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
				cur_stream, (unsigned long long) addr);

G
Gerd Hoffmann 已提交
726
		ret = xhci_update_stream_mapping(cur_ring, mem_flags);
727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772
		if (ret) {
			xhci_ring_free(xhci, cur_ring);
			stream_info->stream_rings[cur_stream] = NULL;
			goto cleanup_rings;
		}
	}
	/* Leave the other unused stream ring pointers in the stream context
	 * array initialized to zero.  This will cause the xHC to give us an
	 * error if the device asks for a stream ID we don't have setup (if it
	 * was any other way, the host controller would assume the ring is
	 * "empty" and wait forever for data to be queued to that stream ID).
	 */

	return stream_info;

cleanup_rings:
	for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
		cur_ring = stream_info->stream_rings[cur_stream];
		if (cur_ring) {
			xhci_ring_free(xhci, cur_ring);
			stream_info->stream_rings[cur_stream] = NULL;
		}
	}
	xhci_free_command(xhci, stream_info->free_streams_command);
cleanup_ctx:
	kfree(stream_info->stream_rings);
cleanup_info:
	kfree(stream_info);
cleanup_trbs:
	xhci->cmd_ring_reserved_trbs--;
	return NULL;
}
/*
 * Sets the MaxPStreams field and the Linear Stream Array field.
 * Sets the dequeue pointer to the stream context array.
 */
void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
		struct xhci_ep_ctx *ep_ctx,
		struct xhci_stream_info *stream_info)
{
	u32 max_primary_streams;
	/* MaxPStreams is the number of stream context array entries, not the
	 * number we're actually using.  Must be in 2^(MaxPstreams + 1) format.
	 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
	 */
	max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
773 774
	xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,
			"Setting number of stream ctx array entries to %u",
775
			1 << (max_primary_streams + 1));
M
Matt Evans 已提交
776 777 778 779
	ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
	ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
				       | EP_HAS_LSA);
	ep_ctx->deq  = cpu_to_le64(stream_info->ctx_array_dma);
780 781 782 783 784 785 786 787 788 789 790 791
}

/*
 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
 * not at the beginning of the ring).
 */
void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
		struct xhci_ep_ctx *ep_ctx,
		struct xhci_virt_ep *ep)
{
	dma_addr_t addr;
M
Matt Evans 已提交
792
	ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
793
	addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
M
Matt Evans 已提交
794
	ep_ctx->deq  = cpu_to_le64(addr | ep->ring->cycle_state);
795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825
}

/* Frees all stream contexts associated with the endpoint,
 *
 * Caller should fix the endpoint context streams fields.
 */
void xhci_free_stream_info(struct xhci_hcd *xhci,
		struct xhci_stream_info *stream_info)
{
	int cur_stream;
	struct xhci_ring *cur_ring;

	if (!stream_info)
		return;

	for (cur_stream = 1; cur_stream < stream_info->num_streams;
			cur_stream++) {
		cur_ring = stream_info->stream_rings[cur_stream];
		if (cur_ring) {
			xhci_ring_free(xhci, cur_ring);
			stream_info->stream_rings[cur_stream] = NULL;
		}
	}
	xhci_free_command(xhci, stream_info->free_streams_command);
	xhci->cmd_ring_reserved_trbs--;
	if (stream_info->stream_ctx_array)
		xhci_free_stream_ctx(xhci,
				stream_info->num_stream_ctxs,
				stream_info->stream_ctx_array,
				stream_info->ctx_array_dma);

826
	kfree(stream_info->stream_rings);
827 828 829 830 831 832
	kfree(stream_info);
}


/***************** Device context manipulation *************************/

833 834 835 836 837 838 839 840 841
static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
		struct xhci_virt_ep *ep)
{
	init_timer(&ep->stop_cmd_timer);
	ep->stop_cmd_timer.data = (unsigned long) ep;
	ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
	ep->xhci = xhci;
}

842 843 844 845 846
static void xhci_free_tt_info(struct xhci_hcd *xhci,
		struct xhci_virt_device *virt_dev,
		int slot_id)
{
	struct list_head *tt_list_head;
847 848
	struct xhci_tt_bw_info *tt_info, *next;
	bool slot_found = false;
849 850 851 852 853 854 855 856 857 858 859

	/* If the device never made it past the Set Address stage,
	 * it may not have the real_port set correctly.
	 */
	if (virt_dev->real_port == 0 ||
			virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
		xhci_dbg(xhci, "Bad real port.\n");
		return;
	}

	tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
860 861 862 863 864 865 866
	list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
		/* Multi-TT hubs will have more than one entry */
		if (tt_info->slot_id == slot_id) {
			slot_found = true;
			list_del(&tt_info->tt_list);
			kfree(tt_info);
		} else if (slot_found) {
867
			break;
868
		}
869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914
	}
}

int xhci_alloc_tt_info(struct xhci_hcd *xhci,
		struct xhci_virt_device *virt_dev,
		struct usb_device *hdev,
		struct usb_tt *tt, gfp_t mem_flags)
{
	struct xhci_tt_bw_info		*tt_info;
	unsigned int			num_ports;
	int				i, j;

	if (!tt->multi)
		num_ports = 1;
	else
		num_ports = hdev->maxchild;

	for (i = 0; i < num_ports; i++, tt_info++) {
		struct xhci_interval_bw_table *bw_table;

		tt_info = kzalloc(sizeof(*tt_info), mem_flags);
		if (!tt_info)
			goto free_tts;
		INIT_LIST_HEAD(&tt_info->tt_list);
		list_add(&tt_info->tt_list,
				&xhci->rh_bw[virt_dev->real_port - 1].tts);
		tt_info->slot_id = virt_dev->udev->slot_id;
		if (tt->multi)
			tt_info->ttport = i+1;
		bw_table = &tt_info->bw_table;
		for (j = 0; j < XHCI_MAX_INTERVAL; j++)
			INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
	}
	return 0;

free_tts:
	xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
	return -ENOMEM;
}


/* All the xhci_tds in the ring's TD list should be freed at this point.
 * Should be called with xhci->lock held if there is any chance the TT lists
 * will be manipulated by the configure endpoint, allocate device, or update
 * hub functions while this function is removing the TT entries from the list.
 */
915 916 917 918
void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
{
	struct xhci_virt_device *dev;
	int i;
919
	int old_active_eps = 0;
920 921 922 923 924 925

	/* Slot ID 0 is reserved */
	if (slot_id == 0 || !xhci->devs[slot_id])
		return;

	dev = xhci->devs[slot_id];
926
	xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
927 928 929
	if (!dev)
		return;

930 931 932
	if (dev->tt_info)
		old_active_eps = dev->tt_info->active_eps;

933
	for (i = 0; i < 31; ++i) {
934 935
		if (dev->eps[i].ring)
			xhci_ring_free(xhci, dev->eps[i].ring);
936 937 938
		if (dev->eps[i].stream_info)
			xhci_free_stream_info(xhci,
					dev->eps[i].stream_info);
939 940 941 942 943 944 945 946 947
		/* Endpoints on the TT/root port lists should have been removed
		 * when usb_disable_device() was called for the device.
		 * We can't drop them anyway, because the udev might have gone
		 * away by this point, and we can't tell what speed it was.
		 */
		if (!list_empty(&dev->eps[i].bw_endpoint_list))
			xhci_warn(xhci, "Slot %u endpoint %u "
					"not removed from BW list!\n",
					slot_id, i);
948
	}
949 950
	/* If this is a hub, free the TT(s) from the TT list */
	xhci_free_tt_info(xhci, dev, slot_id);
951 952
	/* If necessary, update the number of active TTs on this root port */
	xhci_update_tt_active_eps(xhci, dev, old_active_eps);
953

954 955 956 957 958 959
	if (dev->ring_cache) {
		for (i = 0; i < dev->num_rings_cached; i++)
			xhci_ring_free(xhci, dev->ring_cache[i]);
		kfree(dev->ring_cache);
	}

960
	if (dev->in_ctx)
961
		xhci_free_container_ctx(xhci, dev->in_ctx);
962
	if (dev->out_ctx)
963 964
		xhci_free_container_ctx(xhci, dev->out_ctx);

965
	kfree(xhci->devs[slot_id]);
966
	xhci->devs[slot_id] = NULL;
967 968 969 970 971 972
}

int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
		struct usb_device *udev, gfp_t flags)
{
	struct xhci_virt_device *dev;
973
	int i;
974 975 976 977 978 979 980 981 982 983 984 985

	/* Slot ID 0 is reserved */
	if (slot_id == 0 || xhci->devs[slot_id]) {
		xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
		return 0;
	}

	xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
	if (!xhci->devs[slot_id])
		return 0;
	dev = xhci->devs[slot_id];

986 987
	/* Allocate the (output) device context that will be used in the HC. */
	dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
988 989
	if (!dev->out_ctx)
		goto fail;
990

991
	xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
992
			(unsigned long long)dev->out_ctx->dma);
993 994

	/* Allocate the (input) device context for address device command */
995
	dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
996 997
	if (!dev->in_ctx)
		goto fail;
998

999
	xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
1000
			(unsigned long long)dev->in_ctx->dma);
1001

1002 1003 1004
	/* Initialize the cancellation list and watchdog timers for each ep */
	for (i = 0; i < 31; i++) {
		xhci_init_endpoint_timer(xhci, &dev->eps[i]);
1005
		INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
1006
		INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
1007
	}
1008

1009
	/* Allocate endpoint 0 ring */
1010
	dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, flags);
1011
	if (!dev->eps[0].ring)
1012 1013
		goto fail;

1014 1015 1016 1017 1018 1019 1020 1021
	/* Allocate pointers to the ring cache */
	dev->ring_cache = kzalloc(
			sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
			flags);
	if (!dev->ring_cache)
		goto fail;
	dev->num_rings_cached = 0;

1022
	init_completion(&dev->cmd_completion);
1023
	dev->udev = udev;
1024

1025
	/* Point to output device context in dcbaa. */
M
Matt Evans 已提交
1026
	xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
1027
	xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
M
Matt Evans 已提交
1028 1029
		 slot_id,
		 &xhci->dcbaa->dev_context_ptrs[slot_id],
1030
		 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
1031 1032 1033 1034 1035 1036 1037

	return 1;
fail:
	xhci_free_virt_device(xhci, slot_id);
	return 0;
}

1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054
void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
		struct usb_device *udev)
{
	struct xhci_virt_device *virt_dev;
	struct xhci_ep_ctx	*ep0_ctx;
	struct xhci_ring	*ep_ring;

	virt_dev = xhci->devs[udev->slot_id];
	ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
	ep_ring = virt_dev->eps[0].ring;
	/*
	 * FIXME we don't keep track of the dequeue pointer very well after a
	 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
	 * host to our enqueue pointer.  This should only be called after a
	 * configured device has reset, so all control transfers should have
	 * been completed or cancelled before the reset.
	 */
M
Matt Evans 已提交
1055 1056 1057
	ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
							ep_ring->enqueue)
				   | ep_ring->cycle_state);
1058 1059
}

1060 1061 1062 1063 1064 1065 1066 1067 1068
/*
 * The xHCI roothub may have ports of differing speeds in any order in the port
 * status registers.  xhci->port_array provides an array of the port speed for
 * each offset into the port status registers.
 *
 * The xHCI hardware wants to know the roothub port number that the USB device
 * is attached to (or the roothub port its ancestor hub is attached to).  All we
 * know is the index of that port under either the USB 2.0 or the USB 3.0
 * roothub, but that doesn't give us the real index into the HW port status
1069
 * registers. Call xhci_find_raw_port_number() to get real index.
1070 1071 1072 1073 1074
 */
static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
		struct usb_device *udev)
{
	struct usb_device *top_dev;
1075 1076 1077 1078 1079 1080
	struct usb_hcd *hcd;

	if (udev->speed == USB_SPEED_SUPER)
		hcd = xhci->shared_hcd;
	else
		hcd = xhci->main_hcd;
1081 1082 1083 1084 1085

	for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
			top_dev = top_dev->parent)
		/* Found device below root hub */;

1086
	return	xhci_find_raw_port_number(hcd, top_dev->portnum);
1087 1088
}

1089 1090 1091 1092 1093
/* Setup an xHCI virtual device for a Set Address command */
int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
{
	struct xhci_virt_device *dev;
	struct xhci_ep_ctx	*ep0_ctx;
1094
	struct xhci_slot_ctx    *slot_ctx;
1095
	u32			port_num;
1096
	u32			max_packets;
1097
	struct usb_device *top_dev;
1098 1099 1100 1101 1102 1103 1104 1105

	dev = xhci->devs[udev->slot_id];
	/* Slot ID 0 is reserved */
	if (udev->slot_id == 0 || !dev) {
		xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
				udev->slot_id);
		return -EINVAL;
	}
1106 1107
	ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
	slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1108 1109

	/* 3) Only the control endpoint is valid - one endpoint context */
1110
	slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1111 1112
	switch (udev->speed) {
	case USB_SPEED_SUPER:
1113
		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1114
		max_packets = MAX_PACKET(512);
1115 1116
		break;
	case USB_SPEED_HIGH:
1117
		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1118
		max_packets = MAX_PACKET(64);
1119
		break;
1120
	/* USB core guesses at a 64-byte max packet first for FS devices */
1121
	case USB_SPEED_FULL:
1122
		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1123
		max_packets = MAX_PACKET(64);
1124 1125
		break;
	case USB_SPEED_LOW:
1126
		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1127
		max_packets = MAX_PACKET(8);
1128
		break;
1129
	case USB_SPEED_WIRELESS:
1130 1131 1132 1133 1134
		xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
		return -EINVAL;
		break;
	default:
		/* Speed was set earlier, this shouldn't happen. */
1135
		return -EINVAL;
1136 1137
	}
	/* Find the root hub port this device is under */
1138 1139 1140
	port_num = xhci_find_real_port_number(xhci, udev);
	if (!port_num)
		return -EINVAL;
1141
	slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1142
	/* Set the port number in the virtual_device to the faked port number */
1143 1144 1145
	for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
			top_dev = top_dev->parent)
		/* Found device below root hub */;
1146
	dev->fake_port = top_dev->portnum;
1147
	dev->real_port = port_num;
1148
	xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1149
	xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1150

1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180
	/* Find the right bandwidth table that this device will be a part of.
	 * If this is a full speed device attached directly to a root port (or a
	 * decendent of one), it counts as a primary bandwidth domain, not a
	 * secondary bandwidth domain under a TT.  An xhci_tt_info structure
	 * will never be created for the HS root hub.
	 */
	if (!udev->tt || !udev->tt->hub->parent) {
		dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
	} else {
		struct xhci_root_port_bw_info *rh_bw;
		struct xhci_tt_bw_info *tt_bw;

		rh_bw = &xhci->rh_bw[port_num - 1];
		/* Find the right TT. */
		list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
			if (tt_bw->slot_id != udev->tt->hub->slot_id)
				continue;

			if (!dev->udev->tt->multi ||
					(udev->tt->multi &&
					 tt_bw->ttport == dev->udev->ttport)) {
				dev->bw_table = &tt_bw->bw_table;
				dev->tt_info = tt_bw;
				break;
			}
		}
		if (!dev->tt_info)
			xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
	}

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1181 1182
	/* Is this a LS/FS device under an external HS hub? */
	if (udev->tt && udev->tt->hub->parent) {
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1183 1184
		slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
						(udev->ttport << 8));
1185
		if (udev->tt->multi)
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1186
			slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1187
	}
1188
	xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1189 1190 1191 1192
	xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);

	/* Step 4 - ring already allocated */
	/* Step 5 */
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1193
	ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1194

1195
	/* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1196 1197
	ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) |
					 max_packets);
1198

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1199 1200
	ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
				   dev->eps[0].ring->cycle_state);
1201 1202 1203 1204 1205 1206

	/* Steps 7 and 8 were done in xhci_alloc_virt_device() */

	return 0;
}

1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219
/*
 * Convert interval expressed as 2^(bInterval - 1) == interval into
 * straight exponent value 2^n == interval.
 *
 */
static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
		struct usb_host_endpoint *ep)
{
	unsigned int interval;

	interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
	if (interval != ep->desc.bInterval - 1)
		dev_warn(&udev->dev,
1220
			 "ep %#x - rounding interval to %d %sframes\n",
1221
			 ep->desc.bEndpointAddress,
1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232
			 1 << interval,
			 udev->speed == USB_SPEED_FULL ? "" : "micro");

	if (udev->speed == USB_SPEED_FULL) {
		/*
		 * Full speed isoc endpoints specify interval in frames,
		 * not microframes. We are using microframes everywhere,
		 * so adjust accordingly.
		 */
		interval += 3;	/* 1 frame = 2^3 uframes */
	}
1233 1234 1235 1236 1237

	return interval;
}

/*
1238
 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1239 1240
 * microframes, rounded down to nearest power of 2.
 */
1241 1242 1243
static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
		struct usb_host_endpoint *ep, unsigned int desc_interval,
		unsigned int min_exponent, unsigned int max_exponent)
1244 1245 1246
{
	unsigned int interval;

1247 1248 1249
	interval = fls(desc_interval) - 1;
	interval = clamp_val(interval, min_exponent, max_exponent);
	if ((1 << interval) != desc_interval)
1250 1251 1252 1253
		dev_warn(&udev->dev,
			 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
			 ep->desc.bEndpointAddress,
			 1 << interval,
1254
			 desc_interval);
1255 1256 1257 1258

	return interval;
}

1259 1260 1261
static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
		struct usb_host_endpoint *ep)
{
1262 1263
	if (ep->desc.bInterval == 0)
		return 0;
1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275
	return xhci_microframes_to_exponent(udev, ep,
			ep->desc.bInterval, 0, 15);
}


static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
		struct usb_host_endpoint *ep)
{
	return xhci_microframes_to_exponent(udev, ep,
			ep->desc.bInterval * 8, 3, 10);
}

1276 1277 1278 1279 1280 1281 1282 1283
/* Return the polling or NAK interval.
 *
 * The polling interval is expressed in "microframes".  If xHCI's Interval field
 * is set to N, it will service the endpoint every 2^(Interval)*125us.
 *
 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
 * is set to 0.
 */
1284
static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1285 1286 1287 1288 1289 1290 1291 1292
		struct usb_host_endpoint *ep)
{
	unsigned int interval = 0;

	switch (udev->speed) {
	case USB_SPEED_HIGH:
		/* Max NAK rate */
		if (usb_endpoint_xfer_control(&ep->desc) ||
1293
		    usb_endpoint_xfer_bulk(&ep->desc)) {
1294
			interval = xhci_parse_microframe_interval(udev, ep);
1295 1296
			break;
		}
1297
		/* Fall through - SS and HS isoc/int have same decoding */
1298

1299 1300
	case USB_SPEED_SUPER:
		if (usb_endpoint_xfer_int(&ep->desc) ||
1301 1302
		    usb_endpoint_xfer_isoc(&ep->desc)) {
			interval = xhci_parse_exponent_interval(udev, ep);
1303 1304
		}
		break;
1305

1306
	case USB_SPEED_FULL:
1307
		if (usb_endpoint_xfer_isoc(&ep->desc)) {
1308 1309 1310 1311
			interval = xhci_parse_exponent_interval(udev, ep);
			break;
		}
		/*
1312
		 * Fall through for interrupt endpoint interval decoding
1313 1314 1315 1316
		 * since it uses the same rules as low speed interrupt
		 * endpoints.
		 */

1317 1318
	case USB_SPEED_LOW:
		if (usb_endpoint_xfer_int(&ep->desc) ||
1319 1320 1321
		    usb_endpoint_xfer_isoc(&ep->desc)) {

			interval = xhci_parse_frame_interval(udev, ep);
1322 1323
		}
		break;
1324

1325 1326 1327 1328 1329 1330
	default:
		BUG();
	}
	return EP_INTERVAL(interval);
}

1331
/* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1332 1333 1334 1335
 * High speed endpoint descriptors can define "the number of additional
 * transaction opportunities per microframe", but that goes in the Max Burst
 * endpoint context field.
 */
1336
static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1337 1338
		struct usb_host_endpoint *ep)
{
1339 1340
	if (udev->speed != USB_SPEED_SUPER ||
			!usb_endpoint_xfer_isoc(&ep->desc))
1341
		return 0;
1342
	return ep->ss_ep_comp.bmAttributes;
1343 1344
}

1345
static u32 xhci_get_endpoint_type(struct usb_device *udev,
1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369
		struct usb_host_endpoint *ep)
{
	int in;
	u32 type;

	in = usb_endpoint_dir_in(&ep->desc);
	if (usb_endpoint_xfer_control(&ep->desc)) {
		type = EP_TYPE(CTRL_EP);
	} else if (usb_endpoint_xfer_bulk(&ep->desc)) {
		if (in)
			type = EP_TYPE(BULK_IN_EP);
		else
			type = EP_TYPE(BULK_OUT_EP);
	} else if (usb_endpoint_xfer_isoc(&ep->desc)) {
		if (in)
			type = EP_TYPE(ISOC_IN_EP);
		else
			type = EP_TYPE(ISOC_OUT_EP);
	} else if (usb_endpoint_xfer_int(&ep->desc)) {
		if (in)
			type = EP_TYPE(INT_IN_EP);
		else
			type = EP_TYPE(INT_OUT_EP);
	} else {
1370
		type = 0;
1371 1372 1373 1374
	}
	return type;
}

1375 1376 1377 1378
/* Return the maximum endpoint service interval time (ESIT) payload.
 * Basically, this is the maxpacket size, multiplied by the burst size
 * and mult size.
 */
1379
static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390
		struct usb_device *udev,
		struct usb_host_endpoint *ep)
{
	int max_burst;
	int max_packet;

	/* Only applies for interrupt or isochronous endpoints */
	if (usb_endpoint_xfer_control(&ep->desc) ||
			usb_endpoint_xfer_bulk(&ep->desc))
		return 0;

1391
	if (udev->speed == USB_SPEED_SUPER)
1392
		return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1393

1394 1395
	max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
	max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1396 1397 1398 1399
	/* A 0 in max burst means 1 transfer per ESIT */
	return max_packet * (max_burst + 1);
}

1400 1401 1402
/* Set up an endpoint with one ring segment.  Do not allocate stream rings.
 * Drivers will have to call usb_alloc_streams() to do that.
 */
1403 1404 1405
int xhci_endpoint_init(struct xhci_hcd *xhci,
		struct xhci_virt_device *virt_dev,
		struct usb_device *udev,
1406 1407
		struct usb_host_endpoint *ep,
		gfp_t mem_flags)
1408 1409 1410 1411 1412 1413
{
	unsigned int ep_index;
	struct xhci_ep_ctx *ep_ctx;
	struct xhci_ring *ep_ring;
	unsigned int max_packet;
	unsigned int max_burst;
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1414
	enum xhci_ring_type type;
1415
	u32 max_esit_payload;
1416
	u32 endpoint_type;
1417 1418

	ep_index = xhci_get_endpoint_index(&ep->desc);
1419
	ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1420

1421 1422 1423 1424 1425
	endpoint_type = xhci_get_endpoint_type(udev, ep);
	if (!endpoint_type)
		return -EINVAL;
	ep_ctx->ep_info2 = cpu_to_le32(endpoint_type);

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1426
	type = usb_endpoint_type(&ep->desc);
1427
	/* Set up the endpoint ring */
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1428
	virt_dev->eps[ep_index].new_ring =
1429
		xhci_ring_alloc(xhci, 2, 1, type, mem_flags);
1430 1431 1432 1433 1434 1435 1436 1437
	if (!virt_dev->eps[ep_index].new_ring) {
		/* Attempt to use the ring cache */
		if (virt_dev->num_rings_cached == 0)
			return -ENOMEM;
		virt_dev->eps[ep_index].new_ring =
			virt_dev->ring_cache[virt_dev->num_rings_cached];
		virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
		virt_dev->num_rings_cached--;
1438
		xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
1439
					1, type);
1440
	}
1441
	virt_dev->eps[ep_index].skip = false;
1442
	ep_ring = virt_dev->eps[ep_index].new_ring;
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1443
	ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1444

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1445 1446
	ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
				      | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1447 1448 1449

	/* FIXME dig Mult and streams info out of ep companion desc */

1450
	/* Allow 3 retries for everything but isoc;
1451
	 * CErr shall be set to 0 for Isoch endpoints.
1452
	 */
1453
	if (!usb_endpoint_xfer_isoc(&ep->desc))
1454
		ep_ctx->ep_info2 |= cpu_to_le32(ERROR_COUNT(3));
1455
	else
1456
		ep_ctx->ep_info2 |= cpu_to_le32(ERROR_COUNT(0));
1457 1458

	/* Set the max packet size and max burst */
1459 1460
	max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
	max_burst = 0;
1461 1462
	switch (udev->speed) {
	case USB_SPEED_SUPER:
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Sarah Sharp 已提交
1463
		/* dig out max burst from ep companion desc */
1464
		max_burst = ep->ss_ep_comp.bMaxBurst;
1465 1466
		break;
	case USB_SPEED_HIGH:
1467 1468 1469
		/* Some devices get this wrong */
		if (usb_endpoint_xfer_bulk(&ep->desc))
			max_packet = 512;
1470 1471 1472 1473 1474
		/* bits 11:12 specify the number of additional transaction
		 * opportunities per microframe (USB 2.0, section 9.6.6)
		 */
		if (usb_endpoint_xfer_isoc(&ep->desc) ||
				usb_endpoint_xfer_int(&ep->desc)) {
1475
			max_burst = (usb_endpoint_maxp(&ep->desc)
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1476
				     & 0x1800) >> 11;
1477
		}
1478
		break;
1479 1480 1481 1482 1483 1484
	case USB_SPEED_FULL:
	case USB_SPEED_LOW:
		break;
	default:
		BUG();
	}
1485 1486
	ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet) |
			MAX_BURST(max_burst));
1487
	max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
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1488
	ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503

	/*
	 * XXX no idea how to calculate the average TRB buffer length for bulk
	 * endpoints, as the driver gives us no clue how big each scatter gather
	 * list entry (or buffer) is going to be.
	 *
	 * For isochronous and interrupt endpoints, we set it to the max
	 * available, until we have new API in the USB core to allow drivers to
	 * declare how much bandwidth they actually need.
	 *
	 * Normally, it would be calculated by taking the total of the buffer
	 * lengths in the TD and then dividing by the number of TRBs in a TD,
	 * including link TRBs, No-op TRBs, and Event data TRBs.  Since we don't
	 * use Event Data TRBs, and we don't chain in a link TRB on short
	 * transfers, we're basically dividing by 1.
1504 1505 1506
	 *
	 * xHCI 1.0 specification indicates that the Average TRB Length should
	 * be set to 8 for control endpoints.
1507
	 */
1508 1509 1510 1511 1512
	if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
		ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
	else
		ep_ctx->tx_info |=
			 cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1513

1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525
	/* FIXME Debug endpoint context */
	return 0;
}

void xhci_endpoint_zero(struct xhci_hcd *xhci,
		struct xhci_virt_device *virt_dev,
		struct usb_host_endpoint *ep)
{
	unsigned int ep_index;
	struct xhci_ep_ctx *ep_ctx;

	ep_index = xhci_get_endpoint_index(&ep->desc);
1526
	ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1527 1528 1529

	ep_ctx->ep_info = 0;
	ep_ctx->ep_info2 = 0;
1530
	ep_ctx->deq = 0;
1531 1532 1533 1534 1535 1536
	ep_ctx->tx_info = 0;
	/* Don't free the endpoint ring until the set interface or configuration
	 * request succeeds.
	 */
}

1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583
void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
{
	bw_info->ep_interval = 0;
	bw_info->mult = 0;
	bw_info->num_packets = 0;
	bw_info->max_packet_size = 0;
	bw_info->type = 0;
	bw_info->max_esit_payload = 0;
}

void xhci_update_bw_info(struct xhci_hcd *xhci,
		struct xhci_container_ctx *in_ctx,
		struct xhci_input_control_ctx *ctrl_ctx,
		struct xhci_virt_device *virt_dev)
{
	struct xhci_bw_info *bw_info;
	struct xhci_ep_ctx *ep_ctx;
	unsigned int ep_type;
	int i;

	for (i = 1; i < 31; ++i) {
		bw_info = &virt_dev->eps[i].bw_info;

		/* We can't tell what endpoint type is being dropped, but
		 * unconditionally clearing the bandwidth info for non-periodic
		 * endpoints should be harmless because the info will never be
		 * set in the first place.
		 */
		if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
			/* Dropped endpoint */
			xhci_clear_endpoint_bw_info(bw_info);
			continue;
		}

		if (EP_IS_ADDED(ctrl_ctx, i)) {
			ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
			ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));

			/* Ignore non-periodic endpoints */
			if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
					ep_type != ISOC_IN_EP &&
					ep_type != INT_IN_EP)
				continue;

			/* Added or changed endpoint */
			bw_info->ep_interval = CTX_TO_EP_INTERVAL(
					le32_to_cpu(ep_ctx->ep_info));
1584 1585 1586
			/* Number of packets and mult are zero-based in the
			 * input context, but we want one-based for the
			 * interval table.
1587
			 */
1588 1589
			bw_info->mult = CTX_TO_EP_MULT(
					le32_to_cpu(ep_ctx->ep_info)) + 1;
1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600
			bw_info->num_packets = CTX_TO_MAX_BURST(
					le32_to_cpu(ep_ctx->ep_info2)) + 1;
			bw_info->max_packet_size = MAX_PACKET_DECODED(
					le32_to_cpu(ep_ctx->ep_info2));
			bw_info->type = ep_type;
			bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
					le32_to_cpu(ep_ctx->tx_info));
		}
	}
}

1601 1602 1603 1604 1605
/* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
 * Useful when you want to change one particular aspect of the endpoint and then
 * issue a configure endpoint command.
 */
void xhci_endpoint_copy(struct xhci_hcd *xhci,
1606 1607 1608
		struct xhci_container_ctx *in_ctx,
		struct xhci_container_ctx *out_ctx,
		unsigned int ep_index)
1609 1610 1611 1612
{
	struct xhci_ep_ctx *out_ep_ctx;
	struct xhci_ep_ctx *in_ep_ctx;

1613 1614
	out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
	in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626

	in_ep_ctx->ep_info = out_ep_ctx->ep_info;
	in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
	in_ep_ctx->deq = out_ep_ctx->deq;
	in_ep_ctx->tx_info = out_ep_ctx->tx_info;
}

/* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
 * Useful when you want to change one particular aspect of the endpoint and then
 * issue a configure endpoint command.  Only the context entries field matters,
 * but we'll copy the whole thing anyway.
 */
1627 1628 1629
void xhci_slot_copy(struct xhci_hcd *xhci,
		struct xhci_container_ctx *in_ctx,
		struct xhci_container_ctx *out_ctx)
1630 1631 1632 1633
{
	struct xhci_slot_ctx *in_slot_ctx;
	struct xhci_slot_ctx *out_slot_ctx;

1634 1635
	in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
	out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1636 1637 1638 1639 1640 1641 1642

	in_slot_ctx->dev_info = out_slot_ctx->dev_info;
	in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
	in_slot_ctx->tt_info = out_slot_ctx->tt_info;
	in_slot_ctx->dev_state = out_slot_ctx->dev_state;
}

1643 1644 1645 1646 1647 1648 1649
/* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
{
	int i;
	struct device *dev = xhci_to_hcd(xhci)->self.controller;
	int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);

1650 1651
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"Allocating %d scratchpad buffers", num_sp);
1652 1653 1654 1655 1656 1657 1658 1659

	if (!num_sp)
		return 0;

	xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
	if (!xhci->scratchpad)
		goto fail_sp;

1660
	xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1661
				     num_sp * sizeof(u64),
1662
				     &xhci->scratchpad->sp_dma, flags);
1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675
	if (!xhci->scratchpad->sp_array)
		goto fail_sp2;

	xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
	if (!xhci->scratchpad->sp_buffers)
		goto fail_sp3;

	xhci->scratchpad->sp_dma_buffers =
		kzalloc(sizeof(dma_addr_t) * num_sp, flags);

	if (!xhci->scratchpad->sp_dma_buffers)
		goto fail_sp4;

M
Matt Evans 已提交
1676
	xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1677 1678
	for (i = 0; i < num_sp; i++) {
		dma_addr_t dma;
1679 1680
		void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
				flags);
1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692
		if (!buf)
			goto fail_sp5;

		xhci->scratchpad->sp_array[i] = dma;
		xhci->scratchpad->sp_buffers[i] = buf;
		xhci->scratchpad->sp_dma_buffers[i] = dma;
	}

	return 0;

 fail_sp5:
	for (i = i - 1; i >= 0; i--) {
1693
		dma_free_coherent(dev, xhci->page_size,
1694 1695 1696 1697 1698 1699 1700 1701 1702
				    xhci->scratchpad->sp_buffers[i],
				    xhci->scratchpad->sp_dma_buffers[i]);
	}
	kfree(xhci->scratchpad->sp_dma_buffers);

 fail_sp4:
	kfree(xhci->scratchpad->sp_buffers);

 fail_sp3:
1703
	dma_free_coherent(dev, num_sp * sizeof(u64),
1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718
			    xhci->scratchpad->sp_array,
			    xhci->scratchpad->sp_dma);

 fail_sp2:
	kfree(xhci->scratchpad);
	xhci->scratchpad = NULL;

 fail_sp:
	return -ENOMEM;
}

static void scratchpad_free(struct xhci_hcd *xhci)
{
	int num_sp;
	int i;
1719
	struct device *dev = xhci_to_hcd(xhci)->self.controller;
1720 1721 1722 1723 1724 1725 1726

	if (!xhci->scratchpad)
		return;

	num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);

	for (i = 0; i < num_sp; i++) {
1727
		dma_free_coherent(dev, xhci->page_size,
1728 1729 1730 1731 1732
				    xhci->scratchpad->sp_buffers[i],
				    xhci->scratchpad->sp_dma_buffers[i]);
	}
	kfree(xhci->scratchpad->sp_dma_buffers);
	kfree(xhci->scratchpad->sp_buffers);
1733
	dma_free_coherent(dev, num_sp * sizeof(u64),
1734 1735 1736 1737 1738 1739
			    xhci->scratchpad->sp_array,
			    xhci->scratchpad->sp_dma);
	kfree(xhci->scratchpad);
	xhci->scratchpad = NULL;
}

1740
struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1741 1742
		bool allocate_in_ctx, bool allocate_completion,
		gfp_t mem_flags)
1743 1744 1745 1746 1747 1748 1749
{
	struct xhci_command *command;

	command = kzalloc(sizeof(*command), mem_flags);
	if (!command)
		return NULL;

1750 1751 1752 1753 1754 1755 1756 1757
	if (allocate_in_ctx) {
		command->in_ctx =
			xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
					mem_flags);
		if (!command->in_ctx) {
			kfree(command);
			return NULL;
		}
1758
	}
1759 1760 1761 1762 1763 1764

	if (allocate_completion) {
		command->completion =
			kzalloc(sizeof(struct completion), mem_flags);
		if (!command->completion) {
			xhci_free_container_ctx(xhci, command->in_ctx);
1765
			kfree(command);
1766 1767 1768 1769 1770 1771 1772 1773 1774 1775
			return NULL;
		}
		init_completion(command->completion);
	}

	command->status = 0;
	INIT_LIST_HEAD(&command->cmd_list);
	return command;
}

1776 1777
void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
{
A
Andiry Xu 已提交
1778 1779 1780
	if (urb_priv) {
		kfree(urb_priv->td[0]);
		kfree(urb_priv);
1781 1782 1783
	}
}

1784 1785 1786 1787 1788 1789 1790 1791 1792
void xhci_free_command(struct xhci_hcd *xhci,
		struct xhci_command *command)
{
	xhci_free_container_ctx(xhci,
			command->in_ctx);
	kfree(command->completion);
	kfree(command);
}

1793 1794
void xhci_mem_cleanup(struct xhci_hcd *xhci)
{
1795
	struct device	*dev = xhci_to_hcd(xhci)->self.controller;
1796
	struct xhci_cd  *cur_cd, *next_cd;
1797
	int size;
1798
	int i, j, num_ports;
1799 1800 1801 1802

	/* Free the Event Ring Segment Table and the actual Event Ring */
	size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
	if (xhci->erst.entries)
1803
		dma_free_coherent(dev, size,
1804 1805
				xhci->erst.entries, xhci->erst.erst_dma_addr);
	xhci->erst.entries = NULL;
1806
	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed ERST");
1807 1808 1809
	if (xhci->event_ring)
		xhci_ring_free(xhci, xhci->event_ring);
	xhci->event_ring = NULL;
1810
	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed event ring");
1811

1812 1813
	if (xhci->lpm_command)
		xhci_free_command(xhci, xhci->lpm_command);
1814 1815 1816
	if (xhci->cmd_ring)
		xhci_ring_free(xhci, xhci->cmd_ring);
	xhci->cmd_ring = NULL;
1817
	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed command ring");
1818 1819 1820 1821 1822
	list_for_each_entry_safe(cur_cd, next_cd,
			&xhci->cancel_cmd_list, cancel_cmd_list) {
		list_del(&cur_cd->cancel_cmd_list);
		kfree(cur_cd);
	}
M
Mathias Nyman 已提交
1823
	xhci_cleanup_command_queue(xhci);
1824 1825 1826 1827

	for (i = 1; i < MAX_HC_SLOTS; ++i)
		xhci_free_virt_device(xhci, i);

1828 1829 1830
	if (xhci->segment_pool)
		dma_pool_destroy(xhci->segment_pool);
	xhci->segment_pool = NULL;
1831
	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed segment pool");
1832 1833 1834 1835

	if (xhci->device_pool)
		dma_pool_destroy(xhci->device_pool);
	xhci->device_pool = NULL;
1836
	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed device context pool");
1837

1838 1839 1840
	if (xhci->small_streams_pool)
		dma_pool_destroy(xhci->small_streams_pool);
	xhci->small_streams_pool = NULL;
1841 1842
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"Freed small stream array pool");
1843 1844 1845 1846

	if (xhci->medium_streams_pool)
		dma_pool_destroy(xhci->medium_streams_pool);
	xhci->medium_streams_pool = NULL;
1847 1848
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"Freed medium stream array pool");
1849

1850
	if (xhci->dcbaa)
1851
		dma_free_coherent(dev, sizeof(*xhci->dcbaa),
1852 1853
				xhci->dcbaa, xhci->dcbaa->dma);
	xhci->dcbaa = NULL;
1854

1855
	scratchpad_free(xhci);
1856

1857 1858 1859
	if (!xhci->rh_bw)
		goto no_bw;

1860 1861 1862 1863 1864 1865 1866
	num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
	for (i = 0; i < num_ports; i++) {
		struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
		for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
			struct list_head *ep = &bwt->interval_bw[j].endpoints;
			while (!list_empty(ep))
				list_del_init(ep->next);
1867 1868 1869
		}
	}

1870 1871 1872 1873 1874 1875
	for (i = 0; i < num_ports; i++) {
		struct xhci_tt_bw_info *tt, *n;
		list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
			list_del(&tt->tt_list);
			kfree(tt);
		}
1876 1877
	}

1878
no_bw:
1879
	xhci->cmd_ring_reserved_trbs = 0;
1880 1881
	xhci->num_usb2_ports = 0;
	xhci->num_usb3_ports = 0;
1882
	xhci->num_active_eps = 0;
1883 1884 1885
	kfree(xhci->usb2_ports);
	kfree(xhci->usb3_ports);
	kfree(xhci->port_array);
1886
	kfree(xhci->rh_bw);
1887
	kfree(xhci->ext_caps);
1888

1889 1890
	xhci->page_size = 0;
	xhci->page_shift = 0;
1891
	xhci->bus_state[0].bus_suspended = 0;
1892
	xhci->bus_state[1].bus_suspended = 0;
1893 1894
}

1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021
static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
		struct xhci_segment *input_seg,
		union xhci_trb *start_trb,
		union xhci_trb *end_trb,
		dma_addr_t input_dma,
		struct xhci_segment *result_seg,
		char *test_name, int test_number)
{
	unsigned long long start_dma;
	unsigned long long end_dma;
	struct xhci_segment *seg;

	start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
	end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);

	seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
	if (seg != result_seg) {
		xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
				test_name, test_number);
		xhci_warn(xhci, "Tested TRB math w/ seg %p and "
				"input DMA 0x%llx\n",
				input_seg,
				(unsigned long long) input_dma);
		xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
				"ending TRB %p (0x%llx DMA)\n",
				start_trb, start_dma,
				end_trb, end_dma);
		xhci_warn(xhci, "Expected seg %p, got seg %p\n",
				result_seg, seg);
		return -1;
	}
	return 0;
}

/* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
{
	struct {
		dma_addr_t		input_dma;
		struct xhci_segment	*result_seg;
	} simple_test_vector [] = {
		/* A zeroed DMA field should fail */
		{ 0, NULL },
		/* One TRB before the ring start should fail */
		{ xhci->event_ring->first_seg->dma - 16, NULL },
		/* One byte before the ring start should fail */
		{ xhci->event_ring->first_seg->dma - 1, NULL },
		/* Starting TRB should succeed */
		{ xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
		/* Ending TRB should succeed */
		{ xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
			xhci->event_ring->first_seg },
		/* One byte after the ring end should fail */
		{ xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
		/* One TRB after the ring end should fail */
		{ xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
		/* An address of all ones should fail */
		{ (dma_addr_t) (~0), NULL },
	};
	struct {
		struct xhci_segment	*input_seg;
		union xhci_trb		*start_trb;
		union xhci_trb		*end_trb;
		dma_addr_t		input_dma;
		struct xhci_segment	*result_seg;
	} complex_test_vector [] = {
		/* Test feeding a valid DMA address from a different ring */
		{	.input_seg = xhci->event_ring->first_seg,
			.start_trb = xhci->event_ring->first_seg->trbs,
			.end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
			.input_dma = xhci->cmd_ring->first_seg->dma,
			.result_seg = NULL,
		},
		/* Test feeding a valid end TRB from a different ring */
		{	.input_seg = xhci->event_ring->first_seg,
			.start_trb = xhci->event_ring->first_seg->trbs,
			.end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
			.input_dma = xhci->cmd_ring->first_seg->dma,
			.result_seg = NULL,
		},
		/* Test feeding a valid start and end TRB from a different ring */
		{	.input_seg = xhci->event_ring->first_seg,
			.start_trb = xhci->cmd_ring->first_seg->trbs,
			.end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
			.input_dma = xhci->cmd_ring->first_seg->dma,
			.result_seg = NULL,
		},
		/* TRB in this ring, but after this TD */
		{	.input_seg = xhci->event_ring->first_seg,
			.start_trb = &xhci->event_ring->first_seg->trbs[0],
			.end_trb = &xhci->event_ring->first_seg->trbs[3],
			.input_dma = xhci->event_ring->first_seg->dma + 4*16,
			.result_seg = NULL,
		},
		/* TRB in this ring, but before this TD */
		{	.input_seg = xhci->event_ring->first_seg,
			.start_trb = &xhci->event_ring->first_seg->trbs[3],
			.end_trb = &xhci->event_ring->first_seg->trbs[6],
			.input_dma = xhci->event_ring->first_seg->dma + 2*16,
			.result_seg = NULL,
		},
		/* TRB in this ring, but after this wrapped TD */
		{	.input_seg = xhci->event_ring->first_seg,
			.start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
			.end_trb = &xhci->event_ring->first_seg->trbs[1],
			.input_dma = xhci->event_ring->first_seg->dma + 2*16,
			.result_seg = NULL,
		},
		/* TRB in this ring, but before this wrapped TD */
		{	.input_seg = xhci->event_ring->first_seg,
			.start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
			.end_trb = &xhci->event_ring->first_seg->trbs[1],
			.input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
			.result_seg = NULL,
		},
		/* TRB not in this ring, and we have a wrapped TD */
		{	.input_seg = xhci->event_ring->first_seg,
			.start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
			.end_trb = &xhci->event_ring->first_seg->trbs[1],
			.input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
			.result_seg = NULL,
		},
	};

	unsigned int num_tests;
	int i, ret;

2022
	num_tests = ARRAY_SIZE(simple_test_vector);
2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034
	for (i = 0; i < num_tests; i++) {
		ret = xhci_test_trb_in_td(xhci,
				xhci->event_ring->first_seg,
				xhci->event_ring->first_seg->trbs,
				&xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
				simple_test_vector[i].input_dma,
				simple_test_vector[i].result_seg,
				"Simple", i);
		if (ret < 0)
			return ret;
	}

2035
	num_tests = ARRAY_SIZE(complex_test_vector);
2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050
	for (i = 0; i < num_tests; i++) {
		ret = xhci_test_trb_in_td(xhci,
				complex_test_vector[i].input_seg,
				complex_test_vector[i].start_trb,
				complex_test_vector[i].end_trb,
				complex_test_vector[i].input_dma,
				complex_test_vector[i].result_seg,
				"Complex", i);
		if (ret < 0)
			return ret;
	}
	xhci_dbg(xhci, "TRB math tests passed.\n");
	return 0;
}

2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061
static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
{
	u64 temp;
	dma_addr_t deq;

	deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
			xhci->event_ring->dequeue);
	if (deq == 0 && !in_interrupt())
		xhci_warn(xhci, "WARN something wrong with SW event ring "
				"dequeue ptr.\n");
	/* Update HC event ring dequeue pointer */
2062
	temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2063 2064 2065 2066 2067
	temp &= ERST_PTR_MASK;
	/* Don't clear the EHB bit (which is RW1C) because
	 * there might be more events to service.
	 */
	temp &= ~ERST_EHB;
2068 2069 2070
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"// Write event ring dequeue pointer, "
			"preserving EHB bit");
2071
	xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
2072 2073 2074
			&xhci->ir_set->erst_dequeue);
}

2075
static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2076
		__le32 __iomem *addr, u8 major_revision, int max_caps)
2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089
{
	u32 temp, port_offset, port_count;
	int i;

	if (major_revision > 0x03) {
		xhci_warn(xhci, "Ignoring unknown port speed, "
				"Ext Cap %p, revision = 0x%x\n",
				addr, major_revision);
		/* Ignoring port protocol we can't understand. FIXME */
		return;
	}

	/* Port offset and count in the third dword, see section 7.2 */
2090
	temp = readl(addr + 2);
2091 2092
	port_offset = XHCI_EXT_PORT_OFF(temp);
	port_count = XHCI_EXT_PORT_COUNT(temp);
2093 2094 2095
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"Ext Cap %p, port offset = %u, "
			"count = %u, revision = 0x%x",
2096 2097 2098 2099 2100
			addr, port_offset, port_count, major_revision);
	/* Port count includes the current port offset */
	if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
		/* WTF? "Valid values are ‘1’ to MaxPorts" */
		return;
A
Andiry Xu 已提交
2101

2102 2103 2104 2105
	/* cache usb2 port capabilities */
	if (major_revision < 0x03 && xhci->num_ext_caps < max_caps)
		xhci->ext_caps[xhci->num_ext_caps++] = temp;

A
Andiry Xu 已提交
2106 2107 2108
	/* Check the host's USB2 LPM capability */
	if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
			(temp & XHCI_L1C)) {
2109 2110
		xhci_dbg_trace(xhci, trace_xhci_dbg_init,
				"xHCI 0.96: support USB2 software lpm");
A
Andiry Xu 已提交
2111 2112 2113 2114
		xhci->sw_lpm_support = 1;
	}

	if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
2115 2116
		xhci_dbg_trace(xhci, trace_xhci_dbg_init,
				"xHCI 1.0: support USB2 software lpm");
A
Andiry Xu 已提交
2117 2118
		xhci->sw_lpm_support = 1;
		if (temp & XHCI_HLC) {
2119 2120
			xhci_dbg_trace(xhci, trace_xhci_dbg_init,
					"xHCI 1.0: support USB2 hardware lpm");
A
Andiry Xu 已提交
2121 2122 2123 2124
			xhci->hw_lpm_support = 1;
		}
	}

2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137
	port_offset--;
	for (i = port_offset; i < (port_offset + port_count); i++) {
		/* Duplicate entry.  Ignore the port if the revisions differ. */
		if (xhci->port_array[i] != 0) {
			xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
					" port %u\n", addr, i);
			xhci_warn(xhci, "Port was marked as USB %u, "
					"duplicated as USB %u\n",
					xhci->port_array[i], major_revision);
			/* Only adjust the roothub port counts if we haven't
			 * found a similar duplicate.
			 */
			if (xhci->port_array[i] != major_revision &&
2138
				xhci->port_array[i] != DUPLICATE_ENTRY) {
2139 2140 2141 2142
				if (xhci->port_array[i] == 0x03)
					xhci->num_usb3_ports--;
				else
					xhci->num_usb2_ports--;
2143
				xhci->port_array[i] = DUPLICATE_ENTRY;
2144 2145
			}
			/* FIXME: Should we disable the port? */
2146
			continue;
2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165
		}
		xhci->port_array[i] = major_revision;
		if (major_revision == 0x03)
			xhci->num_usb3_ports++;
		else
			xhci->num_usb2_ports++;
	}
	/* FIXME: Should we disable ports not in the Extended Capabilities? */
}

/*
 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
 * specify what speeds each port is supposed to be.  We can't count on the port
 * speed bits in the PORTSC register being correct until a device is connected,
 * but we need to set up the two fake roothubs with the correct number of USB
 * 3.0 and USB 2.0 ports at host controller initialization time.
 */
static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
{
2166 2167
	__le32 __iomem *addr, *tmp_addr;
	u32 offset, tmp_offset;
2168
	unsigned int num_ports;
2169
	int i, j, port_index;
2170
	int cap_count = 0;
2171 2172

	addr = &xhci->cap_regs->hcc_params;
2173
	offset = XHCI_HCC_EXT_CAPS(readl(addr));
2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184
	if (offset == 0) {
		xhci_err(xhci, "No Extended Capability registers, "
				"unable to set up roothub.\n");
		return -ENODEV;
	}

	num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
	xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
	if (!xhci->port_array)
		return -ENOMEM;

2185 2186 2187
	xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
	if (!xhci->rh_bw)
		return -ENOMEM;
2188 2189 2190
	for (i = 0; i < num_ports; i++) {
		struct xhci_interval_bw_table *bw_table;

2191
		INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2192 2193 2194 2195
		bw_table = &xhci->rh_bw[i].bw_table;
		for (j = 0; j < XHCI_MAX_INTERVAL; j++)
			INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
	}
2196

2197 2198 2199 2200 2201 2202
	/*
	 * For whatever reason, the first capability offset is from the
	 * capability register base, not from the HCCPARAMS register.
	 * See section 5.3.6 for offset calculation.
	 */
	addr = &xhci->cap_regs->hc_capbase + offset;
2203 2204 2205 2206 2207 2208 2209

	tmp_addr = addr;
	tmp_offset = offset;

	/* count extended protocol capability entries for later caching */
	do {
		u32 cap_id;
2210
		cap_id = readl(tmp_addr);
2211 2212 2213 2214 2215 2216 2217 2218 2219 2220
		if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
			cap_count++;
		tmp_offset = XHCI_EXT_CAPS_NEXT(cap_id);
		tmp_addr += tmp_offset;
	} while (tmp_offset);

	xhci->ext_caps = kzalloc(sizeof(*xhci->ext_caps) * cap_count, flags);
	if (!xhci->ext_caps)
		return -ENOMEM;

2221 2222 2223
	while (1) {
		u32 cap_id;

2224
		cap_id = readl(addr);
2225 2226
		if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
			xhci_add_in_port(xhci, num_ports, addr,
2227 2228
					(u8) XHCI_EXT_PORT_MAJOR(cap_id),
					cap_count);
2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243
		offset = XHCI_EXT_CAPS_NEXT(cap_id);
		if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
				== num_ports)
			break;
		/*
		 * Once you're into the Extended Capabilities, the offset is
		 * always relative to the register holding the offset.
		 */
		addr += offset;
	}

	if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
		xhci_warn(xhci, "No ports on the roothubs?\n");
		return -ENODEV;
	}
2244 2245
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"Found %u USB 2.0 ports and %u USB 3.0 ports.",
2246
			xhci->num_usb2_ports, xhci->num_usb3_ports);
2247 2248 2249 2250 2251

	/* Place limits on the number of roothub ports so that the hub
	 * descriptors aren't longer than the USB core will allocate.
	 */
	if (xhci->num_usb3_ports > 15) {
2252 2253
		xhci_dbg_trace(xhci, trace_xhci_dbg_init,
				"Limiting USB 3.0 roothub ports to 15.");
2254 2255 2256
		xhci->num_usb3_ports = 15;
	}
	if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2257 2258
		xhci_dbg_trace(xhci, trace_xhci_dbg_init,
				"Limiting USB 2.0 roothub ports to %u.",
2259 2260 2261 2262
				USB_MAXCHILDREN);
		xhci->num_usb2_ports = USB_MAXCHILDREN;
	}

2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273
	/*
	 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
	 * Not sure how the USB core will handle a hub with no ports...
	 */
	if (xhci->num_usb2_ports) {
		xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
				xhci->num_usb2_ports, flags);
		if (!xhci->usb2_ports)
			return -ENOMEM;

		port_index = 0;
2274 2275 2276
		for (i = 0; i < num_ports; i++) {
			if (xhci->port_array[i] == 0x03 ||
					xhci->port_array[i] == 0 ||
2277
					xhci->port_array[i] == DUPLICATE_ENTRY)
2278 2279 2280 2281 2282
				continue;

			xhci->usb2_ports[port_index] =
				&xhci->op_regs->port_status_base +
				NUM_PORT_REGS*i;
2283 2284 2285
			xhci_dbg_trace(xhci, trace_xhci_dbg_init,
					"USB 2.0 port at index %u, "
					"addr = %p", i,
2286 2287
					xhci->usb2_ports[port_index]);
			port_index++;
2288 2289
			if (port_index == xhci->num_usb2_ports)
				break;
2290
		}
2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303
	}
	if (xhci->num_usb3_ports) {
		xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
				xhci->num_usb3_ports, flags);
		if (!xhci->usb3_ports)
			return -ENOMEM;

		port_index = 0;
		for (i = 0; i < num_ports; i++)
			if (xhci->port_array[i] == 0x03) {
				xhci->usb3_ports[port_index] =
					&xhci->op_regs->port_status_base +
					NUM_PORT_REGS*i;
2304 2305 2306
				xhci_dbg_trace(xhci, trace_xhci_dbg_init,
						"USB 3.0 port at index %u, "
						"addr = %p", i,
2307 2308
						xhci->usb3_ports[port_index]);
				port_index++;
2309 2310
				if (port_index == xhci->num_usb3_ports)
					break;
2311 2312 2313 2314
			}
	}
	return 0;
}
2315

2316 2317
int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
{
2318 2319
	dma_addr_t	dma;
	struct device	*dev = xhci_to_hcd(xhci)->self.controller;
2320
	unsigned int	val, val2;
2321
	u64		val_64;
2322
	struct xhci_segment	*seg;
2323
	u32 page_size, temp;
2324 2325
	int i;

2326
	INIT_LIST_HEAD(&xhci->cancel_cmd_list);
M
Mathias Nyman 已提交
2327
	INIT_LIST_HEAD(&xhci->cmd_list);
2328

2329
	page_size = readl(&xhci->op_regs->page_size);
2330 2331
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"Supported page size register = 0x%x", page_size);
2332 2333 2334 2335 2336 2337
	for (i = 0; i < 16; i++) {
		if ((0x1 & page_size) != 0)
			break;
		page_size = page_size >> 1;
	}
	if (i < 16)
2338 2339
		xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"Supported page size of %iK", (1 << (i+12)) / 1024);
2340 2341 2342 2343 2344
	else
		xhci_warn(xhci, "WARN: no supported page size\n");
	/* Use 4K pages, since that's common and the minimum the HC supports */
	xhci->page_shift = 12;
	xhci->page_size = 1 << xhci->page_shift;
2345 2346
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"HCD page size set to %iK", xhci->page_size / 1024);
2347 2348 2349 2350 2351

	/*
	 * Program the Number of Device Slots Enabled field in the CONFIG
	 * register with the max value of slots the HC can handle.
	 */
2352
	val = HCS_MAX_SLOTS(readl(&xhci->cap_regs->hcs_params1));
2353 2354
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"// xHC can handle at most %d device slots.", val);
2355
	val2 = readl(&xhci->op_regs->config_reg);
2356
	val |= (val2 & ~HCS_SLOTS_MASK);
2357 2358
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"// Setting Max device slots reg = 0x%x.", val);
2359
	writel(val, &xhci->op_regs->config_reg);
2360

2361 2362 2363 2364
	/*
	 * Section 5.4.8 - doorbell array must be
	 * "physically contiguous and 64-byte (cache line) aligned".
	 */
2365 2366
	xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
			GFP_KERNEL);
2367 2368 2369 2370
	if (!xhci->dcbaa)
		goto fail;
	memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
	xhci->dcbaa->dma = dma;
2371 2372
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"// Device context base array address = 0x%llx (DMA), %p (virt)",
2373
			(unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2374
	xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2375

2376 2377 2378
	/*
	 * Initialize the ring segment pool.  The ring must be a contiguous
	 * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
2379 2380 2381
	 * however, the command ring segment needs 64-byte aligned segments
	 * and our use of dma addresses in the trb_address_map radix tree needs
	 * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
2382 2383
	 */
	xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2384
			TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size);
2385

2386 2387
	/* See Table 46 and Note on Figure 55 */
	xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2388
			2112, 64, xhci->page_size);
2389
	if (!xhci->segment_pool || !xhci->device_pool)
2390 2391
		goto fail;

2392 2393 2394 2395 2396 2397 2398 2399 2400 2401
	/* Linear stream context arrays don't have any boundary restrictions,
	 * and only need to be 16-byte aligned.
	 */
	xhci->small_streams_pool =
		dma_pool_create("xHCI 256 byte stream ctx arrays",
			dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
	xhci->medium_streams_pool =
		dma_pool_create("xHCI 1KB stream ctx arrays",
			dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
	/* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2402
	 * will be allocated with dma_alloc_coherent()
2403 2404 2405 2406 2407
	 */

	if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
		goto fail;

2408
	/* Set up the command ring to have one segments for now. */
2409
	xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags);
2410 2411
	if (!xhci->cmd_ring)
		goto fail;
2412 2413 2414
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"Allocated command ring at %p", xhci->cmd_ring);
	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%llx",
2415
			(unsigned long long)xhci->cmd_ring->first_seg->dma);
2416 2417

	/* Set the address in the Command Ring Control register */
2418
	val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2419 2420
	val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
		(xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2421
		xhci->cmd_ring->cycle_state;
2422 2423
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"// Setting command ring address to 0x%x", val);
2424
	xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2425 2426
	xhci_dbg_cmd_ptrs(xhci);

2427 2428 2429 2430 2431 2432 2433 2434 2435 2436
	xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags);
	if (!xhci->lpm_command)
		goto fail;

	/* Reserve one command ring TRB for disabling LPM.
	 * Since the USB core grabs the shared usb_bus bandwidth mutex before
	 * disabling LPM, we only need to reserve one TRB for all devices.
	 */
	xhci->cmd_ring_reserved_trbs++;

2437
	val = readl(&xhci->cap_regs->db_off);
2438
	val &= DBOFF_MASK;
2439 2440 2441
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"// Doorbell array is located at offset 0x%x"
			" from cap regs base addr", val);
2442
	xhci->dba = (void __iomem *) xhci->cap_regs + val;
2443 2444 2445
	xhci_dbg_regs(xhci);
	xhci_print_run_regs(xhci);
	/* Set ir_set to interrupt register set 0 */
2446
	xhci->ir_set = &xhci->run_regs->ir_set[0];
2447 2448 2449 2450 2451

	/*
	 * Event ring setup: Allocate a normal ring, but also setup
	 * the event ring segment table (ERST).  Section 4.9.3.
	 */
2452
	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Allocating event ring");
2453
	xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,
2454
						flags);
2455 2456
	if (!xhci->event_ring)
		goto fail;
2457 2458
	if (xhci_check_trb_in_td_math(xhci, flags) < 0)
		goto fail;
2459

2460 2461 2462
	xhci->erst.entries = dma_alloc_coherent(dev,
			sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
			GFP_KERNEL);
2463 2464
	if (!xhci->erst.entries)
		goto fail;
2465 2466
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"// Allocated event ring segment table at 0x%llx",
2467
			(unsigned long long)dma);
2468 2469 2470 2471

	memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
	xhci->erst.num_entries = ERST_NUM_SEGS;
	xhci->erst.erst_dma_addr = dma;
2472 2473
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx",
2474
			xhci->erst.num_entries,
2475 2476
			xhci->erst.entries,
			(unsigned long long)xhci->erst.erst_dma_addr);
2477 2478 2479 2480

	/* set ring base address and size for each segment table entry */
	for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
		struct xhci_erst_entry *entry = &xhci->erst.entries[val];
M
Matt Evans 已提交
2481 2482
		entry->seg_addr = cpu_to_le64(seg->dma);
		entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2483 2484 2485 2486 2487
		entry->rsvd = 0;
		seg = seg->next;
	}

	/* set ERST count with the number of entries in the segment table */
2488
	val = readl(&xhci->ir_set->erst_size);
2489 2490
	val &= ERST_SIZE_MASK;
	val |= ERST_NUM_SEGS;
2491 2492
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"// Write ERST size = %i to ir_set 0 (some bits preserved)",
2493
			val);
2494
	writel(val, &xhci->ir_set->erst_size);
2495

2496 2497
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"// Set ERST entries to point to event ring.");
2498
	/* set the segment table base address */
2499 2500
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"// Set ERST base address for ir_set 0 = 0x%llx",
2501
			(unsigned long long)xhci->erst.erst_dma_addr);
2502
	val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2503 2504
	val_64 &= ERST_PTR_MASK;
	val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2505
	xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2506 2507

	/* Set the event ring dequeue address */
2508
	xhci_set_hc_event_deq(xhci);
2509 2510
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
			"Wrote ERST address to ir_set 0.");
2511
	xhci_print_ir_set(xhci, 0);
2512 2513 2514 2515 2516 2517

	/*
	 * XXX: Might need to set the Interrupter Moderation Register to
	 * something other than the default (~1ms minimum between interrupts).
	 * See section 5.5.1.2.
	 */
2518 2519
	init_completion(&xhci->addr_dev);
	for (i = 0; i < MAX_HC_SLOTS; ++i)
2520
		xhci->devs[i] = NULL;
2521
	for (i = 0; i < USB_MAXCHILDREN; ++i) {
2522
		xhci->bus_state[0].resume_done[i] = 0;
2523
		xhci->bus_state[1].resume_done[i] = 0;
2524 2525
		/* Only the USB 2.0 completions will ever be used. */
		init_completion(&xhci->bus_state[1].rexit_done[i]);
2526
	}
2527

2528 2529
	if (scratchpad_alloc(xhci, flags))
		goto fail;
2530 2531
	if (xhci_setup_port_arrays(xhci, flags))
		goto fail;
2532

2533 2534 2535 2536
	/* Enable USB 3.0 device notifications for function remote wake, which
	 * is necessary for allowing USB 3.0 devices to do remote wakeup from
	 * U3 (device suspend).
	 */
2537
	temp = readl(&xhci->op_regs->dev_notification);
2538 2539
	temp &= ~DEV_NOTE_MASK;
	temp |= DEV_NOTE_FWAKE;
2540
	writel(temp, &xhci->op_regs->dev_notification);
2541

2542
	return 0;
2543

2544 2545
fail:
	xhci_warn(xhci, "Couldn't initialize memory\n");
2546 2547
	xhci_halt(xhci);
	xhci_reset(xhci);
2548 2549 2550
	xhci_mem_cleanup(xhci);
	return -ENOMEM;
}